KR19990061134A - Sub word line decoder - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention is to provide a sub word line decoder configured to facilitate a metal process and to prevent an increase in standby current in a standby state even if the metal lines are shorted to each other.

To this end, the present invention, a plurality of pull-up elements and a plurality of pull-up elements and a ground terminal are formed between the main word line and a plurality of sub word lines to drive the corresponding sub word line by different word line boosting signal By having a plurality of pull-down elements formed between and driven by the different word lines boosted by the inverted word line boosting signals, the number of metal lines is reduced to 1/4 of the metal strapping method as in PMOS. The process is easy, and even if the metal lines are shorted to each other, the standby current does not increase because the metal lines are held at the same potential in the standby state, thereby increasing the yield by operating normally after the repair.

Description

Sub word line decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sub word line decoder applied to a semiconductor memory device such as DRAM, and more particularly, to a sub word line decoder configured to prevent a standby current increase during a metal word line short circuit. will be.

In semiconductor memory devices such as DRAM, polycrystalline silicon is generally used as a gate of a cell transistor.

However, since the polycrystalline silicon is a high resistance material, the resistance is also quite large. This slows down signal transmission from the X-decoder to cells far away.

In order to compensate for this drawback, metal strapping is used. As the integration becomes higher, the space between the metal and the metal becomes narrower, which makes it difficult to proceed with the process.

A sub-line under a hierarchical word line structure in which word lines are divided into appropriate lengths to form sub-word lines, and these sub-word lines are driven by a single row decoder and a word line decoder. The word line decoder method reduces the number of metal lines to half or less, thereby facilitating the process.

Conventional sub-word line decoder methods use CMOS and NMOS. In the CMOS method, metal lines are reduced to one-quarter compared to metal strapping, which facilitates metal processing and Even when shorted to each other, the standby current does not increase because the metal lines are held at the same potential in the standby state. However, since the PMOS is used, a separate N-Well requires a large area.

In the case of using the NMOS, for example, as shown in FIG. 1, the sub word line driver 10 includes a plurality of transfer gates T1 and T2 commonly connected to the main word line, which is a metal line. , T3, T4 and the main word line signal passing through each of the transfer gates T1, T2, T3, and T4 to control the word line boosting signal to the corresponding sub word lines WL0, WL1, WL2, and WL3. NMOS transistors (N1, N3, N5, N7) as a plurality of pull-up elements to be applied to each other, and are provided between the respective NMOS transistors (N1, N3, N5, N7) and the ground terminal, It is composed of NMOS transistors N2, N4, N6, and N8 as pull-down elements that drive the corresponding subword lines WL0, WL1, WL2, and WL3 by the signals of the main word lines.

In the conventional sub word line decoder using the NMOS structure, the gate line of the pull-up element and the gate line of the pull-down element are metal lines, and since the metal lines are always placed at different potentials, the metal lines may be shorted to each other. In this case, the standby current increases and even if repairing, the commodity value is lost.

Accordingly, an object of the present invention is to provide a sub word line decoder configured to solve the above-mentioned problems and to prevent an increase in standby current in a standby state even when the metal process is easy and the metal lines are shorted to each other. .

In order to achieve the above object, a sub word line decoder according to the present invention includes a plurality of pull-ups in which a channel is formed between a main word line and a plurality of sub word lines to drive the corresponding sub word line by different word line boosting signals. And a plurality of pull-down elements formed between the plurality of pull-up elements and the ground terminal to drive the corresponding sub word line by the inverted word line boosting signals.

1 is an internal circuit diagram of a conventional sub word line decoder;

2 is a circuit diagram illustrating a configuration of a sub word line decoder according to an exemplary embodiment of the present invention.

Explanation of symbols for main parts of the drawings

10: sub word line decoder T1 to T8: transfer gate

N1 to N16: NMOS transistors WL0 to WL3: Sub word line

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram illustrating a configuration of a sub word line decoder according to an exemplary embodiment of the present invention, wherein the main word line MWL is a metal line and a sub word line commonly connected to the main word line MWL. NMOS transistors N9, N11, N13, and N15 as pull-up elements are provided between WL0 to WL3.

Each of the NMOS transistors N9, N11, N13, and N15 has word line boosting signals PX + 0, PX + 1, PX + 2, and PX + 3 through respective transfer gates T5, T6, T7, and T8. Drive the respective sub word lines WL0 to WL3.

NMOS transistors N10, N12, N14, and N16 as pull-down elements are provided between the NMOS transistors N9, N11, N13, and N15 and the ground terminal, and the respective NMOS transistors N10, N12, N14, N16 drives each of the sub word lines WL0 to WL3 by the inverted word line boosting signals PX + 0b, PX + 1b, PX + 2b, and PX + 3b.

Here, the word line boosting signals PX + 0b, PX + 1b, PX + 2b, and PX + 3b that are inverted from the word line boosting signals PX + 0, PX + 1, PX + 2, and PX + 3 are words. A signal output from a line boosting signal generating circuit (not shown).

Next, an operation of the sub word line decoder according to the embodiment of the present invention configured as described above will be described.

First, when the word line boosting signal PX + is low VSS and the signal of the main word line MWL is low VSS, the PX + b signal becomes high VCC, so the pull-up device is turned off and the pull-down device is turned off. Comes on. Accordingly, a low level potential is applied to the sub word line.

When the word line boosting signal PX + is high VCC and the signal of the main word line MWL is low VSS, the PX + b signal is low VSS, so the pull-up device is turned on and the pull-down device is turned on. Is off. Accordingly, a low level potential is applied to the sub word line.

When the word line boosting signal PX + is low VSS and the signal of the main word line MWL is high VPP, the PX + b signal becomes high VCC, so the pull-up device is turned off and the pull-down device is turned off. Comes on. Accordingly, a low level potential is applied to the sub word line.

Finally, when the word line boosting signal PX + is high (VCC) and the main word line MWL signal is high (VPP), the PX + b signal becomes low (VSS), so the pull-up element is on and pulls down. The device is turned off. As a result, a high level (to sufficiently turn on the cell transistor) of the high level (VPP) VCC + VT is applied to the sub word line.

Accordingly, four sub word lines WL0, WL1, WL2, and WL3 can be selectively driven. For example, when driving the sub word line WL0, four word line boosting signals PX + 0 and PX can be driven. Among the +1, PX + 2, and PX + 3, only the PX + 0 signal is high (VCC) and the remaining PX + signals (ie, PX + 1, PX + 2, PX + 3) are low and the main word line ( When the signal of the MWL becomes high (VPP), the high potential VPP is transmitted only to the sub word line WL0.

In the case of driving another sub word line, a high potential is transmitted to the corresponding sub word line by inputting a signal corresponding thereto.

According to the present invention as described above, since the sub word line decoder is only NMOS, not only does it occupy the same area as the conventional NMOS method, but also the number of metal lines is 1/4 of the metal strapping method as in the case of PMOS. It is reduced and the metal process is easy.

In addition, even if the metal lines are shorted to each other, since the metal lines are held at the same potential in the standby state, the standby current does not increase and repairs normally. As a result, the yield is increased.

On the other hand, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (3)

A plurality of pull-up elements having a channel formed between the main word line and the plurality of sub word lines to drive the corresponding sub word line by different word line boosting signals; And a plurality of pull-down elements formed between the plurality of pull-up elements and the ground terminal and driving the corresponding sub-word lines by different inverted word line boosting signals. The sub word line decoder of claim 1, wherein the pull-up device and the pull-down device each comprise an NMOS transistor. The sub word line decoder of claim 1, wherein when the sub word line is driven, a voltage equal to or greater than VCC + VT (VCC is a power supply voltage and VT is a threshold voltage of a cell transistor) is applied to the sub word line.