KR100213215B1 - Sub-word line driver control signal generating circuit - Google Patents

Abstract

The present invention relates to a sub word line driver control signal generation circuit of a semiconductor memory device. The present invention provides a sub word line decoder for outputting a first control signal, a level shifter for outputting a second control signal with an output of the sub word line decoder, and a third control signal with an output of the level shifter as an input. By providing a first inverter for outputting the semiconductor chip size is reduced and the reliability of the transistors of the sub word line decoder is improved.

Description

Sub wordline driver control signal generation circuit of semiconductor memory device

The present invention relates to a sub word line driver control signal generation circuit of a semiconductor memory device, and more particularly, to a sub word line driver control signal generation circuit of a semiconductor memory autonomous for improving the reliability of a highly integrated semiconductor memory device.

As the popularity of computers increases, the memory capacity of semiconductor memory devices that are responsible for storing data of computers increases. As the capacity of the semiconductor memory device is increased, the degree of integration of the semiconductor memory device is increased, and thus circuits for controlling the memory cell array are also diversified. One example is the sub wordline driver. Although only a word line driver was needed when the memory capacity of the semiconductor memory device was small, a sub word line driver was developed to assist the word line driver as the memory capacity increased. As the sub word line driver was developed, control signal generation circuits for controlling them were also developed, which is a sub word line driver control signal generation circuit of a semiconductor memory device. Further, researches for reducing the size of a semiconductor memory device are continuing, and the present invention provides a method for reducing the area occupied by circuits for controlling a sub wordline driver.

1 is a circuit diagram illustrating a sub word line driver control signal of a conventional semiconductor memory device. 1 is divided into a sub wordline decoder 11 and a predecoder 13. The sub wordline decoder 11 is arranged in a row decoder area 3 of the semiconductor chip 1, and the predecoder 13 is a connection area 5 of the semiconductor chip 1. Are arranged in. The sub word line decoder 11 includes a NAND gate 15 for inputting an address signal A0 and A1 and a block selection signal, and a level shifter 17 for inputting an output of the NAND gate 15. And a first inverter 19 connected to the output terminal of the level shifter 17. The predecoder 13 may include a second inverter 21 and a third inverter 23 connected in series to an output terminal of the first inverter 19, and a fourth inverter connected to an output terminal of the first inverter 19. 25) and a fifth inverter (27).

The PXi signal is generated at the output terminal of the first inverter 19 to drive the predecoder 13. A sub wordline driver (FIG. 2) is connected to an output terminal of the predecoder 13, and three signals are required to drive the sub wordline driver (FIG. 2). It is PXiB, PXiD1, and PXiD2. PXiB is output from the second inverter 21, PXiD1 is output from the fifth inverter 27, and PXiD2 is output from the third inverter 23.

As described above, the PXiD2 is output through the third inverter 23. In order to reduce the size of the semiconductor chip, it is required to reduce the number of inverters of the predecoder 13. Since PXi is driven at the Vpp level, the reliability of transistors of the sub wordline decoder 11 generating PXi is degraded.

An object of the present invention is to provide a sub word line driver control signal generation circuit of a semiconductor memory device for reducing the size of a semiconductor chip.

1 is a circuit diagram of a sub word line driver control signal of a conventional semiconductor memory device.

2 is a circuit diagram of a sub word line driver of a semiconductor memory device.

3 is a circuit diagram of a sub word line driver control signal generation of a semiconductor memory device according to the present invention;

In order to achieve the above object, the present invention provides a sub word line decoder for outputting a first control signal, a level shifter for outputting a second control signal with an output of the sub word line decoder, and an output of the level shifter. The present invention provides a sub word line driver control signal generation circuit of a semiconductor memory device having a first inverter for outputting a third control signal.

Preferably, the sub word line driver includes a NAND gate as an input for an address signal for selecting a word line, a block selection signal for selecting a memory cell, and a second inverter for inputting an output of the NAND gate. The level shifter may include a first NMOS transistor having a gate connected to an output terminal of the sub word line decoder and a source connected to a ground, a first PMOS transistor having a drain connected to a drain of the first NMOS transistor and a source connected to Vpp; A second PMOS transistor having a gate connected to the drain of the first PMOS transistor and a source connected to Vpp, a second NMOS transistor having a drain connected to the drain of the second PMOS transistor, and having a source grounded; An output terminal is connected to the gate of the input terminal, and an input terminal is connected to the gate of the first NMOS transistor. It is composed of a third inverter.

The first control signal, the second control signal, and the third control signal are signals for controlling a sub word line driver for driving a word line driver.

In addition, the sub wordline decoder is disposed in the row decoder region, and the predecoder is disposed in the connection region.

According to the present invention, the area of the semiconductor chip is reduced and the reliability of the transistors of the sub word line decoder is improved.

Hereinafter, the present invention will be described in detail through examples.

2 is a circuit diagram of a sub word line driver of a semiconductor memory device. The circuit of FIG. 2 is composed of four NMOS transistors, that is, a first NMOS transistor 41, a second NMOS transistor 43, a third NMOS transistor 45, and a fourth NMOS transistor 47. The drain of the first NMOS transistor 41 is connected to MWL, which is a main word line, and the gate is connected to Vcc, which is a power source. The gate of the second NMOS transistor 43 is connected to the source of the first NMOS transistor 41, and the drain thereof is connected to PXiD1, which is the first control signal. The drain of the third NMOS transistor 45 is connected to the drain of the first NMOS transistor 41 and the gate is connected to PXiD2 which is a second control signal. A drain of the fourth NMOS transistor 47 is connected to a source of the third NMOS transistor 45 and a source of the second NMOS transistor 43 through a node N, and a gate thereof is connected to PXiB as a third control signal. It is. A word line WL is connected to the node N.

The operation of FIG. 2 will be described. In order for the word line WL to be enabled, the MWL must be logic high. When MWL becomes logic high, the source of the first NMOS transistor 41 becomes (Vcc-Vt) to conduct the second NMOS transistor 43. Here, Vt is a threshold voltage of the first NMOS transistor 41. As the second NMOS transistor 43 becomes conductive, WL becomes Vpp and is enabled. This is because when PXiD1 is enabled, it becomes Vpp. At this time, the fourth NMOS transistor 47 is turned off because PXiB is disabled.

PXiB must be enabled for WL to be disabled. When PXiB is enabled, the fourth NMOS transistor 47 is turned on so that WL is grounded and disabled.

3 is a circuit for generating a first control signal, a second control signal, and a third control signal for driving the sub word line driver shown in FIG. 2. In Fig. 3, the same numerals as in Fig. 1 denote the same elements. 3 is divided into a sub word line decoder 51 and a predecoder 53. The sub word line decoder 51 may include a NAND gate 55 for inputting an address signal A0 and A1 and a block select signal, and a second inverter for outputting a PXi signal using the output of the NAND gate 55 as an input ( 57).

The sub word line decoder 51 is disposed in the row decoder region 3 of the semiconductor chip 1, and the predecoder 53 is disposed in the connection region 5 of the semiconductor 1. By arranging as shown in FIG. 3, the row decoder region 3 is greatly reduced, and the connection region 5 is also reduced compared to the prior art, thereby reducing the size of the semiconductor chip 1 as a whole.

The predecoder 53 has a level shifter 61 for outputting the second control signal PXiB as an input of the output of the second inverter 57 and an input terminal connected to an output terminal of the level shifter 61. It consists of the 1st inverter 63 which outputs PXiD1 which is 3 control signals.

The level shifter 61 has a gate connected to an output terminal of the sub word line decoder 51 and a source connected to a ground of the first NMOS transistor 71 and a drain connected to a drain of the first NMOS transistor 71. A first PMOS transistor 73 having a source connected to Vpp, a second PMOS transistor 75 having a gate connected to the drain of the first PMOS transistor 73, and a source connected to Vpp, and the second PMOS transistor 75 Drain is connected to the drain of the source and the source is grounded to the gate of the second NMOS transistor 77 and the second NMOS transistor 77, the input terminal is connected to the gate of the first NMOS transistor (71) It consists of three inverters 65.

Here, the power supply of the first inverter 63 is Vpp, and the power supply of the second inverter 57 and the third inverter 65 is Vcc. By doing so, Vcc is supplied when PXiD2 and PXiB are enabled as in the prior art, and Vpp is supplied when PXiD1 is enabled. Therefore, three inverters of the inverters 19, 21, 23, 25, and 27 shown in FIG. 1 are not required, thereby reducing the size of the semiconductor chip.

An operation of the circuit of FIG. 3 for driving the sub wordline driver of FIG. 2 will be described. PXiD1 must be enabled and PXiB must be disabled to enable the word line WL of FIG. 2. To do so, A0, A1 and the block select signal must be enabled. When A0, A1 and the block select signal are enabled, the output of the second inverter 57 becomes Vcc and PXiD2 is enabled. At the same time, since the first NMOS transistor 71 of the level shifter 61 of FIG. 3 is turned on so that the output of the first inverter 63 becomes logic high, PXiD1 is enabled at the Vpp level by the first inverter 63. In addition, PXiB is disabled by the third inverter 65. As described above, since PXiB is disabled and PXiD1 and PXiD2 are enabled, WL is enabled as described in the operation of FIG. 2.

In order to disable WL, as described in FIG. 2, PXiB must be enabled to conduct the fourth NMOS transistor 47 of FIG. 2. To enable PXiB, only one of A0, A1, and the block select signal need to be at a logic low level. For example, if A0 is at a logic low level, the output of the NAND gate 55 is at a logic high. As a result, the output of the second inverter 57 goes logic low and the output of the third inverter 65 goes logic high to enable PXiB. Therefore, the fourth NMOS transistor 47 of FIG. 2 conducts and WL is disabled.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, according to the present invention, since the number of inverters of the predecoder 53 can be reduced, the size of the semiconductor chip is reduced by that much. In addition, since PXi is driven at the Vcc level, the reliability of the transistors of the sub wordline decoder 51 is improved.

Claims (6)

A sub wordline decoder for outputting a first control signal; A level shifter configured to output a second control signal using the output of the sub word line decoder as an input; And a first inverter configured to output a third control signal by using the output of the level shifter as an input. The NAND gate of claim 1, wherein the sub word line driver comprises a NAND gate as an input for an address signal for selecting a word line, a block selection signal for selecting a memory cell, and a second inverter for inputting an output of the NAND gate. And a sub word line driver control signal generation circuit of the semiconductor memory device. The first NMOS transistor of claim 1, wherein the level shifter has a gate connected to an output terminal of the sub word line decoder and a source connected to a ground, a drain connected to a drain of the first NMOS transistor, and a source connected to Vpp. A first PMOS transistor, a second PMOS transistor having a gate connected to the drain of the first PMOS transistor, and a source connected to Vpp, a second NMOS transistor having a drain connected to the drain of the second PMOS transistor and the source grounded; And a third inverter having an output terminal connected to a gate of a second NMOS transistor and an input terminal connected to a gate of the first NMOS transistor. The sub wordline driver control of the semiconductor memory device according to claim 1, wherein the first control signal, the second control signal, and the third control signal are signals for controlling a sub wordline driver for driving a wordline driver. Signal generating circuit. 2. The circuit of claim 1, wherein the sub word line decoder is disposed in a row decoder region. The sub word line driver control signal generation circuit of claim 1, wherein the predecoder is disposed in a connection region.