KR19990060812A - Method of forming a contact hole in a semiconductor device - Google Patents
Method of forming a contact hole in a semiconductor device Download PDFInfo
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- KR19990060812A KR19990060812A KR1019970081058A KR19970081058A KR19990060812A KR 19990060812 A KR19990060812 A KR 19990060812A KR 1019970081058 A KR1019970081058 A KR 1019970081058A KR 19970081058 A KR19970081058 A KR 19970081058A KR 19990060812 A KR19990060812 A KR 19990060812A
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- contact hole
- etching process
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- dry etching
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 238000001312 dry etching Methods 0.000 claims description 19
- 229910052731 fluorine Inorganic materials 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 claims description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000009835 boiling Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000007864 aqueous solution Substances 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 101001027622 Homo sapiens Protein adenylyltransferase FICD Proteins 0.000 description 1
- -1 LTO Chemical compound 0.000 description 1
- 102100037689 Protein adenylyltransferase FICD Human genes 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 콘택 홀 형성 방법에 관한 것이다.The present invention relates to a method of forming a contact hole in a semiconductor device.
자기 정렬 콘택 홀을 반도체 소자에 적용하게 될 경우 콘택 홀과 도전체 라인과의 자기 정렬 과정에서 콘택 홀 영역의 감소가 불가피하며, 하부에 형성된 도전체 패턴 및 절연막이 다층으로 구성될 경우 하나의 도전체 패턴 및 절연막마다 1회씩 콘택을 형성하는 스택 콘택 구조를 채용해야 한다. 이때 상부 콘택과 하부 콘택의 마스크 정렬 마진을 확보하기 위하여 하부 콘택 홀 플러그의 윗부분을 크게 해주기 위해 별도의 플러그 패턴 형성 공정을 거치거나 하부 콘택 홀의 윗부분 또는 전체를 넓혀 주는 별도의 공정이 필요해진다.When a self-aligned contact hole is applied to a semiconductor device, it is inevitable to reduce the contact hole area in the process of self-alignment between the contact hole and the conductive line. In the case where the conductive pattern formed at the lower portion and the insulating film are composed of multiple layers, A stack contact structure in which a contact is formed once for each sieve pattern and for an insulating film should be adopted. At this time, in order to secure the mask alignment margin of the upper contact and the lower contact, a separate plug pattern forming process is performed to enlarge the upper portion of the lower contact hole plug, or a separate process of widening the upper or the whole of the lower contact hole is required.
본 발명에서는 하부의 층간 절연막에 건식 경사 식각 공정을 실시하여 하부 콘택 홀을 형성하고 연속적으로 도전층 측벽에 형성된 스페이서에 대해 높은 식각 선택비를 갖는 등방성 식각을 실시하여 하부 콘택 홀의 상부 폭을 증대시킨다.In the present invention, the lower interlayer insulating film is dry etched to form a lower contact hole, and isotropic etching is continuously performed on the spacer formed on the side wall of the conductive layer to increase the upper width of the lower contact hole .
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 경사 식각 방법 및 선택 식각 방법에 의해 자기 정렬 콘택 패턴을 형성하면서 후속 플러그 형성시 플러그 사이즈를 확대할 수 있는 반도체 소자의 콘택 홀 형성 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact hole in a semiconductor device capable of enlarging a plug size in forming a self-aligned contact pattern by a tilted etching method and a selective etching method.
반도체 소자의 고집적도화에 따라 소자의 최소 설계 한계가 급격히 감소되므로 노광 장비의 한계보다 작은 미세 패턴의 형성이 요구된다.Since the minimum design limit of the device is drastically reduced due to the highly integrated semiconductor device, formation of a fine pattern smaller than the limit of the exposure equipment is required.
그러나 콘택 홀 패턴(contact hole pattern)의 경우 비록 0.1㎛ 이하의 미세 콘택 홀의 형성이 가능하더라도 소자의 전기적 특성면에서 너무 작은 홀 사이즈는 콘택 저항의 증가를 유발한다.However, in the case of a contact hole pattern, a hole size that is too small in terms of the electrical characteristics of the device causes an increase in contact resistance, even though formation of a fine contact hole of 0.1 탆 or less is possible.
이에 따라 여러 가지 형태의 자기 정렬 콘택(self align contact) 형성 방법이 제시되고 있다. 특히 질화막 장벽(nitride barrier) 자기 정렬 콘택 구조의 경우 통상적인 콘택 형성 방법에 비해 적은 공정으로 자기 정렬을 성취할 수 있다.Accordingly, various types of methods for forming a self align contact have been proposed. In particular, a nitride barrier self-aligned contact structure can achieve self-alignment with fewer processes than conventional contact formation methods.
그러나, 이러한 질화막 장벽 자기 정렬 콘택 형성 방법은 질화막에 대한 높은 선택비를 얻기 위해 많은 양의 폴리머(polymer)를 이용하며, 이에 따라 콘택을 형성하기 위한 식각 공정시 폴리머로 인한 식각 멈춤(etch stop)을 동시에 조절해야 하는 매우 까다로운 방법이다.However, such a nitride barrier self-aligned contact formation method uses a large amount of polymer to obtain a high selectivity to a nitride film, and thus etch stop due to the polymer during the etching process for forming a contact, This is a very tricky way to adjust the speed at the same time.
한편, 자기 정렬 콘택 홀을 반도체 소자에 적용하게 될 경우 콘택 홀과 도전체 라인과의 자기 정렬 과정에서 콘택 홀 영역의 감소가 불가피한데, 하부에 형성된 도전체 패턴이 다층일 경우 이러한 과정을 2회 이상 반복해야 하므로 사실상 콘택 영역 확보가 불가능해진다. 따라서 하나의 도전체 패턴/절연층마다 1회씩 콘택을 형성하는 스택 콘택(stack contact) 구조를 채용해야 한다. 이때 상부 콘택과 하부 콘택의 마스크 정렬 마진(mask align margin)을 확보하기 위하여 하부 콘택 홀 플러그(contact hole plug)의 윗부분을 크게 해주어야 한다. 그리고, 플러그의 크기를 확보하기 위하여는 별도의 플러그 패턴 형성 공정을 거치거나 또는 하부 콘택 홀의 윗부분 또는 전체를 넓혀 주는 별도의 공정이 필요해진다.On the other hand, when a self-aligned contact hole is applied to a semiconductor device, it is inevitable to reduce the contact hole area in the process of self-alignment between the contact hole and the conductor line. It is impossible to secure the contact area. Therefore, a stack contact structure that forms a contact once for each conductor pattern / insulating layer must be employed. At this time, the upper portion of the lower contact hole plug should be enlarged to secure a mask align margin between the upper contact and the lower contact. Further, in order to secure the size of the plug, a separate step of forming a separate plug pattern or widening the upper portion or the entire lower contact hole is required.
따라서, 본 발명은 콘택 홀의 면적과 플러그의 크기를 확보하는 동시에 하부 도전층에 대해 자기 정렬을 이룰 수 있는 반도체 소자의 콘택 홀 형성 방법을 제공하는데 그 목적이 있다.Accordingly, it is an object of the present invention to provide a method of forming a contact hole in a semiconductor device, which can ensure the size of the contact hole and the size of the plug, while achieving self alignment of the lower conductive layer.
상술한 목적을 달성하기 위한 본 발명은 반도체 기판 상부의 선택된 영역에 형성된 제 1 도전층 상부에 제 1 절연막을 형성한 후 상기 제 1 도전층 및 제 1 절연막의 측벽에 절연막 스페이서를 형성하는 단계와, 전체 구조 상부에 제 1 층간 절연막을 형성한 후 상기 제 1 층간 절연막의 선택된 영역에 건식 경사 식각 공정을 실시하여 상기 반도체 기판이 노출되도록 제 1 콘택 홀을 형성하는 단계와, 상기 제 1 층간 절연막에 등방성 식각 공정을 실시하여 상기 제 1 콘택 홀의 폭을 넓히는 단계와, 상기 제 1 콘택 홀이 매립되도록 플러그를 형성하는 단계와, 상기 플러그를 포함한 전체 구조 상부에 제 2 절연막을 형성한 후 상기 제 2 절연막 상부의 선택된 영역에 제 2 도전층을 형성하는 단계와, 상기 제 2 도전층을 포함한 전체 구조 상부에 제 2 층간 절연막을 형성한 후 상기 제 2 층간 절연막의 선택된 영역을 건식 경사 식각 공정으로 제거하여 제 2 콘택 홀을 형성하므로써 상기 플러그와의 정렬 마진을 확대하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating layer on a first conductive layer formed on a selected region of a semiconductor substrate; forming an insulating layer spacer on the sidewalls of the first conductive layer and the first insulating layer; Forming a first contact hole to expose the semiconductor substrate by performing a dry etching process on a selected region of the first interlayer insulating film after forming a first interlayer insulating film on the entire structure, A step of forming a first contact hole in the first contact hole and a second contact hole in the second contact hole by performing an isotropic etching process on the first contact hole to form a plug so that the first contact hole is embedded; Forming a second conductive layer on a selected region of the upper surface of the second insulating layer, forming a second interlayer insulating film on the entire structure including the second conductive layer And forming a second contact hole by removing a selected region of the second interlayer insulating film by a dry etching process so as to enlarge the alignment margin with the plug.
도 1(a) 내지 도 1(f)는 본 발명에 따른 반도체 소자의 콘택 홀 형성 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (f) are cross-sectional views of a device for explaining a method of forming a contact hole in a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호 설명DESCRIPTION OF THE DRAWINGS FIG.
11 : 반도체 기판 12 : 제 1 도전층11: semiconductor substrate 12: first conductive layer
13 : 제 1 절연막 14 : 절연막 스페이서13: first insulating film 14: insulating film spacer
15 : 제 1 층간 절연막 16 : 감광막 패턴15: first interlayer insulating film 16: photosensitive film pattern
17 : 제 1 콘택 홀 18 : 플러그17: first contact hole 18: plug
19 : 제 2 절연막 20 : 제 2 절연막19: second insulating film 20: second insulating film
21 : 제 2 층간 절연막 22 : 제 2 콘택 홀21: second interlayer insulating film 22: second contact hole
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 1(a) 내지 도 1(f)는 본 발명에 따른 반도체 소자의 콘택 홀 형성 방법을 설명하기 위한 소자의 단면도이다.1 (a) to 1 (f) are cross-sectional views of a device for explaining a contact hole forming method of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 기판(11) 상부의 선택된 영역에 제 1 도전층(12) 및 제 1 절연막(13)을 순차적으로 형성하고, 제 1 도전층(12) 및 제 1 절연막(13)의 측벽에 절연막 스페이서(14)를 형성한다.1 (a), a first conductive layer 12 and a first insulating layer 13 are sequentially formed on a selected region of the semiconductor substrate 11, and a first conductive layer 12 and a first insulating layer An insulating film spacer 14 is formed on the side wall of the insulating film 13.
제 1 절연막(13) 및 절연막 스페이서(14)는 TEOS, LTO, MTO, HTO 등 언도프트 실리콘 산화막으로 형성한다.The first insulating film 13 and the insulating film spacer 14 are formed from an undoped silicon oxide film such as TEOS, LTO, MTO, or HTO.
도 1(b)를 참조하면, 전체 구조 상부에 제 1 층간 절연막(15)을 형성하고, 제 1 층간 절연막(15) 상부에 감광막을 형성한 후 패터닝하여 감광막 패턴(16)을 형성한다. 감광막 패턴(16)은 콘택 형성 마스크에 의한 식각 공정으로 형성된다.Referring to FIG. 1 (b), a first interlayer insulating film 15 is formed on the entire structure, a photoresist film is formed on the first interlayer insulating film 15, and then patterned to form a photoresist pattern 16. The photoresist pattern 16 is formed by an etching process using a contact formation mask.
제 1 층간 절연막(15)는 PSG, BSG, BPSG 등의 도프트 실리콘 산화막으로 형성한다.The first interlayer insulating film 15 is formed of a doped silicon oxide film such as PSG, BSG, or BPSG.
도 1(c)를 참조하면, 감광막 패턴(16)을 마스크로 건식 경사식각 공정을 실시하여 제 1 층간 절연막(15)에 제 1 콘택 홀(17)을 형성한다. 제 1 콘택 홀(17)은 제 1 도전층(12)과의 단락(short)를 방지할 수 있도록 제 1 콘택 홀(17)과 제 1 도전층(12)과의 오버레이 정확성(overlay accuracy)까지 고려하여 최종 임계 치수가 작아지게 확정한다.Referring to FIG. 1 (c), a dry etching process is performed using the photoresist pattern 16 as a mask to form a first contact hole 17 in the first interlayer insulating film 15. The first contact hole 17 may be formed to have an overlay accuracy of the first contact hole 17 and the first conductive layer 12 so as to prevent a short circuit with the first conductive layer 12. [ And the final critical dimension is determined to be small.
제 1 콘택 홀(17)을 형성하기 위한 건식 경사식각 공정은 고밀도 플라즈마 방식의 건식 식각 챔버를 사용하여 현상 공정 후의 임계 치수(DICD)와 식각 공정 후의 임계 치수(FICD)의 비가 2:1 이상이 되도록 경사를 조절한다. 또한, 건식 경사식각 공정은 CF4, CHF3, CH3F, C2F6, C3F8, C4F8, CH2F2등 탄소 및 불소가 함유된 가스를 주식각 반응 가스로 사용한다.The dry etching process for forming the first contact hole 17 may be performed by using a dry etching chamber of a high density plasma system so that the ratio of the critical dimension after the development process (DICD) to the critical dimension after etching (FICD) Adjust the slope so that The dry etching process is a process in which carbon and fluorine-containing gases, such as CF 4 , CHF 3 , CH 3 F, C 2 F 6 , C 3 F 8 , C 4 F 8 , and CH 2 F 2 , use.
고밀도 플라즈마 방식의 건식 식각 챔버로는 히티드 실리콘 루프(heated silicon roof)가 장착된 ICP 방식의 고밀도 플라즈마 챔버를 사용하며, C3F8및 CO가 1:0.5∼1:1.5로 혼합된 가스를 이용하여 220∼290℃의 실리콘 루프 온도, 1600∼2800W의 ICP 고주파(RF) 전력, 600∼1800W의 바이어스 RF 전력, 30∼150SCCM의 가스 흐름율의 조건에서 식각한다.The high-density plasma dry etching chamber uses an ICP high-density plasma chamber equipped with a heated silicon roof, and a gas mixture of C 3 F 8 and CO at a ratio of 1: 0.5 to 1: 1.5 A silicon loop temperature of 220 to 290C, an ICP high frequency (RF) power of 1600 to 2800W, a bias RF power of 600 to 1800W, and a gas flow rate of 30 to 150 SCCM.
도 1(d)를 참조하면, 절연막 스페이서(14)에 대해 높은 식각 선택비를 갖는 등방성 식각 공정을 실시하여 제 1 층간 절연막(15)의 일부를 제거하므로써 원하는 크기로 콘택 영역의 면적을 확보하는 동시에 제 1 도전층(12)에 대한 자기 정렬 효과를 이룩한다. 이때 제 1 콘택 홀(17)의 입구 부분이 넓어지게 된다.Referring to FIG. 1D, an isotropic etching process having a high etch selectivity with respect to the insulating film spacer 14 is performed to remove a portion of the first interlayer insulating film 15, thereby securing an area of the contact region of a desired size And at the same time achieves a self-aligning effect on the first conductive layer 12. At this time, the entrance portion of the first contact hole 17 becomes wider.
등방성 식각 공정으로 인산 또는 SC-1을 이용한 습식 식각 공정을 실시한다. SC-1을 이용한 습식 식각 공정은 NH4OH와 과수, 순수의 비를 조절하여 절연막 스페이서(14)에 대한 식각 선택비를 원하는 값으로 조절한다. 또한, 습식 식각 공정을 실시할 때 상온∼비등점의 온도에서 절연막 스페이서(14)에 대한 식각 선택비를 원하는 값으로 조절한다.A wet etching process using phosphoric acid or SC-1 is performed in an isotropic etching process. In the wet etching process using SC-1, the ratio of NH 4 OH, water, and pure water is controlled to adjust the etching selectivity ratio of the insulating film spacer 14 to a desired value. Further, when performing the wet etching process, the etching selectivity ratio to the insulating film spacer 14 is adjusted to a desired value at a temperature ranging from room temperature to a boiling point.
등방성 식각 공정으로 건식 식각 공정을 실시할 경우 마이크로 다운 스트림(micro down stream) 방식, ICP 방식, ECR 방식, TCP 방식, 헬리콘(HELICON) 방식의 플라즈마 챔버를 사용하여 불소 함유 가스 또는 NH3를 주식각 반응 가스로 사용하여 건식 경사식각을 실시하고, 챔버의 온도를 상온∼500℃의 범위로 조절하면서 절연막 스페이서(14)에 대한 식각 선택비를 원하는 값으로 조정한다. 불소 함유 가스로는 CF4, NF4, CHF3, CH3F, C2F6, C3F8, C4F8, CH2F2등을 이용한다.When a dry etching process is performed by an isotropic etching process, a fluorine-containing gas or NH 3 is used as a coating solution by using a micro down stream method, an ICP method, an ECR method, a TCP method, and a HELICON method plasma chamber. The etching selectivity to the insulating film spacer 14 is adjusted to a desired value while adjusting the temperature of the chamber to a range from room temperature to 500 캜. As the fluorine-containing gas, CF 4 , NF 4 , CHF 3 , CH 3 F, C 2 F 6 , C 3 F 8 , C 4 F 8 , CH 2 F 2 and the like are used.
도 1(e)를 참조하면, 입구 부분이 넓어진 제 1 콘택 홀(17)이 매립되도록 폴리실리콘막 또는 CVD 방법으로 텅스텐막을 형성한 후 에치 백 공정을 실시하여 플러그(18)를 형성한다.Referring to FIG. 1 (e), a tungsten film is formed by a polysilicon film or a CVD method so that the first contact hole 17 having an enlarged entrance portion is buried, and then an etch-back process is performed to form the plug 18.
도 1(f)를 참조하면, 플러그(18)을 포함한 전체 구조 상부에 제 2 절연막(19)을 형성한다. 제 2 절연막(19) 상부의 선택된 영역에 제 2 도전층(20)을 형성하고, 제 2 도전층(20)을 포함한 전체 구조 상부에 제 2 층간 절연막(21)을 형성한다. 제 2 층간 절연막(21)의 선택된 영역을 식각하여 제 2 콘택 홀(22)을 형성한다.Referring to FIG. 1 (f), a second insulating film 19 is formed on the entire structure including the plug 18. A second conductive layer 20 is formed on a selected region of the second insulating film 19 and a second interlayer insulating film 21 is formed on the entire structure including the second conductive layer 20. [ A selected area of the second interlayer insulating film 21 is etched to form the second contact hole 22. [
제 2 콘택 홀(22)을 형성할 때 건식 경사식각 방법을 사용하여 플러그(18)와의 정렬 마진을 확대한다.When forming the second contact hole 22, the alignment margin with the plug 18 is enlarged by using the dry oblique etching method.
통상적인 자기 정렬 콘택 홀을 형성하기 위한 식각 공정에 비해 기존 공정의 조합으로 용이하게 자기 정렬 콘택 패턴을 형성하는 동시에 후속 플러그 형성시 원하는 플러그 사이즈를 증대(enlargement)할 수 있다.Alignment contact patterns can be easily formed by a combination of existing processes as compared with an etching process for forming a conventional self-aligned contact hole, and a desired plug size can be enlarged in forming a subsequent plug.
Claims (15)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100418090B1 (en) * | 2001-06-28 | 2004-02-11 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| US11232986B2 (en) | 2019-10-11 | 2022-01-25 | Samsung Electronics Co., Ltd. | Integrated circuit devices including enlarged via and fully aligned metal wire and methods of forming the same |
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| KR100698101B1 (en) | 2005-10-05 | 2007-03-23 | 동부일렉트로닉스 주식회사 | Tungsten Plug Structure Of Semiconductor Device And Method for Forming The Same |
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| KR950021130A (en) * | 1993-12-31 | 1995-07-26 | 김주용 | Method for manufacturing contact hole of semiconductor device |
| KR970023725A (en) * | 1995-10-20 | 1997-05-30 | 김광호 | How to Form Contact Holes |
| KR0183764B1 (en) * | 1995-12-05 | 1999-04-15 | 김광호 | Landing pad |
| KR0183899B1 (en) * | 1996-06-28 | 1999-04-15 | 김광호 | Magnetic arrangement contact hole forming method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100418090B1 (en) * | 2001-06-28 | 2004-02-11 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| US11232986B2 (en) | 2019-10-11 | 2022-01-25 | Samsung Electronics Co., Ltd. | Integrated circuit devices including enlarged via and fully aligned metal wire and methods of forming the same |
| US11876017B2 (en) | 2019-10-11 | 2024-01-16 | Samsung Electronics Co., Ltd. | Integrated circuit devices including enlarged via and fully aligned metal wire and methods of forming the same |
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