KR100464391B1 - Method of forming contact holes of a semiconductor device comprising a process of dry etching for SiON layer - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to guarantee a sufficient over-etch margin when a silicon oxide layer is etched until a silicon oxynitride layer is exposed by setting up an etch condition for etching the silicon oxide layer in which the silicon oxide layer has high etch selectivity with respect to a lower etch blocking layer and a deposition of polymer is minimized. CONSTITUTION: A semiconductor substrate is prepared. A conductive layer pattern having a step is formed on the substrate. The uppermost layer of the conductive layer pattern is composed of a silicide layer. The conductive layer pattern and the front surface of the substrate are covered with a silicon oxynitride layer. The front surface of the silicon oxynitride layer is covered with a silicon oxide layer. A photoresist pattern that respectively exposes the silicon oxide layer on a predetermined region of the substrate and the silicon oxide layer on the conductive layer pattern is formed on the silicon oxide layer. The silicon oxide layer is etched to expose the silicon oxynitride layer by using the photoresist pattern as an etch mask. The photoresist pattern and the polymer generated in the etch process are eliminated. The silicon oxynitride layer is etched by using a gas composition in which CHF3 gas and Ar gas are mixed in a ratio of 1:3-1:0.1 so that contact holes for exposing a predetermined region of the substrate and a conductive layer pattern are simultaneously formed.

Description

Method of forming contact holes of a semiconductor device comprising a process of dry etching for SiON layer}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device.

In the metal contact process using an etch stopping layer to overcome the step, the step of etching the interlayer insulating film is to set the etching conditions so that the interlayer insulating film has a high etching selectivity with respect to the lower etch stop layer. In the process of etching the lower etch stop layer, it is important to set etching conditions such that the etch stop layer has a low etch selectivity with respect to the interlayer insulating layer.

To this end, low pressure and high bias power are achieved by using an inductive coupled plasma (ICP) type etching apparatus capable of etching silicon oxide films at high etch rates while achieving high etching selectivity. In the first etching process under a high bias power condition, the etch selectivity of the interlayer dielectric layer is first etched so that the etch selectivity of the interlayer insulating layer is 20: 1 or more, and then the low bias power and the high source In the second etching process under high source power conditions, a method of removing an etch barrier layer by adding carbon monoxide (CO) or oxygen (O 2) to inhibit the polymerization to an etching gas of low carbon / fluorine series is used. .

However, by using an electrostatic chuck for the purpose of removing particles as a means for fixing the wafer, a transition step is required for process stabilization between the first etching process and the second etching process. You need to add At this time, the plasma may become unstable due to a sudden change in gas composition and pressure occurring between the first etching process and the second etching process, which locally deposits a polymer in the contact and contacts the polymer. The hole does not open. The phenomenon in which the contact hole is not opened is mainly caused by the first etching process, and as the time of the first etching process increases, the fluorocarbon polymer deposited on the upper portion of the etch stop layer also increases, thereby increasing after the second etching process. Loss as opposed to the first etching process is shown.

In addition, a silicon (Si) substrate and titanium silicide (TiSi2) using carbon monoxide (CO) or oxygen (O2) added as a base film to inhibit polymerization in the fluorocarbon-based etching gas during the second etching process. ) And the cobalt silicide (CoSi2) film prevents the etching prevention film from exhibiting a sufficiently large etching selectivity.

Accordingly, the conventional dry etching method causes a problem of increasing contact resistance due to excessive underlayer loss.

Accordingly, an aspect of the present invention is to provide a method for forming a contact hole in a semiconductor device including a dry etching process for a silicon oxynitride film which can effectively prevent the above problems.

In order to achieve the above technical problem, the present invention provides a semiconductor substrate, a conductive layer pattern formed to have a step on the semiconductor substrate and having an uppermost layer formed of a silicide layer, and covering the entire surface of the conductive layer pattern and the semiconductor substrate. A film and a structure in which a silicon oxide film covering the entire surface of the silicon oxynitride film are sequentially formed, comprising: (a) exposing the silicon oxide film on a predetermined region of the semiconductor substrate and the silicon oxide film on the conductive layer pattern, respectively; Forming a photoresist pattern on the silicon oxide film; (b) exposing the silicon oxynitride film by etching the silicon oxide film using the photoresist pattern as an etching mask; (c) removing the photoresist pattern and the polymer generated in the etching process of step (b); (d) etching the silicon oxynitride film using a gas composition in which methane trifluoride (CHF3) gas and argon (Ar) gas are mixed in a ratio of 1: 3 to 1: 0, thereby etching a predetermined region of the semiconductor substrate and the A method of forming a contact hole in a semiconductor device, the method comprising: simultaneously forming a contact hole exposing a conductive layer pattern.

In the present invention, the carbon tetrafluoride (CF4) gas and argon (Ar) instead of the gas composition in which the trifluoromethane (CHF3) gas and argon (Ar) gas of step (d) are mixed at a ratio of 1: 3 to 1: 0.1. ) The gas composition which mixed gas in the ratio of 1: 3-1: 0.1 can be used.

In the present invention, the conductive layer pattern may be a gate electrode.

In the present invention, the silicide layer may be formed of titanium silicide (TiSi2) or cobalt silicide (CoSi2).

In the present invention, the etching of the step (d) is preferably made of an etching process using a plasma, the etching process using the plasma, RF power of 100 Watt to 250 Watt, pressure below 150 mTorr, and 60 It is preferable to proceed under the conditions of a magnetic field of Gauss to 80 Gauss.

According to the present invention, the first etching process for etching the silicon oxide film, which is an interlayer insulating film, is set up as an etching condition in which the silicon oxide film has a high etching selectivity with respect to the lower etching prevention film and minimizes deposition of polymer. . Therefore, according to the present invention, a sufficient overetch margin may be secured when the silicon oxide film is etched until the silicon oxynitride film, which is an etch stop layer, is exposed. The present invention also provides a second etching process for etching the silicon oxynitride film (SiON) film, which is the lower etch stop film, in which the etching selectivity of the silicon oxide film and the silicon oxynitride (SiON) film is almost 1: 1. Etching conditions that can be etched with high etching selectivity were set for both the silicide film (in the case of the gate electrode) and the silicon film (in the case of the source / drain) which are films. Therefore, according to the present invention, since the underlying film loss can be minimized, a contact having excellent contact resistance can be simultaneously formed with respect to the underlying silicon film and the silicide underlying film, and at the same time, an undercut is formed under the contact hole. Can be prevented.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 6.

1 is a cross-sectional view for explaining a step of forming the gate electrode 200 and the insulating film 108 via the gate insulating film 102.

Specifically, a device isolation film (not shown) is formed by applying a conventional device isolation process to an inactive region of the semiconductor substrate 100. Subsequently, a gate insulating film, a conductive polysilicon film, and a silicide film are sequentially formed on the entire surface of the semiconductor substrate 100. In this case, the silicide layer is formed of a titanium silicide (TiSi2) layer or a cobalt silicide (CoSi2) layer. Subsequently, the gate insulating film 102 with the gate insulating film 102 is formed by successively patterning the gate insulating film, the conductive polysilicon film, and the silicide film. In this case, the gate electrode 200 is formed of a conductive polysilicon pattern 104 and a silicide pattern 106. Subsequently, an insulating film 108, for example, a silicon nitride film SiN, is formed on the entire surface of the resultant product.

2 is a cross-sectional view for explaining a step of forming the spacer 108a and the source / drain 110.

Specifically, first, anisotropic dry etching is performed on the insulating film 108 of FIG. 1, thereby completing the spacers 108a on both sidewalls of the gate electrode 200 via the gate insulating film 102. .

Subsequently, impurity ions are implanted into the semiconductor substrate 100 using the spacers 108a and the gate electrode 200 as ion implantation masks, and an activation annealing is performed on the gate electrode 200. The source / drain 110 is formed on both semiconductor substrates 100.

3 is a cross-sectional view illustrating a step of forming a silicon oxynitride (SiON) film 112 as an etch stop layer on the entire surface of the resultant image.

In this case, when the silicon oxynitride film 112 forms a contact hole on the gate electrode 200 and the source / drain 110 on the semiconductor substrate 100 at the same time in a subsequent step, The gate electrode 200 serves to prevent overetching.

4 is a cross-sectional view for describing a step of forming the silicon oxide film 114 and the photoresist pattern 116 on the entire surface of the silicon oxynitride (SiON) film 112.

Specifically, first, a silicon oxide film 114 covering the entire surface of the silicon oxynitride film 112 is deposited by, for example, a CVD method. Subsequently, the silicon oxide film is formed by a photoresist pattern 116 exposing the silicon oxide film 114 on the source / drain 110 of the semiconductor substrate 100 and the silicon oxide film 114 on the gate electrode 200, respectively. It is formed on top of 114. Subsequently, the source / drain 110 may be etched by etching the silicon oxide film 114 using a fluorocarbon etching gas such as ethane hexafluoride (C2F6) gas using the photoresist pattern 116 as an etching mask. The silicon oxynitride film 112 on the () and the silicon oxynitride film 112 on the gate electrode 200 are exposed. In this case, a carbon fluoride-based polymer 118 that is an etching byproduct is deposited on the exposed silicon oxynitride film 112.

FIG. 5 is a cross-sectional view illustrating a process of removing the photoresist pattern 116 of FIG. 4 and the polymer 118 of FIG. 4.

Specifically, the resultant is ashed with an oxygen plasma to remove the photoresist pattern (116 of FIG. 4) and the polymer (118 of FIG. 4).

6 is a cross-sectional view illustrating a step of completing a contact hole by removing the exposed silicon oxynitride film 112.

Specifically, methane trifluoride (CHF3) gas and argon (Ar) gas or carbon tetrafluoride (CF4) gas and argon (Ar) gas are mixed using a gas composition in a ratio of 1: 3 to 1: 0.1. By time-etching the exposed silicon oxynitride film 112, a contact hole h exposing the source / drain 110 and the gate electrode 200 of the semiconductor substrate 100 is formed at the same time. . In this case, the etching process is performed by plasmaizing the gas composition, the etching process using the plasma is under the conditions of the RF power of 100 Watt ~ 250 Watt, the pressure of 150 mTorr or less, and the magnetic field of 60 Gauss ~ 80 Gauss Proceed. Under the above conditions, the gas composition may etch the silicon oxynitride film 112 with good etching selectivity with respect to the silicide film 106 and the silicon film 110. Therefore, since the loss of the underlying film can be minimized, a contact excellent in contact resistance can be formed. Further, under the above conditions, the gas composition may etch the silicon oxynitride film 112 such that the etching selectivity with the silicon oxide film 114 is almost 1: 1. Therefore, it is possible to prevent an undercut from being formed in the lower portion of the contact hole.

As described above, the present invention provides a first etching process for etching a silicon oxide film, which is an interlayer insulating film, as an etching condition in which the silicon oxide film has a high etching selectivity with respect to an underlying etch stop layer and minimizes deposition of polymer. Setup was made. Therefore, according to the present invention, a sufficient overetch margin may be secured when the silicon oxide film is etched until the silicon oxynitride film, which is an etch stop layer, is exposed. The present invention also provides a second etching process for etching the silicon oxynitride film (SiON) film, which is the lower etch stop film, in which the etching selectivity of the silicon oxide film and the silicon oxynitride (SiON) film is almost 1: 1. Etching conditions that can be etched with high etching selectivity were set for both the silicide film (in the case of the gate electrode) and the silicon film (in the case of the source / drain) which are films. Therefore, according to the present invention, since the underlying film loss can be minimized, a contact having excellent contact resistance can be simultaneously formed with respect to the underlying silicon film and the silicide underlying film, and at the same time, an undercut is formed under the contact hole. Can be prevented.

The present invention has been described in detail with reference to specific embodiments, but the present invention is not limited thereto, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention.

1 to 6 are cross-sectional views illustrating a method for forming a contact hole according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 102 gate insulating film

104: conductive polysilicon pattern 106: silicide pattern

200: gate electrode 108a: spacer

110 source / drain 112 silicon oxynitride film

114: silicon oxide film 116: photoresist pattern

118: fluorocarbon polymer

Claims (6)

A semiconductor substrate, a conductive layer pattern formed to have a step on the semiconductor substrate and having an uppermost layer formed of a silicide layer, a silicon oxynitride film covering the entire surface of the conductive layer pattern and the semiconductor substrate, and an entire surface of the silicon oxynitride film In a structure in which a silicon oxide film is sequentially formed, (a) forming a photoresist pattern on the silicon oxide film, the photoresist pattern exposing the silicon oxide film on a predetermined region of the semiconductor substrate and the silicon oxide film on the conductive layer pattern, respectively; (b) exposing the silicon oxynitride film by etching the silicon oxide film using the photoresist pattern as an etching mask; (c) removing the photoresist pattern and the polymer generated in the etching process of step (b); (d) etching the silicon oxynitride film by using a gas composition in which methane trifluoride (CHF3) gas and argon (Ar) gas are mixed in a ratio of 1: 3 to 1: 0.1, and the predetermined region of the semiconductor substrate and the Forming a contact hole for exposing the conductive layer pattern at the same time. A semiconductor substrate, a conductive layer pattern formed to have a step on the semiconductor substrate and having an uppermost layer formed of a silicide layer, a silicon oxynitride film covering the entire surface of the conductive layer pattern and the semiconductor substrate, and an entire surface of the silicon oxynitride film In a structure in which a silicon oxide film is sequentially formed, (a) forming a photoresist pattern on the silicon oxide film, the photoresist pattern exposing the silicon oxide film on a predetermined region of the semiconductor substrate and the silicon oxide film on the conductive layer pattern, respectively; (b) exposing the silicon oxynitride film by etching the silicon oxide film using the photoresist pattern as an etching mask; (c) removing the photoresist pattern and the polymer generated in the etching process of step (b); (d) etching the silicon oxynitride film using a gas composition in which carbon tetrafluoride (CF4) gas and argon (Ar) gas are mixed at a ratio of 1: 3 to 1: 0.1, thereby etching a predetermined region of the semiconductor substrate and the conductive material; And simultaneously forming contact holes exposing the layer pattern. The method of claim 1, wherein the conductive layer pattern, A contact hole forming method for a semiconductor device, characterized in that the gate electrode. The method of claim 1, wherein the silicide layer, Method of forming a contact hole in a semiconductor device, characterized in that formed of titanium silicide (TiSi2) or cobalt silicide (CoSi2). The method of claim 1, wherein the etching of the step (d), A method of forming a contact hole in a semiconductor device, characterized in that the etching process using a plasma. The method of claim 5, wherein the etching process using the plasma, A method for forming a contact hole in a semiconductor device, characterized in that it proceeds under conditions of 100 Watts to 250 Watts of RF power, 150 mTorr or less, and 60 Gauss to 80 Gauss magnetic field.

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