KR19980058447A - Contact hole formation method of semiconductor device - Google Patents
Contact hole formation method of semiconductor device Download PDFInfo
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- KR19980058447A KR19980058447A KR1019960077771A KR19960077771A KR19980058447A KR 19980058447 A KR19980058447 A KR 19980058447A KR 1019960077771 A KR1019960077771 A KR 1019960077771A KR 19960077771 A KR19960077771 A KR 19960077771A KR 19980058447 A KR19980058447 A KR 19980058447A
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- insulating film
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- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 23
- 125000006850 spacer group Chemical group 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 description 24
- 239000011229 interlayer Substances 0.000 description 18
- 238000003860 storage Methods 0.000 description 10
- 238000000151 deposition Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 두 절연막의 이상적 반응으로 상기 두 절연막 사이에 소정의 식각 정지층을 형성하여 콘택홀 형성을 위한 절연막의 식각 시 기판의 손실을 방지할 수 있는 반도체 소자의 콘택홀 형성방법을 제공하는 것으로, 반도체 기판 상에 제1 및 제2 절연막을 연속적으로 형성함과 더불어 제1 및 제2 절연막 사이에 식각 정지 절연막을 형성하는 단계; 제2 절연막 상에 제3 절연막을 형성하는 단계; 기판의 소정 부분 상의 제3 및 제2 절연막을 식각하여 식각 정지층을 노출시켜 소정의 예비 콘택홀을 형성하는 단계; 예비 콘택홀 양 측벽에 절연막 스페이서를 형성하는 단계; 및, 절연막 스페이서를 식각 마스크로하여 식각 정지 절연막 및 제1 절연막을 식각하여 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention provides a method for forming a contact hole in a semiconductor device capable of preventing a loss of a substrate during etching of an insulating film for forming a contact hole by forming a predetermined etch stop layer between the two insulating films in an ideal reaction between the two insulating films. Forming an etch stop insulating film between the first and second insulating films while continuously forming the first and second insulating films on the semiconductor substrate; Forming a third insulating film on the second insulating film; Etching the third and second insulating films on the predetermined portion of the substrate to expose the etch stop layer to form a predetermined preliminary contact hole; Forming insulating film spacers on both sidewalls of the preliminary contact holes; And forming a contact hole by etching the etch stop insulating film and the first insulating film by using the insulating film spacer as an etching mask.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 콘택홀 형성을 위한 절연막의 식각시 기판의 손실을 방지할 수 있는 반도체 소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device capable of preventing a loss of a substrate during etching of an insulating film for forming a contact hole.
반도체 소자이 고속화 및 고집적화가 진행됨에 따라, 반도체 소자의 패턴에 대한 미세화의 필요성이 요구되고 있다.As the speed of semiconductor devices increases and the integration of semiconductor devices increases, there is a need for miniaturization of patterns of semiconductor devices.
일반적인 반도체 소자에 있어서, 기판과 상부 층들 사이의 전기적 연결을 위하여 콘택홀을 형성하게 된다. 이때, 상기 콘택홀은 기판과 상부 층 사이의 절연을 위한 절연막을 형성한 다음, 절연막 상부에 포토리소그라피로 소정의 감광막 패턴을 형성하고, 이 감광막 패턴을 이용하여 하부의 절연막을 식각하여 기판을 노출시킴으로써 형성한다.In a typical semiconductor device, contact holes are formed for electrical connection between the substrate and the upper layers. In this case, the contact hole forms an insulating film for insulation between the substrate and the upper layer, and then forms a predetermined photoresist pattern on the insulating film by photolithography, and the substrate is exposed by etching the lower insulating film using the photoresist pattern. By forming.
그러나, 상기한 종래의 콘택홀 형성 방법에서는 다음과 같은 문제가 발생한다. 즉, 절연막 식각 장비의 특성에 따라 기판 중앙과 가장 자리 사이의 식각률의 차이가 심하여, 상기 콘택홀 형성을 위한 절연막의 식각시 기판 표면의 손실 차이로 인하여 기판의 위치에 따라 심한 누설 전류의 차이가 발생함으로써 소자의 신뢰성을 저하시킨다.However, the following problem occurs in the conventional method for forming a contact hole. That is, the difference in the etch rate between the center and the edge of the substrate is severe according to the characteristics of the insulating film etching equipment, the severe leakage current difference according to the position of the substrate due to the difference in the loss of the surface of the substrate when etching the insulating film for forming the contact hole Generation reduces the reliability of the device.
이에 따라, 종래에는 절연막을 일부 식각한 후 콘택홀 측벽에 스페이서 형성을 위한 전면 식각시 나머지의 절연막을 식각하여 기판을 노출시키는 자기정렬 방식을 적용하였지만, 상기한 바와 같은 기판의 위치에 따른 식각률 차이에 의해 나머지 절연막의 식각 시 기판이 노출되지 않거나 기판의 일부에서 손실이 심하게 발생됨에 따라 누설 전류의 증가를 야기시킨다.Accordingly, in the related art, a self-aligning method of exposing the substrate by etching the remaining insulating film after etching the insulating film partially and then etching the entire surface for forming the spacer on the sidewall of the contact hole is applied. However, the etching rate difference according to the position of the substrate is different. As a result, the substrate is not exposed when the remaining insulating layer is etched or the loss is severely generated in a part of the substrate, thereby causing an increase in leakage current.
이에, 본 발명은 상기한 문제점을 감안하여 창출된 것으로서, 두 절연막의 이상적 반응으로 상기 두 절연막 사이에 소정의 식각 정지층을 형성하여 콘택홀 형성을 위한 절연막의 식각 시 기판의 손실을 방지할 수 있는 반도체 소자의 콘택홀 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made in view of the above problems, and by forming an etch stop layer between the two insulating films in an ideal reaction between the two insulating films, it is possible to prevent the loss of the substrate during the etching of the insulating film for forming the contact hole. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device.
도 1A 내지 도 1F는 본 발명의 실시예에 따른 비트라인 및 캐패시터의 스토리지 노드전극 콘택을 위한 콘택홀 형성방법을 설명하기 위한 공정 단면도.1A to 1F are cross-sectional views illustrating a method of forming a contact hole for storage node electrode contact of a bit line and a capacitor according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1:반도체 기판, 2:필드 산화막, 3:트랜지스터, 4:제1 절연막, 5:산화질화막, 6:제1 층간절연막, 7:제2 절연막, 8:제1 예비 콘택홀, 9:제1 스페이서, 10:비트라인용 콘택홀, 11:비트라인, 12:제2 층간절연막, 13:제3 층간절연막, 14:제2 예비 콘택홀, 15:제2 스페이서, 16:스토리지 노드전극용 콘택홀, 17:스토리지 노드 전극.1: semiconductor substrate, 2: field oxide film, 3: transistor, 4: first insulating film, 5: oxynitride film, 6: first interlayer insulating film, 7: second insulating film, 8: first preliminary contact hole, 9: first Spacer, 10: bit line contact hole, 11: bit line, 12: second interlayer insulating film, 13: third interlayer insulating film, 14: second preliminary contact hole, 15: second spacer, 16: storage node electrode contact Hole, 17: storage node electrode.
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 콘택홀 형성방법은 반도체 기판 상에 제1 및 제2 잘연막을 연속적으로 형성함과 더불어 상기 제1 및 제2 절연막 사이에 식각 정지 절연막을 형성하는 단계; 상기 제2 절연막 상에 제3 절연막을 형성하는 단계; 상기 기판의 소정 부분 상의 상기 제3 및 제2 절연막을 식각하여 상기 식각 정지층을 노출시켜 소정의 예비 콘택홀을 형성하는 단계: 상기 예비 콘탤홀 양 측벽에 절연막 스페이서를 형성하는 단계; 및, 상기 절연막 스페이서를 식각 마스크로하여 상기 식각 정지 절연막 및 제1 절연막을 식각하여 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 한다.In the method of forming a contact hole in a semiconductor device according to the present invention for achieving the above object, a first stop layer is continuously formed on a semiconductor substrate and an etch stop insulating layer is formed between the first and second insulating films. Doing; Forming a third insulating film on the second insulating film; Etching the third and second insulating films on the predetermined portion of the substrate to expose the etch stop layer to form a predetermined preliminary contact hole: forming insulating film spacers on both sidewalls of the preliminary contact hole; And forming a contact hole by etching the etch stop insulating layer and the first insulating layer by using the insulating layer spacer as an etch mask.
또한, 상기 식각 정지 절연막은 상기 제1 절연막과 상기 제2 절연막의 연속적 형성 시 상기 제1 절연막과 제2 절연막의 이상(異狀)적 반응에 의해 형성된 절연막인 것을 특징으로 한다.The etch stop insulating film may be an insulating film formed by abnormal reaction between the first insulating film and the second insulating film when the first insulating film and the second insulating film are continuously formed.
또한, 상기 제1 절연막은 중간 열산화막이고, 상기 제2 절연막은 산화질화막인 것을 특징으로 한다.The first insulating film may be an intermediate thermal oxide film, and the second insulating film may be an oxynitride film.
상기 구성으로 된 본 발명에 의하면, 중간 열산화막과 산화질화막의 연속적 증착으로 중간 열산화막과 산화질화막 사이에 식각 정지 절연막을 형성하여 콘택홀 형성을 위한 절연막의 식각시 기판 표면의 손실을 방지할 수 있다.According to the present invention having the above configuration, by the continuous deposition of the intermediate thermal oxide film and the oxynitride film to form an etch stop insulating film between the intermediate thermal oxide film and the oxynitride film to prevent the loss of the surface of the substrate during the etching of the insulating film for forming the contact hole have.
[실시예]EXAMPLE
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 1A 내지 도 1F는 본 발명의 실시예에 따른 비트라인 및 캐패시터의 스토리지 노드전극 콘택을 위한 콘택홀 형성방법을 설명하기 위한 공정 단면도이다.1A to 1F are cross-sectional views illustrating a method of forming a contact hole for storage node electrode contact of a bit line and a capacitor according to an embodiment of the present invention.
먼저, 비트라인 콘택을 형성하기 위하여 도 1A에 도시된 바와 같이, 필드 산화막(2) 및 게이트 절연막(3a), 게이트(3b)와 측벽 스페이서(3c) 및 소오스 및 드레인의 접합영역(도시되지 않음)을 구비한 트랜지스터(3)가 형성된 반도체 기판(1) 상에 제1 절연막(4)으로서 중간열산화막(Mediunm Temperature Oxide ; MTO)을 형성하고, 그 상부에 연속적 증착 방식으로 산화질화막(5)을 형성한다. 이때, 제1 절연막(4)과 산화질화막(5) 사이에 식각률의 차이가 나는 반응에 의하여 쉽게 식각되지 않는 소정의 제1 층간절연막(6)이 형성되는데, 이 제1 층간절연막(6)은 이후 비트라인 및 스토리지 노드전극의 콘택홀 형성을 위한 절연막의 식각 시 식각 정지층으로 작용한다.First, to form a bit line contact, as shown in FIG. 1A, a junction region of a field oxide film 2 and a gate insulating film 3a, a gate 3b and a sidewall spacer 3c, and a source and a drain (not shown) (Mediunm Temperature Oxide (MTO)) is formed as the first insulating film 4 on the semiconductor substrate 1 on which the transistor 3 having the transistor 3 is formed, and the oxynitride film 5 is formed on the upper portion by a continuous deposition method. To form. At this time, a first interlayer insulating film 6 which is not easily etched is formed between the first insulating film 4 and the oxynitride film 5 by a reaction in which the etching rate is different, and the first interlayer insulating film 6 is formed. Subsequently, when the insulating layer is etched to form the contact holes of the bit line and the storage node electrode, it serves as an etch stop layer.
이어서, 산화질화막(5) 상에 제2 절연막(7)을 형성하고, 제2 절연막(7) 상에 포토리소그라피로 소정의 비트라인 콘택 형성을 위한 마스크 패턴(도시되지 않음)을 형성한다. 상기 마스크 패턴을 이용하여 하부의 막들을 식각하면 제1 층간절연막(6)에서 식각이 정지됨에 따라 제2 절연막(7)과 산화질화막(5)만이 식각되고, 제1 층간절연막(6)을 노출시켜 소정의 비트라인용 제1 예비 콘택홀(8)을 형성한다. 그리고 나서, 상기 마스크 패턴을 공지된 방법으로 제거한다.Subsequently, a second insulating film 7 is formed on the oxynitride film 5, and a mask pattern (not shown) for forming a predetermined bit line contact is formed on the second insulating film 7 by photolithography. When the lower layers are etched using the mask pattern, only the second insulating layer 7 and the oxynitride layer 5 are etched as the etch stops in the first interlayer insulating layer 6, and the first interlayer insulating layer 6 is exposed. The first preliminary contact hole 8 for the predetermined bit line is formed. Then, the mask pattern is removed by a known method.
도 1B에 도시된 바와 같이, 도 1A의구조 상에 제3 절연막을 증착하고, 상기 제3 절연막을 전면 식각하여 제1 층간절연막(6)을 노출시킴과 더불어 제1 예비 콘택홀(8) 양 측벽에 제1 스페이서(9)를 형성한다. 이어서, 제1 스페이서(9)를 식각 마스크로하여 노출된 제1 층간절연막(6) 및 제1 절연막(4)을 식각하여 기판(1)을 노출시킴으로써 비트라인용 콘택홀(10)을 완성한다.As shown in FIG. 1B, a third insulating film is deposited on the structure of FIG. 1A, the entire surface of the third insulating film is etched to expose the first interlayer insulating film 6, and the amount of the first preliminary contact hole 8 is also increased. The first spacer 9 is formed on the side wall. Subsequently, the first interlayer insulating film 6 and the first insulating film 4 are etched using the first spacer 9 as an etch mask to expose the substrate 1 to complete the bit line contact hole 10. .
도 1C에 도시된 바와 같이, 도 1C의 구조 상에 폴리실리콘막을 증착하고 소정의 형태로 패터닝하여 콘택홀(9)을 통하여 상기 트랜지스터(3)의 일측 기판(1)과 콘택하는 비트라인(11)을 형성한다.As shown in FIG. 1C, a bit line 11 which contacts the one side substrate 1 of the transistor 3 through the contact hole 9 by depositing and patterning a polysilicon film on the structure of FIG. 1C. ).
이어서, 스토리지 노드전극 콘택을 형성하기 위하여 도 1D에 도시된 바와 같이, 도 1C의구조 상에 제2 층간절연막(12) 및 제3 층간절연막(13)을 형성하고, 제3 층간절연막(13) 상부에 포토리소그라피로 소정의 스토리지 노드전극 콘택 형성을 위한 마스크 패턴(도시되지 않음)을 형성한다. 상기 마스크 패턴을 이용하여 하부의 막들을 식각하면 제1 층간절연막(6)에서 식각이 정지됨에 따라, 제3 및 제2 층간 절연막(12,13)과, 제2 절연막(7) 및 산화질화막(5)만이 식각되고, 제1 층간절연막(6)을 노출시켜 소정의 스토리지 노드 전극용 제2 예비 콘택홀(14)을 형성한다. 그리고 나서, 상기 마스크 패턴을 공지된 방법으로 제거한다.Subsequently, as shown in FIG. 1D, a second interlayer insulating film 12 and a third interlayer insulating film 13 are formed on the structure of FIG. 1C to form a storage node electrode contact, and the third interlayer insulating film 13 is formed. Photolithography forms a mask pattern (not shown) for forming a predetermined storage node electrode contact thereon. When the lower layers are etched using the mask pattern, the etch stops in the first interlayer insulating layer 6, so that the third and second interlayer insulating layers 12 and 13, the second insulating layer 7, and the oxynitride layer ( Only 5) is etched and the first interlayer insulating film 6 is exposed to form a second preliminary contact hole 14 for the predetermined storage node electrode. Then, the mask pattern is removed by a known method.
도 1E에 도시된 바와 같이, 도 1D의 구조 상에 제4 절연막을 증착하고, 상기 제4 절연막을 전면 식각하여 제1 층간절연막(6)을 노출시킴과 더불어 제2 예비 콘택홀(14) 양 측벽에 제2 스페이서(15)를 형성한다. 이어서, 제2 스페이서(15)를 식각 마스크로하여 노출된 제1 층간절연막(6) 및 제1 절연막(4)을 식각하여 기판(1)을 노출시킴으로써 스토리지 노드전극용 콘택홀(6)을 완성한다.As shown in FIG. 1E, a fourth insulating film is deposited on the structure of FIG. 1D, and the fourth insulating film is etched entirely to expose the first interlayer insulating film 6, and the amount of the second preliminary contact hole 14. The second spacer 15 is formed on the side wall. Subsequently, the first interlayer insulating film 6 and the first insulating film 4 are etched using the second spacer 15 as an etch mask to expose the substrate 1 to complete the contact hole 6 for the storage node electrode. do.
도 1F에 도시된 바와 같이, 도 1E의 구조 상에 폴리실리콘막을 증착하고 소정의 형태로 패터닝하여 콘택홀(16)을 통하여 상기 트랜지스터(3)의 다른 측 기판(1)과 콘택하는 캐패시터의 스토리지 노드전극(17)을 형성한다.As shown in FIG. 1F, a storage of a capacitor is deposited on the structure of FIG. 1E and patterned into a predetermined form to contact the other side substrate 1 of the transistor 3 through the contact hole 16. The node electrode 17 is formed.
한편, 상기한 바와 같이 식각 정지층을 이용한 콘택홀 형성방법은 금속 콘택 및 기타 도선에 연결되는 모든 콘택에 적용할 수 있다.On the other hand, as described above, the method for forming a contact hole using the etch stop layer may be applied to all contacts connected to metal contacts and other conductive wires.
상기 실시예에 의하면, MTO와 산화질화막의 연속적 증착에 의한 이상적 층간절연막을 형성하여 절연막의 식각 시 소정의 식각 정지층으로 작용하도록 하여 기판 표면의 손실을 방지할 수 있을 뿐만 아니라, 절연막 식각 장비에 의한 기판의 중앙 및 가장자리의 식각률 차이에 의한 기판의 손실을 방지할 수 있다. 따라서, 기판의 위치에 따른 누설전류의 차이를 감소시킬 수 있게 됨과 더불어 기판 표면의 손실에 따른 누설 전류를 방지함으로써 소자의 신뢰성을 향상시킬 수 있다.According to the above embodiment, the ideal interlayer insulating film is formed by the continuous deposition of MTO and oxynitride film to act as a predetermined etch stop layer during the etching of the insulating film to prevent the loss of the surface of the substrate, It is possible to prevent the loss of the substrate due to the difference in the etching rate of the center and the edge of the substrate. Therefore, it is possible to reduce the difference in leakage current according to the position of the substrate and to improve the reliability of the device by preventing the leakage current due to the loss of the substrate surface.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, A deformation | transformation can be implemented in the range which does not deviate from the technical summary of this invention.
Claims (5)
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|---|---|---|---|
| KR1019960077771A KR19980058447A (en) | 1996-12-30 | 1996-12-30 | Contact hole formation method of semiconductor device |
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| KR1019960077771A KR19980058447A (en) | 1996-12-30 | 1996-12-30 | Contact hole formation method of semiconductor device |
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| KR19980058447A true KR19980058447A (en) | 1998-10-07 |
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1996
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