KR19980054454A - Polysilicon Cone Formation Method - Google Patents
Polysilicon Cone Formation Method Download PDFInfo
- Publication number
- KR19980054454A KR19980054454A KR1019960073617A KR19960073617A KR19980054454A KR 19980054454 A KR19980054454 A KR 19980054454A KR 1019960073617 A KR1019960073617 A KR 1019960073617A KR 19960073617 A KR19960073617 A KR 19960073617A KR 19980054454 A KR19980054454 A KR 19980054454A
- Authority
- KR
- South Korea
- Prior art keywords
- reactor
- polysilicon
- polysilicon layer
- layer forming
- forming method
- Prior art date
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 41
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 230000008021 deposition Effects 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 10
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000007599 discharging Methods 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 230000000087 stabilizing effect Effects 0.000 claims description 2
- 230000014759 maintenance of location Effects 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
Abstract
본 발명은 폴리실리콘층 형성 방법에 관한 것으로, 폴리실리콘을 증착한후 실시하는 불순물 이온 도핑 및 열처리 공정을 개선하므로써 플래쉬 메모리 셀의 데이터 보존 시간을 증대시킬 수 있도록 한 폴리실리콘층 형성 방법에 관한 것이다.The present invention relates to a method for forming a polysilicon layer, and more particularly, to a method for forming a polysilicon layer to improve the data retention time of a flash memory cell by improving an impurity ion doping and heat treatment process performed after the deposition of polysilicon. .
Description
본 발명은 폴리실리콘층 형성 방법에 관한 것으로, 특히 플래쉬 메모리 셀의 플로팅 게이트로 사용되는 폴리실리콘층 형성 방법에 관한 것이다 .The present invention relates to a polysilicon layer forming method, and more particularly, to a polysilicon layer forming method used as a floating gate of a flash memory cell.
일반적으로 반도체 소자의 제조 공정에서 폴리실리콘(Poly - Si)은 증착 및 도핑 과정을 통해 전극으로 이용된다. 그 예로 모스(MOS) 트랜지스터의 게이트 전극, 플래쉬 메모리 셀의 플로팅 게이트 및 콘트롤 게이트 등이 여기에 속하는데, 그러면 도 1에 도시된 플래쉬 메모리 셀의 구조를 통해 종래의 폴리실리콘층 형성 방법을 설명하기로한다.In general, polysilicon (Poly-Si) is used as an electrode through a deposition and doping process in a semiconductor device manufacturing process. Examples include a gate electrode of a MOS transistor, a floating gate of a flash memory cell, a control gate, and the like, and then a conventional method of forming a polysilicon layer will be described through the structure of the flash memory cell shown in FIG. 1. do.
일반적인 플래쉬 메모리 셀은 도 1에 도시된 바와 같이 실리콘 기판(1)상에 터널산화막(4), 플로팅 게이트(5), 유전체막(6) 및 콘트롤 게이트(7)가 적층된 구조의 게이트 전극이 형성되고 상기 게이트 전극 양측부의 상기 실리콘 기판(1)에 소오스 및 드레인 영역(2 및 3)이 각각 형성된다. 상기 플로팅 게이트(5) 및 콘트롤 게이트(7)는 폴리실리콘층으로 형성되며 상기 유전체막(6)은 하부 산화막, 질화막 및 상부 산화막이 적층된 ONO(Oxide-Nitride-OXide) 구조로 형성된다. 여기서 상기 플로팅 게이트(5) 및 콘트롤 게이트(7)는 620℃의 온도에서 SiH4가스를 이용하여 폴리실리콘을 증착하고 상압 및 880℃이상의 고온에서 POCl3와 같은 액체 소오스(Liquid Source)를 이용한 도핑 공정으로 상기 폴리실리콘내에 인(P)과 같은 불순물 이온을 도핑하므로써 형성된다. 또한 900℃이상의 온도에서 상기 폴리실리콘의 표면을 50 내지 130Å의 두께로 산화시켜 상기 유전체막(6)을 구성하는 하부 산화막을 형성한다. 그런데 상기와 같이 폴리실리콘층 및 유전체막을 형성하는 경우 도핑 공정시의 온도와 산화 공정시의 온도 차이가 작기 때문에 도 2에 도시된 바와 같이 상기 폴리실리콘층의 그레인(5A)과 그레인(5A)이 접하는 계면(5B)에 많은 량의 불순물 이온이 침전된 상태로 존재하게 된다. 그리고 이는 상기 하부 산화막을 형성하기 위한 산화 공정시 산화 속도를 증가시키는 요인으로 작용하는 동시에 불순물 이온의 함유로 인해 질이 낮은 산화막(6A)이 형성되는 요인으로 작용한다. 그러므로 상기와 같이 형성된 플래쉬 메모리 셀은 동작시 상기 유전체막(6)의 국부(즉, 상기 폴리실리콘층의 그레인 계면부)를 통한 집중적인 저하(Charge)의 누설로 인해 상기 유전체막(6)의 항복전압(Breakdown Voltage)이 낮아지고, 이에 따라 상기 플로팅 게이트(5)의 프로그램 전압값이 낮아진다. 따라서 상기 플로팅 게이트(5)에 프로그램된 데이터를 독출(Read)하는 동작이 반복될수록 전하의 누설량이 증가하여 데이터 보존 시간(Data Retention Time)이 점점 감소된다.A typical flash memory cell includes a gate electrode having a structure in which a tunnel oxide film 4, a floating gate 5, a dielectric film 6, and a control gate 7 are stacked on a silicon substrate 1 as shown in FIG. 1. And source and drain regions 2 and 3 are formed in the silicon substrate 1 at both sides of the gate electrode. The floating gate 5 and the control gate 7 are formed of a polysilicon layer, and the dielectric layer 6 is formed of an oxide-nitride-OXide (ONO) structure in which a lower oxide film, a nitride film, and an upper oxide film are stacked. Here, the floating gate 5 and the control gate 7 deposit polysilicon using SiH 4 gas at a temperature of 620 ° C. and doping using a liquid source such as POCl 3 at atmospheric pressure and a high temperature of 880 ° C. or higher. It is formed by doping impurity ions such as phosphorus (P) in the polysilicon in the process. Further, the surface of the polysilicon is oxidized to a thickness of 50 to 130 kPa at a temperature of 900 ° C. or higher to form a lower oxide film constituting the dielectric film 6. However, when the polysilicon layer and the dielectric film are formed as described above, since the temperature difference during the doping process and the oxidation process is small, as shown in FIG. 2, the grains 5A and 5A of the polysilicon layer are separated. A large amount of impurity ions are present at the interface 5B in contact with each other. This acts as a factor of increasing the oxidation rate during the oxidation process for forming the lower oxide film and at the same time as a factor of forming a low quality oxide film 6A due to the inclusion of impurity ions. Therefore, the flash memory cell formed as described above may cause the leakage of the dielectric film 6 due to the leakage of concentrated charge through the local portion of the dielectric film 6 (ie, the grain interface of the polysilicon layer). The breakdown voltage is lowered, thereby lowering the program voltage value of the floating gate 5. Therefore, as the operation of reading data programmed into the floating gate 5 is repeated, the leakage of charge increases, and the data retention time gradually decreases.
따라서 본 발명은 폴리실리콘을 증착한 후 실시되는 불순물 이온 도핑 및 열처리 공정을 개선하므로써 상기한 단점을 해소할 수 있는 폴리실리콘층 형성 방법을 제공하는데 그 목적이 있다. 상기한 목적을 달성하기 위한 본 발명은 실리콘 기판상에 폴리실리콘을 증착한 후 상기 실리콘 기판을 질소 가스 분위기의 반응로 내부로 로드하는 단계와, 상기 단계로부터 상기 반응로 내부의 온도를 상승시키기 위한 램프-엎 공정을 실시한 후 상기 반응로 내부의 온도를 안정화시키는 단계와, 상기 단계로부터 잔류된 가스를 완전히 외부로 배출시킨 후 상기 폴리실리콘내에 불순물 이온을 도핑시키는 단계와, 상기 단계로부터 상기 도핑된 불순물 이온을 내부 확산시키기 위하여 질소 가스 분위기하에서 열처리를 실시한 후 상기 반응로 내부의 온도를 하강시키기 위한 램프-다운 공정을 실시하는 단계와, 상기 단계로부터 상기 반응로 내부를 정화시키고 상기 실리콘 기판을 상기 반응로 외부로 언로드시키는 단계로 이루어지는 것을 특징으로 하며, 상기 폴리실리콘은 600 내지 700℃ 온도 및 150 내지 250mT압력이 유지되는 저압화학상증착 장비에서 SiH4 가스의 반응에 의해 증착되고, 상기 도핑 공정 및 열처리는 850 내지 900℃의 온도에서 실시되는 것을 특징으로 한다. 또한 상기 도핑 공정은 10 내지 30 SLPM의 질소, 0.4 내지 0.8 SLPM의 산소 그리고 POCl3가 플로우되는 상태에서 실시되며, 상기 POCl3는 0.05 내지 0.07g/분의 속도로 플로우되는 것을 특징으로 한다.Therefore, an object of the present invention is to provide a method for forming a polysilicon layer that can solve the above-mentioned disadvantages by improving the impurity ion doping and heat treatment processes performed after the deposition of polysilicon. The present invention for achieving the above object is to load the silicon substrate into the reactor in a nitrogen gas atmosphere after depositing polysilicon on a silicon substrate, and from the step to increase the temperature inside the reactor Stabilizing the temperature inside the reactor after the ramp-up process; doping impurity ions into the polysilicon after completely discharging the remaining gas from the step; and Performing a heat-treatment under a nitrogen gas atmosphere to internally diffuse the impurity ions, and then performing a ramp-down process for lowering the temperature inside the reactor, purifying the inside of the reactor from the step and removing the silicon substrate from the Unloading to the outside of the reactor characterized in that The polysilicon is deposited by reaction of SiH 4 gas in a low pressure chemical vapor deposition apparatus maintaining a temperature of 600 to 700 ° C. and a pressure of 150 to 250 mT, and the doping process and heat treatment are performed at a temperature of 850 to 900 ° C. do. In addition, the doping process is carried out in a state of flowing nitrogen of 10 to 30 SLPM, oxygen of 0.4 to 0.8 SLPM and POCl 3 , the POCl 3 is characterized in that flow at a rate of 0.05 to 0.07g / min.
도 1은 일반적인 플래쉬 메모리 셀의 단면도.1 is a cross-sectional view of a typical flash memory cell.
도 2는 도 1에 도시된 A부분의 상세도.FIG. 2 is a detailed view of portion A shown in FIG. 1. FIG.
도 3은 본 발명에 따른 폴리실리콘층 형성 방법을 설명하기 위한 공정도.Figure 3 is a process chart for explaining a polysilicon layer forming method according to the present invention.
*도면의 주요 부분에 대한 기호설명** Description of Symbols on Main Parts of Drawing *
1: 실리콘 기판2 : 소오스 영역1: silicon substrate 2: source region
3: 드레인 영역4: 터널 산화막3: drain region 4: tunnel oxide film
5: 플로팅 게이트5A: 그레인5: floating gate 5A: grain
5B: 계면6: 유전체막5B: Interface 6: Dielectric Film
6A: 산화막7: 콘트롤 게이트6A: oxide film 7: control gate
본 발명은 형성된 폴리실리콘층의 표면을 산화시켜 유전체막을 형성하는 경우, 예를 들어 플래쉬 메모리 셀의 플로팅 게이트로 이용되는 폴리실리콘층의 표면을 산화시켜 유전체막으로 이용되는 산화막을 형성하는 경우 상기 폴리실리콘층의 그레인 계면에 침전된 불순물 이온으로 인한 산화막의 특성 저하를 방지하기 위하여 폴리실리콘층 형성 공정을 개선한 것이다. 그러면 이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.According to the present invention, when the surface of the polysilicon layer formed is oxidized to form a dielectric film, for example, when the surface of the polysilicon layer used as a floating gate of a flash memory cell is oxidized to form an oxide film used as a dielectric film, the poly The polysilicon layer forming process is improved to prevent deterioration of the oxide film due to impurity ions deposited at the grain interface of the silicon layer. Next, the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 폴리실리콘층 형성 방법을 설명하기 위한 공정도로서;3 is a process chart for explaining the polysilicon layer forming method according to the present invention;
먼저, 600 내지 700℃ 온도 및 150 내지 250mT 압력이 유지되는 저압화학기상증착(LPCVD)장비에서 SiH4 가스의 반응을 이용하여 실리콘 기판상에 폴리실리콘을 증착한 후 상기 실리콘 기판을 700 내지 800℃온도 및 질소(N2) 가스분위기의 반응로 내부로 로드(Load) 하고 5 내지 20분동안 대기한다. 그리고 분당 5℃의 속도로 상기 반응로 내부의 온도를 850 내지 900℃까지 상승시키기 위한 램프-엎(Lamp-Up) 공정을 실시한 후 상기 반응로 내부의 온도를 안정화시킨다. 이후 상기 반응로 내부에 잔류된 가스를 완전히 외부로 배출시킨 후 상기 폴리실리콘내에 인(P)과 같은 불순물 이온을 도핑시킨다. 이때 상기 반응로 내부로 10 내지 30 SLPM의 질소(N2), 0.4 내지 0.8 SLPM의 산소(O2) 그리고 POCl3를 플로우(Flow)시키는데, 상기 POCl3는 0.05 내지 0.07g/분의 속도로 플로우시킨다. 상기 도핑 공정이 완료되면 질소(N2) 가스 분위기하에서 30 내지 60분동안 열처리를 실시하여 상기 도핑된 불순물 이온이 상기 폴리실리콘층 내부로 완전히 확산되도록 한다. 그리고 상기 반응로 내부의 온도를 하강시키기 위한 램프-다운(Lamp-Down) 공정을 실시한 후 상기 반응로 내부를 정화시키고 상기 실로콘 기판을 상기 반응로 외부로 언로드(Unload)시킨다.First, polysilicon is deposited on a silicon substrate using SiH4 gas in a low pressure chemical vapor deposition (LPCVD) apparatus having a temperature of 600 to 700 ° C. and a pressure of 150 to 250 mT, and then the silicon substrate is 700 to 800 ° C. And load into the reactor of a nitrogen (N 2 ) gas atmosphere and wait for 5 to 20 minutes. After the ramp-up process for raising the temperature inside the reactor to 850 to 900 ° C. at a rate of 5 ° C. per minute, the temperature inside the reactor is stabilized. Thereafter, the gas remaining in the reactor is completely discharged to the outside and then doped with impurity ions such as phosphorus (P) in the polysilicon. The sikineunde nitrogen (N2), oxygen (O 2) and the flow (Flow) of POCl 3 in the range of 0.4 to 0.8 SLPM of from 10 to 30 SLPM with the reactor interior, the POCl 3 is a flow at a rate of 0.05 to 0.07g / min. Let's do it. When the doping process is completed, heat treatment is performed for 30 to 60 minutes in a nitrogen (N 2 ) gas atmosphere so that the doped impurity ions are completely diffused into the polysilicon layer. After the ramp-down process for lowering the temperature inside the reactor, the inside of the reactor is purged and the silocon substrate is unloaded to the outside of the reactor.
여기서 상기와 같이 이루어지는 본 발명을 플래쉬 메모리 셀의 제조 과정에 적용하는 경우 후속 유전체막을 형성하는 고정은 다음과 같이 이루어진다.When the present invention made as described above is applied to a manufacturing process of a flash memory cell, fixing to form a subsequent dielectric film is performed as follows.
먼저, 상기와 같이 형성된 폴리실리콘층의 표면에 성장된 자연 산화막을 제거시킨다. 그리고 900℃온도 및 상압이 유지되는 반응로내에 희석된 산소(O2) 가스를 공급하며 상기 폴리실리콘층의 표면을 산화시켜 50 내지 130Å두께의 하부산화막을 형성한다. 이후 상기 하부 산화막상에 60 내지 120Å두께의 질화막을 증착하고 상기 질화막상에 10 내지 30Å두께의 상부 산화막을 형성하여 ONO 구조를 갖는 유전체막의 형성을 완료한다.First, the natural oxide film grown on the surface of the polysilicon layer formed as described above is removed. In addition, a diluted oxygen (O 2 ) gas is supplied into the reactor maintained at 900 ° C. and atmospheric pressure, and the surface of the polysilicon layer is oxidized to form a lower oxide film having a thickness of 50 to 130 μm. Thereafter, a nitride film having a thickness of 60 to 120 GPa is deposited on the lower oxide film, and an upper oxide film having a thickness of 10 to 30 GPa is formed on the nitride film to complete formation of a dielectric film having an ONO structure.
이때, 상기 폴리실리콘층에는 도핑된 불순물 이온이 상기 열처리에 의해 균일하게 내부 확산되어 있으며, 한 상기 도핑 공정시 실시되는 열처리 온도와 산화 공정시의 온도 차이가 매우 작기 때문에 그레인 계면에는 불순물 이온이 매우 적게 침전된다. 그러므로 상기 하부 산화막은 균일하고 불순물 이온이 포함되지 않은 양호한 특성을 갖게 된다.At this time, the doped impurity ions are uniformly diffused into the polysilicon layer by the heat treatment, and the impurity ions are very large at the grain interface because the temperature difference between the heat treatment temperature and the oxidation process performed during the doping process is very small. Less precipitate. Therefore, the lower oxide film has good characteristics that are uniform and do not contain impurity ions.
상술한 바와 같이 본 발명에 의하면 폴리실리콘을 증착한 후 실시되는 불순물 이동 도핑 및 열처리 공정을 개선하므로써 폴리실리콘내의 불순물 이온의 분포를 균일하게 만들고 그레인 계면에 침전되는 불순물 이온의 량이 감소되도록 한다. 그러므로 본 발명을 메모리 셀의 제조에 적용하는 경우 유전체막으로 이용되는 산화막의 질이 양호해질 수 있고, 따라서 데이터 보존 시간이 증가되어 소자의 신뢰성이 향상될 수 있는 효과가 있다.As described above, according to the present invention, by improving the impurity transfer doping and heat treatment processes performed after the deposition of polysilicon, the distribution of impurity ions in the polysilicon is made uniform and the amount of impurity ions deposited at the grain interface is reduced. Therefore, when the present invention is applied to the manufacture of a memory cell, the quality of the oxide film used as the dielectric film can be improved, and thus the data retention time can be increased, thereby improving the reliability of the device.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960073617A KR19980054454A (en) | 1996-12-27 | 1996-12-27 | Polysilicon Cone Formation Method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960073617A KR19980054454A (en) | 1996-12-27 | 1996-12-27 | Polysilicon Cone Formation Method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980054454A true KR19980054454A (en) | 1998-09-25 |
Family
ID=66382939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960073617A KR19980054454A (en) | 1996-12-27 | 1996-12-27 | Polysilicon Cone Formation Method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19980054454A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6459858A (en) * | 1987-08-31 | 1989-03-07 | Toshiba Corp | Manufacture of semiconductor device |
| KR920007124A (en) * | 1990-09-04 | 1992-04-28 | 김광호 | Manufacturing Method of Poly-Emitter Bipolar Transistor |
| US5244831A (en) * | 1992-05-04 | 1993-09-14 | Zilog, Inc. | Method of doping a polysilicon layer on a semiconductor wafer |
| JPH08148680A (en) * | 1994-11-25 | 1996-06-07 | Sony Corp | Threshold voltage control method |
| KR970003470A (en) * | 1995-06-16 | 1997-01-28 | 김주용 | Method of manufacturing silicon electrode |
-
1996
- 1996-12-27 KR KR1019960073617A patent/KR19980054454A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6459858A (en) * | 1987-08-31 | 1989-03-07 | Toshiba Corp | Manufacture of semiconductor device |
| KR920007124A (en) * | 1990-09-04 | 1992-04-28 | 김광호 | Manufacturing Method of Poly-Emitter Bipolar Transistor |
| US5244831A (en) * | 1992-05-04 | 1993-09-14 | Zilog, Inc. | Method of doping a polysilicon layer on a semiconductor wafer |
| JPH08148680A (en) * | 1994-11-25 | 1996-06-07 | Sony Corp | Threshold voltage control method |
| KR970003470A (en) * | 1995-06-16 | 1997-01-28 | 김주용 | Method of manufacturing silicon electrode |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4001960B2 (en) | Method for manufacturing a semiconductor device having a nitrided oxide dielectric layer | |
| US6319775B1 (en) | Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device | |
| US6265268B1 (en) | High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device | |
| US7585725B2 (en) | Use of dilute steam ambient for improvement of flash devices | |
| KR20050014317A (en) | semiconductor device with floating trap type nonvolatile memory cell and fabricating method thereof | |
| US5716891A (en) | Fabrication process of semiconductor device | |
| KR100466312B1 (en) | Method of manufacturing semiconductor device having an ONO layer | |
| JP2002217317A (en) | Non-volatile semiconductor storage device and its manufacturing method | |
| US7148109B2 (en) | Method for manufacturing flash memory device | |
| KR100482751B1 (en) | Method of manufacturing semiconductor device | |
| US6350707B1 (en) | Method of fabricating capacitor dielectric | |
| KR100469128B1 (en) | Method of forming floating gate of non-volatile memory device having self-aligned shallow trench isolation | |
| US6777764B2 (en) | ONO interpoly dielectric for flash memory cells and method for fabricating the same using a single wafer low temperature deposition process | |
| US20020168869A1 (en) | Method for fabricating an ONO layer | |
| US7132328B2 (en) | Method of manufacturing flash memory device | |
| KR19980054454A (en) | Polysilicon Cone Formation Method | |
| KR100586006B1 (en) | Method of forming a gate structure of a non-volatile memory device and apparatus for performing the method | |
| KR100255167B1 (en) | Method for forming polysilicon electrode of semiconductor device | |
| US6709927B1 (en) | Process for treating ONO dielectric film of a floating gate memory cell | |
| KR100246776B1 (en) | Method for forming oxidation film of semiconductor device | |
| KR100647002B1 (en) | Method of oxidation for polycide in a flash EEPROM | |
| KR100200707B1 (en) | Fabrication method of semiconductor device | |
| KR100274352B1 (en) | Method of manufacturing a flash memory cell | |
| KR100223676B1 (en) | Process for forming interlayer insulator of memory cell in non-volatile semiconductor memory device | |
| KR940005294B1 (en) | Manufacturing method of mosfet |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |