KR102679997B1 - Printed circuit board - Google Patents

Abstract

A printed circuit board according to one aspect of the present invention includes a printed circuit board having a plurality of device mounting units, a first laminate including a plurality of insulating layers and a first circuit; a cavity formed in the first laminate and open to an upper surface of the first laminate; and a second laminate including a plurality of resin layers and a second circuit stacked in the cavity, wherein the first circuit includes a connection pad exposed by the cavity, and the second laminate is at the bottom layer. It includes a connection via that penetrates the resin layer and contacts the connection pad, and the second circuit is electrically connected to a plurality of device mounting units.

Description

Printed circuit board {PRINTED CIRCUIT BOARD}

The present invention relates to printed circuit boards.

As the computer industry develops, technology for integrated circuits (die) that can be produced with higher performance and lower cost is developing. Accordingly, technology for a package substrate including multiple dies is also being developed.

US Registration Notice No. 8754514

According to one aspect of the present invention, a printed circuit board having a plurality of device mounting units, comprising: a first laminate including a plurality of insulating layers and a first circuit; a cavity formed in the first laminate and open to an upper surface of the first laminate; and a second laminate including a plurality of resin layers and a second circuit stacked in the cavity, wherein the first circuit includes a connection pad exposed by the cavity, and the second laminate is at the bottom layer. A printed circuit board is provided that penetrates the resin layer and includes a connection via that contacts the connection pad, and the second circuit is electrically connected to a plurality of device mounting units.

A portion of the second circuit may electrically connect the plurality of device mounting portions to each other, and a portion of the second circuit may electrically connect one of the device mounting portions to the connection via.

The resin layer may include a photosensitive resin, and the thickness of the resin layer may be smaller than the thickness of the insulating layer.

The circuit width of the first circuit may be larger than the circuit width of the second circuit.

The first circuit located on the uppermost layer of the first laminate may be embedded in the upper surface of the insulating layer located on the uppermost layer, and the first circuit located on the uppermost layer of the first laminate may be embedded in the insulating layer located on the uppermost layer. It may protrude more.

The top surface of the second laminate may be located below the height of the top surface of the first laminate.

It may further include a second resin layer formed on the upper surface of the first laminate and the upper surface of the second laminate. A via hole may be formed in the insulating layer located on the uppermost layer, a via may be formed within the via hole, and the second resin layer may fill the inside of the via hole to surround the via.

It may further include a solder resist layer laminated on the second resin layer. It may further include a third circuit formed on the second resin layer and electrically connected to the second circuit.

It may further include a solder resist layer laminated on the first laminate and the second laminate. It may further include a metal post that penetrates the solder resist layer and provides the device mounting portion. The metal post includes a post via penetrating the solder resist layer; and a post pad formed on the post via to protrude beyond the solder resist layer.

1 is a diagram showing a printed circuit board according to a first embodiment of the present invention.
Figure 2 is a diagram showing a package including a printed circuit board according to the first embodiment of the present invention.
Figure 3 is a diagram showing a printed circuit board according to a second embodiment of the present invention.
Figure 4 is a diagram showing a printed circuit board according to a third embodiment of the present invention.
Figure 5 is a diagram showing a printed circuit board according to a fourth embodiment of the present invention.
Figure 6 is a diagram showing a printed circuit board according to a fifth embodiment of the present invention.
Figure 7 is a diagram showing a package including a printed circuit board according to a fifth embodiment of the present invention.
Figure 8 is a diagram showing a printed circuit board according to a sixth embodiment of the present invention.
Figure 9 is a diagram showing a printed circuit board according to a seventh embodiment of the present invention.
10 and 11 are diagrams showing a method of manufacturing a package according to an embodiment of the present invention.
12 and 13 are diagrams showing a method of manufacturing a package according to another embodiment of the present invention.

Embodiments of the printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, identical or corresponding components are assigned the same drawing numbers and overlapping descriptions thereof are provided. Decided to omit it.

In addition, terms such as first, second, etc. used below are merely identifiers to distinguish identical or corresponding components, and the same or corresponding components are not limited by terms such as first, second, etc. no.

In addition, coupling does not mean only the case of direct physical contact between each component in the contact relationship between each component, but also means that another component is interposed between each component, and the component is in that other component. It should be used as a concept that encompasses even the cases where each is in contact.

Hereinafter, various embodiments of the printed circuit board will be separately described, but it is not excluded that the description of one embodiment can be applied to other embodiments. Description of one embodiment may also be applied to other embodiments unless there is an incompatible relationship.

printed circuit board

1st Example

FIG. 1 is a diagram showing a printed circuit board according to a first embodiment of the present invention, and FIG. 2 is a diagram showing a package including a printed circuit board according to a first embodiment of the present invention.

A printed circuit board according to an embodiment of the present invention may provide a plurality of device mounting units so that a plurality of electronic devices can be mounted. The device mounting portion is an area where electronic devices are coupled and may include a plurality of mounting pads. Here, electronic devices may be selected from various sources such as active devices, passive devices, and integrated circuits, and may include chips, dies, etc.

In explaining the printed circuit board according to an embodiment of the present invention, the printed circuit board is described as having a first device mounting portion (M1) and a second device mounting portion (M2), but there are three device mounting portions. It is not ruled out that it may be more than that.

The first device mounting portion M1 and the second device mounting portion M2 are partitioned to be spaced apart from each other, and each device mounting portion may include a plurality of different mounting pads. The first electronic device (E1) is mounted on the first device mounting portion (M1), the second electronic device (E2) is mounted on the second device mounting portion (M2), and the first electronic device (E1) and the second electronic device (E1) are mounted on the first device mounting portion (M1). Each electronic device (E2) may be selected from active devices, passive devices, integrated circuits, etc. For example, the first electronic device (E1) may be a HBM, and the second electronic device (E2) may be a GPU, but are not limited thereto.

Referring to FIG. 1, a printed circuit board according to the first embodiment of the present invention may include a first laminate 100, a cavity 120, and a second laminate 200.

The first laminate 100 is formed by stacking a plurality of insulating layers 110 vertically. The insulating layer 110 is a layer made of an organic or inorganic insulating material and may include resin. The resin of the insulating layer 110 may be thermosetting or thermoplastic, and specifically, at least one of epoxy resin, imidazole resin, polyimide resin, BT (Bismaleimide Triazine) resin, and fluorine-based resin. It may include, but is not limited to.

The insulating layer 110 may include a fiber reinforcement material such as glass fiber therein, and prepreg may be used as this specific insulating layer 110. Additionally, the insulating layer 110 may contain an organic filler or an inorganic filler. The inorganic filler contained in the insulating layer 110 may be silica.

A plurality of insulating layers 110 made of the same or different materials may be stacked in turns to form the first laminate 100. Although two insulating layers 110 are shown in FIG. 1, the number of insulating layers 110 may change depending on design, etc.

A circuit may be formed in the first laminate 100, and the circuit formed in the first laminate 100 will be referred to as the first circuit C1. The first circuit C1 may be formed of metal, and the metal of the first circuit C1 may include at least one of copper, silver, nickel, palladium, platinum, gold, and aluminum.

The first circuit C1 may be formed on one surface of each insulating layer 110. When there are two insulating layers 110, the first circuit C1 may be formed of three layers. The first circuits C1 located on different layers may be electrically connected through a via (first via V1). Referring to FIG. 1, among the first circuits C1, the outermost first circuit C1' located closest to the device mounting surface is embedded in the upper surface of the outermost insulating layer 110, and the outermost first circuit (C1') In C1'), the remaining surfaces except the top surface may be covered with the outermost insulating layer 110.

The first circuit C1 may include a plurality of circuit lines. A pad may be provided at the end of each circuit line. These pads may be connected to vias such as the first via V1. Meanwhile, among the first circuits C1, the outermost first circuit C1' located closest to the device mounting surface may include a mounting pad for mounting electronic devices and provide a device mounting portion.

A cavity 120 may be formed in the first laminate 100. The cavity 120 is formed within the first laminate 100 and opens upward. However, since the lower part of the cavity 120 is not open, the cavity 120 penetrates only a portion of the thickness of the first laminate 100. As shown in FIG. 1, the depth of the cavity 120 may match the thickness of N insulating layers 110 of the first laminate 100. Additionally, the bottom of the cavity 120 may be located at the interface between the two insulating layers 110.

A portion of the first circuit C1 may be exposed by the cavity 120. Among the plurality of insulating layers 110, the first circuit C1 located on the insulating layer 110 in contact with the cavity 120 may be exposed by the cavity 120, and may be located at an end of the first circuit C1. The provided pad may be exposed. The pad of the first circuit C1 exposed by the cavity 120 may be referred to as the connection pad 300. In other words, the connection pad 300 of the first circuit C1 is exposed by the cavity 120, and the connection pad 300 is a pad of the first circuit C1 located below the cavity 120.

The second laminate 200 is formed in the cavity 120 and may be formed by stacking a plurality of resin layers 210 vertically. A plurality of resin layers 210 may be sequentially stacked within the cavity 120.

The resin layer 210 includes a resin, specifically, epoxy resin, imidazole resin, polyimide resin, liquid crystal polymer (LCP), BT (Bismaleimide Triazine) resin, and fluorine-based resin. It may include at least one, but is not limited.

The resin layer 210 may include photosensitive resin. In this case, the resin layer 210 may react to light and may be processed through a photolithography process. The resin layer 210 containing photosensitive resin may be a PID (photo imageable dielectric). Additionally, the photosensitive resin may be a positive type or a negative type.

In the case of the positive type resin layer 210, during the exposure process, the photopolymer bond in the portion that receives light is broken. Afterwards, when the development process is performed, the part where the photopolymer polymer bond is broken by receiving light is removed.

In the case of the negative type resin layer 210, during the exposure process, the part that received light undergoes a photopolymerization reaction, changing from a single structure to a three-dimensional network structure with a chain structure. When the developing process is performed, the part that did not receive light is removed. It becomes.

According to the resin layer 210 containing a photosensitive resin, a circuit and via formation process is possible through a photolithography process, so fine pattern processing can be facilitated.

The thickness of the resin layer 210 may be smaller than the thickness of the insulating layer 110. That is, the thickness of one of the plurality of resin layers 210 may be smaller than the thickness of one of the plurality of insulating layers 110. According to this, when the depth of the cavity 120 is equal to the thickness of one insulating layer 110, a plurality of resin layers 210 can be formed within the cavity 120.

The uppermost surface of the resin layer 210, that is, the upper surface of the second laminate 200, may be located on the same plane as the upper surface of the first laminate 100.

A circuit may be formed in the second laminate 200, and the circuit formed in the second laminate 200 will be referred to as a second circuit C2. The second circuit C2 may be formed of metal, and the metal of the second circuit C2 may include at least one of copper, silver, nickel, palladium, platinum, gold, and aluminum.

The second circuit C2 may be formed on one surface (upper surface) of each resin layer 210. The outermost layer (top layer) second circuit (C2') located closest to the device mounting surface is embedded in the outermost (top layer) resin layer 210, and the outermost layer second circuit (C2') located closest to the device mounting surface. ') may be located on the same plane as the top surface of the outermost first circuit (C1') located closest to the device mounting surface.

The second circuits C2 located on different layers may be connected to each other through a via (second via V2). Meanwhile, a connection via 400 that penetrates the lowermost resin layer 211 and contacts the connection pad 300 described above may be formed in the second laminate 200. That is, the connection via 400 can electrically connect the connection pad 300 and the second circuit C2.

The present invention is characterized in that the resin layer 210 is formed directly in the cavity 120 of the first laminate 100. That is, a plurality of resin layers 210 are sequentially stacked in the cavity 120 of the first laminate 100 to form the second laminate 200, which is manufactured separately. It is distinguished from the structure that is later inserted into the cavity 120 and attached to the first laminate 100.

In addition, a connection via 400 is formed on the bottom of the cavity 120 to contact the connection pad 300, and the first stack 100 and the second stack 200 are electrically connected by the connection via 400. This can be done. Accordingly, there is no need for soldering or use of adhesive to connect the first laminate 100 and the second laminate 200.

The circuit width of the first circuit (C1) may be larger than the circuit width of the second circuit (C2). The circuit thickness of the first circuit (C1) may be greater than the circuit thickness of the second circuit (C2). The second circuit C2 may have a finer pitch than the first circuit C1. The circuit density of the second circuit C2 may be greater than that of the first circuit C1.

The first circuit (C1) and the second circuit (C2) may be formed through a substrate process such as a SAP process (Semi-Additive Process), an M-SAP process (Modified Semi-Additive Process), or a tenting process. Here, the second circuit (C2) may be formed through a SAP process, and the first circuit (C1) may be formed through a tenting process, etc., but are not limited thereto.

The size of the first via (V1) may be larger than the size of the second via (V2), and the pitch of the first via (V1) may be larger than the pitch of the second via (V2). Additionally, the connection via 400 may have the same size as the second via V2.

The second circuit C2 may include a plurality of circuit lines. A pad may be provided at the end of each circuit line. This pad may be connected to the second via (V2). Meanwhile, among the second circuits (C2), the outermost second circuit (C2') located closest to the device mounting surface may include a mounting pad for mounting electronic devices and provide a device mounting portion.

Each of the plurality of device mounting units is formed over both the first stack 100 and the second stack 200. That is, the first device mounting portion M1 is provided on the first stack 100 and the second stack 200, and the second device mounting portion M2 is also provided on the first stack 100 and the second stack 200. It is provided on the laminate 200. The upper surface of the second stack 200 may be divided into multiple sections to provide a plurality of device mounting units.

Referring to FIG. 2(a), the first electronic device (E1) is mounted on the first device mounting portion (M1), and the second electronic device (E2) is mounted on the second device mounting portion (M2). . The first electronic device E1 is located across both the first stack 100 and the second stack 200, and the second electronic device E2 is also located across the first stack 100 and the second stack 200. It is located across all 200.

The first electronic device (E1) includes an electrode terminal (T1), and the electrode terminal (T1) is coupled to the mounting pad of the first device mounting portion (M1) of the printed circuit board with a low melting point metal member (LM). You can. The space between the first electronic element (E1) and the printed circuit board may be filled with an underfill material (F). The second electronic device (E2) includes an electrode terminal (T2), and the electrode terminal (T2) is coupled to the mounting pad of the second device mounting portion (M2) of the printed circuit board with a low melting point metal member (LM). You can. The space between the second electronic element (E2) and the printed circuit board may be filled with an underfill material (F).

As described above, the second circuit C2 may include a plurality of circuit lines. The second circuit C2 may include a circuit line electrically connected to the connection via 400. Additionally, the second circuit C2 is electrically insulated from the connection via 400 and may include a circuit line that electrically connects a plurality of device mounting units. In this case, the second circuit C2 can provide various signal transmission paths (see arrow in FIG. 2(a)).

Figure 2(b) shows a circuit line providing a specific signal transmission path of the second circuit C2. Referring to FIG. 2(b), the second circuit C2 includes i) a circuit line (not shown) connecting the first device mounting unit M1 and the first circuit C1, and ii) a second device mounting section. a circuit line (C23) connecting the unit (M2) and the second circuit (C2); iii) a circuit line (C21, C22) connecting the first device mounting unit (M1) and the second device mounting unit (M2); It can be included. In the case of i and ii, the circuit line is electrically connected to the connection via 400, and in the case of iii, the circuit line may be electrically insulated from the connection via 400.

Here, the circuit lines (C21, C22) connecting the first device mounting portion (M1) and the second device mounting portion (M2) are bridge circuits, and connect the first electronic device (E1) and the second electronic device ( It can be responsible for the electrical connection of E2) (this can be called die to die interconnection). A plurality of bridge circuits may be formed, and the two electronic devices E1 and E2 may be connected via the second via V2.

In short, a part of the second circuit (C2) can electrically connect at least two of a plurality of device mounting units, and another part of the second circuit (C2) can electrically connect one device mounting unit and the connection via 400. You can connect with .

A solder resist layer 500 may be laminated on the upper surface of the first laminate 100 and the upper surface of the second laminate 200. An opening is formed in the solder resist layer 500, and the outermost layer circuits C1' and C2' can be exposed through the opening. In particular, the pads of the outermost layer circuits C1' and C2' are exposed through the opening, and the exposed pads can function as mounting pads. Meanwhile, the solder resist layer 500 may also be laminated on the lower surface of the first laminate 100.

2nd Example

Figure 3 is a diagram showing a printed circuit board according to a second embodiment of the present invention.

Referring to FIG. 3, in the printed circuit board according to the second embodiment, the second circuit C2′ located on the outermost layer (top layer) protrudes beyond the resin layer 210. Here, the second circuit (C2') located on the outermost layer (top layer) protrudes beyond the first laminate 100. This can be distinguished from the first embodiment in which the second circuit C2' located in the outermost layer (top layer) is embedded in the resin layer 210 and does not protrude beyond the first laminate 100.

3rd Example

Figure 4 is a diagram showing a printed circuit board according to a third embodiment of the present invention.

Referring to FIG. 4 , in the printed circuit board according to the third embodiment, the upper surface of the second laminate 200 is located below (lower) than the upper surface of the first laminate 100. According to this, the resin layer 210 does not fill the entire cavity 120, and the solder resist layer 500 may partially fill the inside of the cavity 120. This embodiment can be distinguished from the first embodiment in which the cavity 120 is completely filled with the second laminate 200. Meanwhile, the second circuit C2' located on the outermost layer (top layer) protrudes beyond the resin layer 210, but does not protrude beyond the first laminate 100.

4th Example

Figure 5 is a diagram showing a printed circuit board according to a fourth embodiment of the present invention.

Referring to FIG. 5, the printed circuit board according to the fourth embodiment includes a first laminate 100, a cavity 120, and a second laminate 200, and a second resin layer 220. More may be included.

The second resin layer 220 may fill the inside of the cavity 120 to be laminated on the second laminate 200 and may extend to the upper surface of the first laminate 100. The second resin layer 220 may be formed of the same material as the resin layer 210 of the second laminate 200, and the second resin layer 220 may include a photosensitive resin.

Referring to FIG. 5(a), a via (third via V3) penetrating the second resin layer 220 is formed on the second circuit C2', the outermost layer of the second laminate 200. And the third circuit C3 is formed on the second resin layer 220. Here, the pad of the third circuit C3 may function as a mounting pad. The third circuit C3 may have the same specifications as the second circuit C2.

In addition, as shown in FIG. 5(a), the solder resist layer 500 is laminated on the second resin layer 220, and the opening of the solder resist layer 500 is opened through the second resin layer 220. can penetrate. When both the solder resist layer 500 and the second resin layer 220 include photosensitive resin, the opening of the solder resist layer 500 may be formed through a photolithography process.

Referring to FIG. 5(b), a first via (V1') may be formed in the via hole (VH) located in the outermost insulating layer 110 of the first laminate 100. That is, the first via (V1') is formed under the outermost first circuit (C1'). Here, the second resin layer 220 may fill the inside of the via hole (VH) to surround the first via (V1').

The outermost first circuit C1' is formed on the second resin layer 220 and may provide a mounting pad.

In addition, a via (third via V3) penetrating the second resin layer 220 is formed on the second circuit C2', the outermost layer of the second laminate 200, and the second resin layer A third circuit C3 is formed on 220. Here, the pad of the third circuit C3 may function as a mounting pad.

As shown in FIG. 5 , when the second resin layer 220 is used, the adhesion between the first laminate 100 and the second laminate 200 can be improved.

5th Example

Figure 6 is a diagram showing a printed circuit board according to a fifth embodiment of the present invention. Additionally, Figure 7 is a diagram showing a package using the printed circuit board of Figure 6.

Referring to FIG. 6, the printed circuit board according to the fifth embodiment includes a first laminate 100, a cavity 120, and a second laminate 200, and a metal post 600. More may be included.

The metal post 600 may be formed to penetrate the solder resist layer 500 and may provide a mounting pad. Since the metal post 600 protrudes beyond the solder resist layer 500, the distance between the printed circuit board and the electronic device is narrowed, and the height of the low melting point metal member (LM) for mounting the electronic device can be reduced ( (see Figure 7).

The metal post 600 may include a post via 610 and a post pad 620. The post via 610 may penetrate the solder resist layer 500 and be formed on the first outermost circuit C1', the second outermost circuit C2', or the third circuit C3. The post pad 620 protrudes beyond the solder resist layer 500 and provides a mounting pad.

Meanwhile, FIG. 6(a) shows a metal post 600 added to the printed circuit board described with reference to FIG. 3, and FIG. 6(b) shows a metal post 600 added to the printed circuit board described with reference to FIG. 4. It was added. Additionally, Figure 6(c) shows a metal post 600 added to the printed circuit board described with reference to Figure 5(b). Meanwhile, Figure 7 shows a package using the printed circuit board of Figure 6(a).

6th Example

Figure 8 is a diagram showing a printed circuit board according to a sixth embodiment of the present invention.

Referring to FIG. 8 , the printed circuit board according to the sixth embodiment of the present invention may include a first stack 100, a cavity 120, and a second stack 200.

The first laminate 100 is formed by stacking a plurality of insulating layers 110 vertically. The insulating layer 110 is a layer made of an organic or inorganic insulating material and may include resin. The resin of the insulating layer 110 may be thermosetting or thermoplastic, and specifically, at least one of epoxy resin, imidazole resin, polyimide resin, BT (Bismaleimide Triazine) resin, and fluorine-based resin. It may include, but is not limited to.

The insulating layer 110 may include a fiber reinforcement material such as glass fiber therein, and prepreg may be used as this specific insulating layer 110. Additionally, the insulating layer 110 may contain an organic filler or an inorganic filler. The inorganic filler contained in the insulating layer 110 may be silica.

A plurality of insulating layers 110 made of the same or different materials may be stacked in turns to form the first laminate 100. Although two insulating layers 110 are shown in FIG. 1, the number of insulating layers 110 may change depending on design, etc.

A circuit may be formed in the first laminate 100, and the circuit formed in the first laminate 100 will be referred to as the first circuit C1. The first circuit C1 may be formed of metal, and the metal of the first circuit C1 may include at least one of copper, silver, nickel, palladium, platinum, gold, and aluminum.

The first circuit C1 may be formed on one surface of each insulating layer 110. The first circuits C1 located on different layers may be electrically connected through a via (first via V1). Referring to FIG. 8, among the first circuits C1, the uppermost first circuit C1' located closest to the device mounting surface protrudes beyond the uppermost insulating layer 110, and the lowest layer located furthest from the device mounting surface. The first circuit (C1") may be buried in the lower surface of the lowest layer insulating layer 110, and the remaining surfaces of the lowermost first circuit (C1") except for the lower surface may be covered with the lowest layer insulating layer 110.

The first circuit C1 may include a plurality of circuit lines. A pad may be provided at the end of each circuit line. These pads may be connected to vias such as the first via V1. Meanwhile, among the first circuits C1, the outermost first circuit C1' located closest to the device mounting surface may include a mounting pad for mounting electronic devices and provide a device mounting portion.

A cavity 120 may be formed in the first laminate 100. The cavity 120 is formed within the first laminate 100 and opens upward. However, since the lower part of the cavity 120 is not open, the cavity 120 penetrates only a portion of the thickness of the first laminate 100. As shown in FIG. 1, the depth of the cavity 120 may be more than the thickness of N insulating layers 110 of the first laminate 100, and the bottom of the cavity 120 is the interface between the two insulating layers 110. and may not be located on the same plane.

A portion of the first circuit C1 may be exposed by the cavity 120. Among the plurality of insulating layers 110, the first circuit C1 located on the insulating layer 110 in contact with the cavity 120 may be exposed by the cavity 120, and may be located at an end of the first circuit C1. The provided pad may be exposed. The pad of the first circuit C1 exposed by the cavity 120 may be referred to as the connection pad 300. In other words, the connection pad 300 of the first circuit C1 is exposed by the cavity 120, and the connection pad 300 is a pad of the first circuit C1 located below the cavity 120.

The second laminate 200 is formed in the cavity 120 and may be formed by stacking a plurality of resin layers 210 vertically. A plurality of resin layers 210 may be sequentially stacked within the cavity 120.

The resin layer 210 includes a resin, specifically, epoxy resin, imidazole resin, polyimide resin, liquid crystal polymer (LCP), BT (Bismaleimide Triazine) resin, and fluorine-based resin. It may include at least one, but is not limited.

The resin layer 210 may include photosensitive resin. In this case, the resin layer 210 may react to light and may be processed through a photolithography process. The resin layer 210 containing photosensitive resin may be a PID (photo imageable dielectric). Additionally, the photosensitive resin may be a positive type or a negative type.

In the case of the positive type resin layer 210, during the exposure process, the photopolymer bond in the portion that receives light is broken. Afterwards, when the development process is performed, the part where the photopolymer polymer bond is broken by receiving light is removed.

In the case of the negative type resin layer 210, during the exposure process, the part that received light undergoes a photopolymerization reaction, changing from a single structure to a three-dimensional network structure with a chain structure. When the developing process is performed, the part that did not receive light is removed. It becomes.

According to the resin layer 210 containing a photosensitive resin, a circuit and via formation process is possible through a photolithography process, so fine pattern processing can be facilitated.

The thickness of the resin layer 210 may be smaller than the thickness of the insulating layer 110. That is, the thickness of one of the plurality of resin layers 210 may be smaller than the thickness of one of the plurality of insulating layers 110.

The uppermost surface of the resin layer 210, that is, the upper surface of the second laminate 200, may be located on the same plane as the upper surface of the first laminate 100.

A circuit may be formed in the second laminate 200, and the circuit formed in the second laminate 200 will be referred to as a second circuit C2. The second circuit C2 may be formed of metal, and the metal of the second circuit C2 may include at least one of copper, silver, nickel, palladium, platinum, gold, and aluminum.

The second circuit C2 may be formed on one surface (upper surface) of each resin layer 210. The outermost layer (top layer) second circuit (C2') located closest to the device mounting surface protrudes beyond the outermost (top layer) resin layer 210, and the outermost layer second circuit (C2') located closest to the device mounting surface. ') may be located on the same plane as the top surface of the outermost first circuit (C1') located closest to the device mounting surface. However, unlike the illustration in FIG. 8, the thickness of the second outermost circuit (C2') may be smaller than the thickness of the first outermost circuit (C1'). In this case, the top surfaces of the two outermost layer circuits C1' and C2' are not located on the same plane.

The second circuits C2 located on different layers may be connected to each other through a via (second via V2). Meanwhile, a connection via 400 that penetrates the lowermost resin layer 211 and contacts the connection pad 300 described above may be formed in the second laminate 200. That is, the connection via 400 can electrically connect the connection pad 300 and the second circuit C2.

The circuit width of the first circuit (C1) may be larger than the circuit width of the second circuit (C2). The circuit thickness of the first circuit (C1) may be greater than the circuit thickness of the second circuit (C2). The second circuit C2 may have a finer pitch than the first circuit C1. The circuit density of the second circuit C2 may be greater than that of the first circuit C1.

The size of the first via (V1) may be larger than the size of the second via (V2), and the pitch of the first via (V1) may be larger than the pitch of the second via (V2). Additionally, the connection via 400 may have the same size as the second via V2.

The second circuit C2 may include a plurality of circuit lines. A pad may be provided at the end of each circuit line. This pad may be connected to the second via (V2). Meanwhile, among the second circuits (C2), the outermost second circuit (C2') located closest to the device mounting surface may include a mounting pad for mounting electronic devices and provide a device mounting portion.

Each of the plurality of device mounting units is formed over both the first stack 100 and the second stack 200. That is, the first device mounting portion M1 is provided on the first stack 100 and the second stack 200, and the second device mounting portion M2 is also provided on the first stack 100 and the second stack 200. It is provided on the laminate 200. The upper surface of the second stack 200 may be divided into multiple sections to provide a plurality of device mounting units.

The first electronic device (E1) is mounted on the first device mounting portion (M1), and the second electronic device (E2) is mounted on the second device mounting portion (M2). The first electronic device E1 is located across both the first stack 100 and the second stack 200, and the second electronic device E2 is also located across the first stack 100 and the second stack 200. It is located across all 200.

The first electronic device (E1) includes an electrode terminal (T1), and the electrode terminal (T1) is coupled to the mounting pad of the first device mounting portion (M1) of the printed circuit board with a low melting point metal member (LM). You can. The space between the first electronic element (E1) and the printed circuit board may be filled with an underfill material (F). The second electronic device (E2) includes an electrode terminal (T2), and the electrode terminal (T2) is coupled to the mounting pad of the second device mounting portion (M2) of the printed circuit board with a low melting point metal member (LM). You can. The space between the second electronic element (E2) and the printed circuit board may be filled with an underfill material (F).

As described above, the second circuit C2 may include a plurality of circuit lines. The second circuit C2 may include a circuit line electrically connected to the connection via 400. Additionally, the second circuit C2 is electrically insulated from the connection via 400 and may include a circuit line that electrically connects a plurality of device mounting units. In this case, the second circuit (C2) can provide various signal transmission paths.

The second circuit (C2) is i) a circuit line connecting the first device mounting portion (M1) and the first circuit (C1), ii) connecting the second device mounting portion (M2) and the second circuit (C2). iii) a circuit line connecting the first device mounting portion (M1) and the second device mounting portion (M2). In the case of i and ii, the circuit line is electrically connected to the connection via 400, and in the case of iii, the circuit line may be electrically insulated from the connection via 400.

In short, a part of the second circuit (C2) can electrically connect at least two of a plurality of device mounting units, and another part of the second circuit (C2) can electrically connect one device mounting unit and the connection via 400. You can connect with .

A solder resist layer 500 may be laminated on the upper surface of the first laminate 100 and the upper surface of the second laminate 200. An opening is formed in the solder resist layer 500, and the outermost layer circuits C1' and C2' can be exposed through the opening. In particular, the pads of the outermost layer circuits C1' and C2' are exposed through the opening, and the exposed pads can function as mounting pads. Meanwhile, the solder resist layer 500 may be laminated on the lower surface of the first laminate 100 to cover the lowermost first circuit (C1”).

Lesson 7 Example

Figure 9 is a diagram showing a printed circuit board according to a seventh embodiment of the present invention.

Referring to FIG. 9, the printed circuit board according to the seventh embodiment includes a first laminate 100, a cavity 120, a second laminate 200, a second resin layer 220, and /Or it may further include a metal post 600.

The second resin layer 220 may fill the inside of the cavity 120 to be laminated on the second laminate 200 and may extend to the upper surface of the first laminate 100. The second resin layer 220 may be formed of the same material as the resin layer 210 of the second laminate 200, and the second resin layer 220 may include a photosensitive resin.

A first via (V1') may be formed in the via hole (VH) located in the outermost insulating layer 110 of the first laminate 100. That is, the first via (V1') is formed under the outermost first circuit (C1'). Here, the second resin layer 220 may fill the inside of the via hole (VH) to surround the first via (V1').

The outermost first circuit (C1') may be formed on the second resin layer (220). A via (third via V3) penetrating the second resin layer 220 is formed on the second circuit C2', the outermost layer of the second laminate 200, and the second resin layer 220 ) A third circuit (C3) is formed on the.

The solder resist layer 500 is laminated on the second resin layer 220 and may also be laminated on the lower surface of the first laminate 100.

The metal post 600 may be formed to penetrate the solder resist layer 500 and may provide a mounting pad. Since the metal post 600 protrudes beyond the solder resist layer 500, the distance between the printed circuit board and the electronic device is narrowed, and the height of the low melting point metal member (LM) for mounting the electronic device can be reduced.

The metal post 600 may include a post via 610 and a post pad 620. The post via 610 may penetrate the solder resist layer 500 and be formed on the first outermost circuit C1', the second outermost circuit C2', or the third circuit C3. The post pad 620 protrudes beyond the solder resist layer 500 and provides a mounting pad.

Printed circuit board manufacturing method

10 and 11 are diagrams showing a method of manufacturing a printed circuit board and a package including the same according to an embodiment of the present invention. Figures 10 and 11 illustrate a method of manufacturing the printed circuit board shown in Figure 3, but the manufacturing method can also be applied to a method of manufacturing other printed circuit boards.

Referring to FIG. 10(a), a plurality of insulating layers 110 are stacked up and down, a first circuit C1 is formed, and a first laminate 100 is prepared. Although not shown, the first laminate 100 can be formed using a carrier. That is, after sequentially stacking a plurality of insulating layers 110 on a carrier and forming a first circuit C1 on one side of each layer, the carrier is removed to prepare the first laminate 100. Here, surface a is the carrier attachment surface, and the first circuit (C1) on the carrier attachment surface side may be an embedded circuit. Also, here, the a-plane becomes the device mounting surface.

Referring to FIG. 10(b), a cavity 120 is formed in the first laminate 100. Cavity 120 may be formed through laser processing. A portion of the first circuit C1 may be exposed by the cavity 120, and in particular, a pad of the first circuit C1 may be exposed, and the exposed pad becomes the connection pad 300.

Referring to FIGS. 10(c) and 10(d), a plurality of resin layers 210 are stacked vertically in the cavity 120 and a second circuit C2 is formed, thereby forming a second laminate 200. form First, as shown in FIG. 10(c), the lowest resin layer 211 is formed on the bottom of the cavity 120. The resin layer 210 may be formed by a spray method. As shown in FIG. 10(d), the lowest resin layer 211 is processed to form a via hole, and the via hole is plated to form the connection via 400 and the second circuit C2. When the resin layer 210 includes photosensitive resin, the via hole may be formed using a photolithography method. The connection via 400 is formed to directly contact the connection pad 300 exposed by the cavity 120.

Referring to FIG. 11(a), the second laminate 200 can be prepared by repeating the processes of FIGS. 10(c) and 10(d) described above. Here, the formed first laminate 100 and the second laminate 200 have the same form as the printed circuit board shown in FIG. 3, but can be replaced with any printed circuit board shown in FIGS. 1 to 5.

Referring to FIG. 11(b), the solder resist layer 500 is formed, and an opening is formed in the solder resist layer 500, thereby exposing the pads of the outermost layer circuits C1' C2'. The exposed pad can function as a mounting pad.

Referring to FIG. 11(c), a low melting point metal member (LM) is located on the exposed mounting pad, and the electrode terminal (T1) of the first electronic device (E1) and the second electrode terminal (T1) are connected to the low melting point metal member (LM). The electrode terminal (T2) of the electronic device (E2) may be coupled. The lower portions of the first electronic device (E1) and the second electronic device (E2) may be filled with an underfill material (F).

The first electronic device E1 is electrically connected to the first circuit C1 of the first stack 100 and is also electrically connected to the second circuit C2 of the second stack 200. Likewise, the second electronic device E2 is electrically connected to the first circuit C1 of the first stack 100 and is also electrically connected to the second circuit C2 of the second stack 200. . In particular, the bridge circuit connecting the first device mounting portion (M1) and the second device mounting portion (M2) of the second circuit (C2) connects the first electronic device (E1) and the second electronic device (E2). do.

12 and 13 are diagrams showing a method of manufacturing a package according to another embodiment of the present invention. Figures 12 and 13 show a method of manufacturing the printed circuit board shown in Figure 9.

Referring to FIGS. 12(a) and 12(b), a plurality of insulating layers 110 are stacked up and down, a first circuit C1 is formed, and a first laminate 100 is prepared. Although not shown, the first laminate 100 can be formed using a carrier. That is, after sequentially stacking a plurality of insulating layers 110 on a carrier and forming a first circuit C1 on one side of each layer, the carrier is removed to prepare the first laminate 100. Here, the b surface is the carrier attachment surface, and the first circuit (C1) on the carrier attachment surface side may be an embedded circuit. Also, here, the b-side is the opposite side of the element mounting surface.

Referring to FIG. 12(c), a cavity 120 is formed in the first laminate 100. Cavity 120 may be formed through laser processing. A portion of the first circuit C1 may be exposed by the cavity 120, and in particular, a pad of the first circuit C1 may be exposed, and the exposed pad becomes the connection pad 300. Meanwhile, a via hole (VH) is formed in the outermost insulating layer 110. A via hole (VH) can be formed through laser processing.

Referring to FIG. 12(d), the second laminate 200 is formed in the cavity 120. Refer to FIGS. 10(c) and 10(d) for a method of forming the second laminate 200. It is the same as what was explained.

Referring to FIG. 12(e), a second resin layer 220 is formed on the second laminate 200. The second resin layer 220 is also formed on the upper surface of the first laminate 100 and fills the inside of the via hole (VH).

Referring to FIG. 13(a), a via hole (VH') is formed in the second resin layer 220. A via hole (VH') of the second resin layer 220 is formed inside the via hole (VH) of the insulating layer 110, thereby exposing the pad of the first circuit (C1). Additionally, the via hole (VH') of the second resin layer 220 may expose the pad of the second outermost circuit (C2').

Referring to FIG. 13(b), a first via (V1') located in the outermost layer and a first circuit (C1') in the outermost layer are formed, and at the same time, a third via (V3) and a third circuit (C3) are formed. is formed These can all be formed by plating.

Referring to FIG. 13(c), the solder resist layer 500 is laminated on the second resin layer 220 and on the lower surface of the first laminate 100. Additionally, a metal post 600 is formed. Here, the post via 610 may be formed by forming an opening in the solder resist layer 500 and then plating the opening, and the post pad 620 may be formed by overplating the opening. The post pad 620 protrudes beyond the solder resist layer 500 and functions as a mounting pad.

Referring to FIG. 13(d), a low melting point metal member (LM) is located on the metal post 600, and the electrode terminal (T1) of the first electronic device (E1) and the low melting point metal member (LM) are connected to the low melting point metal member (LM). 2 The electrode terminal (T2) of the electronic device (E2) can be coupled. The lower portions of the first electronic device (E1) and the second electronic device (E2) may be filled with an underfill material (F).

The first electronic device E1 is electrically connected to the first circuit C1 of the first stack 100 and is also electrically connected to the second circuit C2 of the second stack 200. Likewise, the second electronic device E2 is electrically connected to the first circuit C1 of the first stack 100 and is also electrically connected to the second circuit C2 of the second stack 200. . In particular, the bridge circuit connecting the first device mounting portion (M1) and the second device mounting portion (M2) of the second circuit (C2) connects the first electronic device (E1) and the second electronic device (E2). do.

Above, an embodiment of the present invention has been described, but those skilled in the art can add, change, delete or add components without departing from the spirit of the present invention as set forth in the patent claims. The present invention may be modified and changed in various ways, and this will also be included within the scope of rights of the present invention.

100: first laminate
110: insulating layer
120: Cavity
200: second laminate
210: Resin layer
220: Second resin layer
300: Connection pad
400: Connection via
C1: first circuit
C2: second circuit
500: Solder resist layer
600: Metal post
610: Postvia
620: Post pad
M1: 1st device mounting unit
M2: Second device mounting unit

Claims (16)

In a printed circuit board having a plurality of device mounting units,
A first laminate including a plurality of insulating layers and a first circuit;
a cavity formed in the first laminate and open to an upper surface of the first laminate; and
Comprising a second laminate including a plurality of resin layers stacked in the cavity and a second circuit,
The first circuit includes a connection pad exposed by the cavity,
The second laminate includes a connection via that penetrates the resin layer located in the lowest layer and contacts the connection pad,
The resin layer located in the lowest layer among the plurality of resin layers is in contact with an insulating layer exposed to the bottom surface of the cavity among the plurality of insulating layers,
The second circuit is a printed circuit board electrically connected to a plurality of device mounting units. According to paragraph 1,
A portion of the second circuit is a printed circuit board that electrically connects the plurality of device mounting units to each other.
According to paragraph 1,
A portion of the second circuit is a printed circuit board that electrically connects one of the device mounting units and the connection via.
According to paragraph 1,
The resin layer is a printed circuit board containing a photosensitive resin.
According to paragraph 1,
A printed circuit board wherein the resin layer thickness is smaller than the insulating layer thickness.
According to paragraph 1,
A printed circuit board wherein the circuit width of the first circuit is greater than the circuit width of the second circuit.
According to paragraph 1,
The first circuit located on the uppermost layer of the first laminate is a printed circuit board embedded in the upper surface of the insulating layer located on the uppermost layer.
According to paragraph 1,
A printed circuit board in which the first circuit located on the uppermost layer of the first laminate protrudes than the insulating layer located on the uppermost layer.
According to paragraph 1,
A printed circuit board where the upper surface of the second laminate is located below the height of the upper surface of the first laminate.
According to paragraph 1,
A printed circuit board further comprising a second resin layer formed on the upper surface of the first laminate and the upper surface of the second laminate.
According to clause 10,
A via hole is formed in the insulating layer located on the uppermost layer,
A via is formed in the via hole,
The second resin layer is a printed circuit board that fills the inside of the via hole to surround the via.
According to clause 10,
A printed circuit board further comprising a solder resist layer laminated on the second resin layer.
According to clause 10,
A printed circuit board further comprising a third circuit formed on the second resin layer and electrically connected to the second circuit.
According to paragraph 1,
A printed circuit board further comprising a solder resist layer laminated on the first laminate and the second laminate.
According to clause 14,
A printed circuit board further comprising a metal post that penetrates the solder resist layer and provides the device mounting portion.
According to clause 15,
The metal post is,
Post vias penetrating the solder resist layer; and
A printed circuit board including a post pad formed on the post via to protrude beyond the solder resist layer.

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