KR102654585B1 - Display apparatus and method capable of controlling brightness of pixel - Google Patents

Abstract

A display driving device according to one aspect includes a pixel driving circuit each connected to a plurality of LEDs forming at least one row and one column and driving the LEDs in a PWM method; A control unit that determines a PWM duty ratio (PWM ON Duty) representing the light emission time period of the LED during one frame section; and a timing controller that generates a first clock signal according to the PWM duty ratio and supplies the first clock signal to the pixel driving circuit in units of rows or columns through a shift register. When the duty ratio is changed, a second clock signal matching the changed PWM duty ratio is generated, and the first clock signal or the second clock signal is selectively supplied to the pixel driving circuit.

Description

Display driving device and method capable of controlling the brightness of pixels {DISPLAY APPARATUS AND METHOD CAPABLE OF CONTROLLING BRIGHTNESS OF PIXEL}

The present invention relates to a display driving device and method capable of granular brightness control using a plurality of clock signals.

The present invention relates to a display driving device and method, and more specifically, to a display driving device and method that can flexibly control PWM ON Duty change that adjusts the light emission time of a pixel.

A typical display driving device includes a plurality of pixels, and is composed of M*N pixels arranged. Each pixel may include one or more light-emitting devices and is generally composed of three light-emitting devices (R, G, and B). Each light emitting element is called a subpixel.

Among various methods for controlling the operation of subpixels, there is a PWM control method that stores video data to control the emission of subframes during a single frame in built-in memory and controls grayscale through a PWM (Pulse Width Modulation) signal.

In the case of PWM driven pixels, image data is stored in the pixel memory for a certain period of time (pixel programming). Then, the subpixel emits light during the light emission time (On duty) within one frame according to the image data stored in the pixel memory. At this time, the brightness of the subpixel is controlled by the PWM method. A gray clock signal for PWM control is input to the driving circuit of the subpixel, as shown in FIG. 1. At this time, the number of gray clock signals (MSB, MSB-1, MSB-2, ??, LSB) is determined according to the number of bits of image data.

The erection of subpixels can be controlled by changing the emission time, and the change in emission time can be controlled by adjusting the PWM ON Duty.

However, when the emission time is changed to adjust the brightness of the subpixel, the gray clock signal changes, causing a problem in that the output signal before the change is affected by the changed gray clock signal, causing an error.

The above-mentioned background technology is technical information that the inventor possessed for deriving the present invention or acquired in the process of deriving the present invention, and cannot necessarily be said to be known art disclosed to the general public before filing the application for the present invention.

Domestic Patent Publication No. 10-2137638 (2020.07.20)

The object is to provide a display driving device and method capable of granular brightness control using a plurality of clock signals. The technical challenges to be solved are not limited to those described above, and other technical challenges may exist.

A display driving device according to one aspect includes a pixel driving circuit each connected to a plurality of LEDs forming at least one row and one column and driving the LEDs in a PWM method; A control unit that determines a PWM duty ratio (PWM ON Duty) representing the light emission time period of the LED during one frame section; and a timing controller that generates a first clock signal according to the PWM duty ratio and supplies the first clock signal to the pixel driving circuit in units of rows or columns through a shift register. When the duty ratio is changed, a second clock signal matching the changed PWM duty ratio is generated, and the first clock signal or the second clock signal is selectively supplied to the pixel driving circuit.

A display driving device according to another aspect includes a pixel driving circuit each connected to a plurality of LEDs forming at least one row and one column and driving the LEDs in a PWM method; a scan driving circuit that sequentially outputs a first signal to LEDs arranged in a first direction among the LEDs included in the pixel driving circuit; a data driving circuit that outputs a second signal to LEDs arranged in a second direction among the LEDs included in the pixel driving circuit; and a timing controller according to any one of claims 1 to 8.

A method of controlling a display driving device according to another aspect includes receiving a first clock signal corresponding to a first frame section and a second clock signal corresponding to a second frame section consecutive to the first frame section; Receiving a first selection signal; The first selection signal is transmitted to a selection signal shift register corresponding to a first row of a plurality of LEDs, the first clock signal is selected based on the first selection signal, and the first clock signal is transmitted to the first row of LEDs. A first frame driving step of transmitting a clock signal connected to a row to a shift register; sequentially performing the first frame driving step during the first frame period up to the Nth row of the plurality of LEDs; receiving a second selection signal; The second selection signal is transmitted to a selection signal shift register corresponding to the first row, the second clock signal is selected based on the second selection signal, and the second clock signal is connected to the first row. a second frame driving step of transmitting a clock signal to a shift register; And sequentially performing the second frame driving step during a second frame period up to the N-th row, wherein at least one row where the first frame driving step and the second frame driving step overlap is the It is characterized in that it is operated only by the first clock signal.

According to the present invention, the brightness of the display panel can be controlled in a more detailed manner compared to the prior art.

Additionally, according to the present invention, optimal brightness can be adjusted according to display quality or power consumption.

In addition, according to the present invention, it is possible to solve the output error of the shift register that may occur when controlling the brightness of the display panel.

The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a driving circuit diagram of a subpixel according to the prior art.
Figure 2 is a block diagram schematically showing the configuration of a display driving device according to an embodiment.
FIG. 3 is a block diagram schematically showing the configuration of a display driving device including a timing controller according to an embodiment.
Figure 4 is a block diagram schematically showing an example of a PWM clock signal output by a timing controller when a single clock is used.
Figure 5 is a timing diagram showing another example of a PWM clock signal output by a timing controller when using a single clock.
Figure 6 is a timing diagram schematically showing problems with the pulse signal output by the timing controller when using a single clock.
Figure 7 is a block diagram schematically showing the configuration of a timing controller according to an embodiment.
Figure 8 is a timing diagram illustrating an example of a timing controller selecting a CLK signal according to an embodiment.
Figure 9 is a block diagram schematically showing the configuration of a timing controller including a MUX according to an embodiment.
FIG. 10 is a timing diagram illustrating an example of a PWM clock signal output by a timing controller according to an embodiment.
FIG. 11 is a flowchart illustrating an example of a method for controlling a display driving device according to an embodiment.

The terms used in the embodiments are general terms that are currently widely used as much as possible, but may vary depending on the intention or precedent of a technician working in the art, the emergence of new technology, etc. In addition, in certain cases, there are terms arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the relevant description. Therefore, terms used in the specification should be defined based on the meaning of the term and the overall content of the specification, not just the name of the term.

When it is said that a part "includes" a certain element throughout the specification, this means that, unless specifically stated to the contrary, it does not exclude other elements but may further include other elements. In addition, terms such as “??unit” and “??module” used in the specification refer to a unit that processes at least one function or operation, which may be implemented as hardware or software, or as a combination of hardware and software. there is. Additionally, a “part” may be a hardware component, such as a processor or circuit, and/or a software component executed by the hardware component, such as a processor.

Additionally, terms including ordinal numbers, such as “first” or “second,” used in the specification may be used to describe various components, but the components should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another component.

When one element is referred to as being “connected to” another element, it includes both direct connection to the other element or intervening other elements.

Below, the embodiment will be described in detail with reference to the attached drawings. However, the embodiments may be implemented in various different forms and are not limited to the examples described herein.

Figure 2 is a block diagram schematically showing the configuration of a display driving device according to an embodiment.

Referring to FIG. 2 , the display driving device 101 according to an embodiment may include a display panel 111, a scan driving circuit 130, a data driving circuit 140, and a control unit 150. Meanwhile, the control unit 150 may include a timing controller (not shown), but is not limited thereto. For example, the display driving device 101 may include a display panel 111, a scan driving circuit 130, a data driving circuit 140, a control unit 150, and a timing controller (not shown).

The display panel 111 may include a plurality of pixels (PX). A plurality of pixels (PX) may be arranged in a matrix of m x n (m, n are natural numbers). However, the pattern in which the plurality of pixels are arranged may be arranged in various patterns depending on the embodiment, such as a zigzag pattern.

The display panel 111 includes a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital mirror device (DMD), It can be implemented as one of AMD (Actuated Mirror Device), GLV (Grating Light Valve), PDP (Plasma Display Panel), ELD (Electro Luminescent Display), VFD (Vacuum Fluorescent Display), and other types of flat panel displays or flexible displays. It can be implemented as a display. In this specification, an LED display panel will be described as an example.

Each pixel PX may include one or more light emitting elements. The light emitting device may be a light emitting diode (LED). The light emitting diode may be a micro LED with a size of 80um or less. One pixel (PX) can output various colors through a plurality of light-emitting elements with different colors. As an example, one pixel PX may include light emitting elements composed of red, green, and blue. As another example, if a white light emitting device can be further included, the white light emitting device may replace any one of the red, green, and blue light emitting devices. In an embodiment in which one pixel (PX) includes a plurality of light emitting devices, each light emitting device included in one pixel (PX) may be referred to as a 'sub pixel'.

Each subpixel can store data related to the brightness, or gradation, of the color to be output during one image frame. The size of data related to grayscale may vary, and in this specification, 10 bits will be explained as an example. However, the display driving device 101 according to the present specification is not limited to the above example.

Each pixel PX may include a pixel driving circuit that drives a light-emitting element included in the pixel, that is, a sub-pixel. The pixel driving circuit may drive a turn on or turn off operation of the subpixel by a signal output from the scan driving circuit 130 and/or the data driving circuit 140. As an example, the pixel driving circuit may include at least one transistor, at least one capacitor, etc. The pixel driving circuit may be implemented on a semiconductor wafer and connected to the light-emitting device to form a layered structure, or may be arranged and connected to the side of the light-emitting device to control light emission of the light-emitting device.

Meanwhile, the display panel 111 may include one or more scan lines (SL1 to SLm) arranged in a first direction and one or more data lines (DL1 to DLn) arranged in a second direction. Here, the first direction refers to the row direction or column direction, and the second direction refers to the column direction or row direction. As an example, the first direction may be a row direction and the second direction may be a column direction. As another example, the first direction may be a column direction and the second direction may be a row direction.

Meanwhile, the pixel (PX) may be located at the intersection of one or more scan lines (SL1 to SLm) and one or more data lines (DL1 to DLn). Each pixel (PX) may be connected to one scan line (SLk) and one data line (DLk). One or more scan lines (SL1 to SLm) may be connected to the scan driving circuit 130, and one or more data lines (DL1 to DLn) may be connected to the data driving circuit 140.

The scan driving circuit 130 may output a signal (hereinafter referred to as a first signal) that causes one or more pixels connected to one of the one or more scan lines SL1 to SLm to be driven. Preferably, the scan driving circuit 130 can sequentially select one or more scan lines (SL1 to SLm). As an example, a pixel connected to the first scan line SL1 may be driven during the first scan driving period, and a pixel connected to the second scan line SL2 may be driven during the second scan driving period.

The data driving circuit 140 may output a signal related to gradation (hereinafter referred to as a second signal) to each pixel through one or more data lines DL1 to DLn. As an example, as shown in FIG. 2, one data line is connected to one or more pixels in the longitudinal direction, but a signal related to gray level may be input only to pixels connected to the scan line selected by the scan driving circuit 130.

The control unit 150 may output a control signal to execute the operations of the scan driving circuit 130 and the data driving circuit 140. The control unit 150 may output a control signal corresponding to image data corresponding to one image frame to the scan driving circuit 130 or the data driving circuit 140. The control unit 150 may determine the PWM duty ratio (PWM ON DUTY), which represents the emission time period of the LED during one frame period. Meanwhile, the scan driving circuit 130 and the data driving circuit 140 are processors, application-specific integrated circuits (ASICs), other chipsets, logic circuits, registers, etc. known in the technical field to which the present invention belongs to execute various control logics. It may include communication modems, data processing devices, etc. Additionally, when the control logic is implemented as software, the scan driving circuit 130 and the data driving circuit 140 may be implemented as a set of program modules. At this time, the program module may be stored in a memory device and executed by a processor. As an example, the scan driving circuit 130 may include at least one shift register. Here, the shift register may correspond to any one of the plurality of shift registers 120_1, 120_2, ????, 120_k in FIG. 3. Additionally, the shift register may correspond to the timing controller 120 of FIG. 9, which will be described below.

A program is written in a computer language such as C/C++, C#, JAVA, Python, or machine language that the computer's processor (CPU) can read through the computer's device interface in order for the computer to read the program and execute the methods implemented in the program. May contain encoded code. These codes may include functional codes related to functions that define the necessary functions for executing the methods, and may include control codes related to execution procedures necessary for the computer's processor to execute the functions according to predetermined procedures. there is. In addition, these codes may further include memory reference-related codes that indicate from which location (address address) in the computer's internal or external memory additional information or media required for the computer's processor to execute functions should be referenced. Additionally, if the computer's processor needs to communicate with any other remote computer or server to execute functions, how should the code communicate with any other remote computer or server using the computer's communication module? , It may further include communication-related codes regarding what information or media should be transmitted and received during communication.

A storage medium in which a program is stored is not a medium that stores data for a short period of time, such as a register or cache memory, but a medium that stores data semi-permanently and can be read by a device. Specifically, examples of storage media include, but are not limited to, ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage devices. That is, the program can be stored in various recording media on various servers that the computer can access or in various recording media on the user's computer. Additionally, the storage medium may be distributed across networked computer systems to store computer-readable code in a distributed manner.

FIG. 3 is a block diagram schematically showing the configuration of a display driving device including a timing controller according to an embodiment.

Referring to FIG. 3, the display driving device 100 may include a display panel 110 and a plurality of shift registers 120_1, 120_2, ..., 120_k.

For convenience of explanation, a plurality of shift registers 120_1, 120_2, ????, 120_k are shown in FIG. 3, but the present invention is not limited thereto. In other words, there can be only one shift register. Preferably, there may be one shift register or as many as the number of lines in the display panel, and a PWM clock signal that controls the PWM driving section of the pixel may be supplied to each line. Hereinafter, a means for generating or supplying a PWM clock signal including a shift register or a plurality of shift registers 120_1, 120_2, ??, 120_k is defined as the timing controller 120. Additionally, the timing controller 120 may include at least one of the scan driving circuit 130 or the data driving circuit 140 of FIG. 2 .

Meanwhile, as described above, the scan driving circuit 130 of FIG. 2 may include at least one shift register. That is, the scan driving circuit 130 of FIG. 2 corresponds to a plurality of shift registers 120_1, 120_2, ????, 120_k of FIG. 3. Although the data driving circuit 140 and the control unit 150 of FIG. 2 are not shown in FIG. 3, a person skilled in the art will easily understand that the data driving circuit and control unit can be configured as shown in FIG. 2 as well in FIG. 3. . Accordingly, the display driving device 100 and the display panel 110 correspond to the display driving device 101 and the display panel 111 of FIG. 2. Hereinafter, descriptions of the display driving device 100 and the display panel 110 that overlap with those of FIG. 2 will be omitted.

As an example, the timing controller 120 may generate a first clock signal according to the PWM duty ratio and supply the first clock signal to the pixel driving circuit on a row or column basis through a shift register. Additionally, when the PWM duty ratio of the timing controller 120 is changed, a second clock signal matching the changed PWM duty ratio may be generated, and the first clock signal or the second clock signal may be selectively supplied to the pixel driving circuit. As another example, the timing controller 120 generates a first clock signal according to the PWM duty ratio, generates a PWM clock signal based on the first clock signal through a shift register, and drives the pixel driving circuit in row or column units. A PWM clock signal can be supplied. And, when the PWM duty ratio is changed, the timing controller 120 generates a second clock signal suitable for the changed PWM duty ratio, selects the first clock signal or the second clock signal, and selects the PWM clock signal based on the selected clock signal. It can generate a signal and supply a PWM clock signal to the pixel driving circuit.

The pixel line refers to an electrical connection connected so that the PWM clock signal output from the timing controller 120 is input to the pixel. Pixel lines can be connected in parallel with all pixels connected to the same row or column. As an example, when 'm' is 533, the timing controller 120 may include 533 pixel lines.

Figure 4 is a block diagram schematically showing an example of a PWM clock signal output by a timing controller when a single clock is used.

Referring to FIG. 4, you can see a timing diagram in which a PWM clock signal is sequentially output to pixel lines by a timing controller using a single clock. Specifically, the ST signal is a pulse signal for the PWM ON Duty section in which the LED emits light in relation to PWM control. The CLK signal is a signal input to multiple flip-flops or MUX in the timing controller. The PWM clock signal is a signal output to the pixel line, and is a signal in which the ST signal is output in synchronization with the period of the CLK signal.

Looking at the block diagram of the timing controller in FIG. 4, the ST signal is input to the timing controller. At this time, the ST signal is shifted by the CLK signal and sequentially output to each pixel line.

Looking at the timing diagram shown on the right side of FIG. 4, it can be seen that the ST signal is input and sequentially shifted from the first line to the Nth line by the CLK signal, and is output as a PWM clock signal to each pixel line. The characteristic of the PWM clock signal at this time is that it is output to the pixel line in the order in which the ST signal is shifted to the CLK signal. Therefore, there is a time difference determined by the CLK signal for each PWM clock signal of each line.

Figure 5 is a timing diagram showing another example of a PWM clock signal output by a timing controller when using a single clock.

The Hsync signal indicates the timing at which the signal moves for each row in the display. Referring to Figure 5, for example, assuming that the panel is simply composed of 4 ROW Lines and that the LED is driven with 100% PWM ON Duty, which represents the maximum brightness of the LED, the pulse period (1H) included in Hsync is An ST signal with a length four times that of can be generated. As an example, the CLK signal is a signal input to the MUX, and the ST signal input to the timing controller may be shifted in response to the CLK signal and output as a pixel line. As another example, the CLK signal is a signal input to a number of flip-flops in a shift register, and is formed as a pulse with the same period as the pulse period in the Hsync signal. Therefore, the ST signal input to the first flip-flop by the CLK signal can be synchronized with the pulse period of the Hsync signal and output from the next flip-flop.

Figure 6 is a timing diagram schematically showing problems with the pulse signal output by the timing controller when using a single clock.

Referring to FIG. 6, it is assumed that the PWM ON Duty is adjusted in the PWM driving time section of the first ST signal, for example, the brightness is adjusted to 75% of the PWM On Duty and the second ST signal is changed to drive the LED. You can check the problem that occurs when an 'ST' signal with a changed width is input to a timing controller that uses a single clock. Specifically, the width of the ST signal can be changed to change driving, such as the brightness of the display. At this time, if the width of the ST signal is changed, the period of the CLK signal is also changed. At this time, the changed cycle of the CLK signal can affect the entire circuit through the shift register. Therefore, at the point when the cycle of the CLK signal is changed, the pulse signal output to the Nth pixel line by the ST signal before the width of the ST signal is changed is affected by the changed CLK signal, causing an error in the output.

In summary, a timing controller using a single clock signal uses only one CLK signal, so the CLK signal changed according to the ST signal whose width has been changed affects the pulse signal caused by the existing ST signal. Accordingly, errors such as the signal blinking or turning off may occur.

Figure 7 is a block diagram schematically showing the configuration of a timing controller according to an embodiment.

Referring to FIG. 7, it can be seen that the MUX 124 is included in the configuration of the timing controller 120. In FIG. 7, the MUX 124 is shown as included in the timing controller 120, but it may be configured individually rather than included in the timing controller 120, and is not limited to this.

Meanwhile, the MUX 124 is shown as a component for selecting a clock signal, but it can be implemented by other components of the display driving device, and is not limited to this. Accordingly, the operation of the MUX 124, which will be described below, may be implemented by the timing controller 120, the scan driving circuit 130, the data driving circuit 140, the control unit 150, or more devices.

First, the MUX 124 included in the timing controller 120 can select one clock signal from among the clock signals CLK 1 signal and CLK 2 signal. Specifically, when an ST signal with a certain width is first input to the timing controller 120, each PWM clock signal is sequentially output to the pixel line according to the corresponding CLK 1 signal. And when an ST signal with a different width from the first ST signal is input to the timing controller, each PWM clock signal is sequentially output to the pixel line according to the corresponding CLK 2 signal.

Even if an ST signal with a different width is input to the shift register 121, since a clock signal different from the first ST signal is used, the CLK signal changed according to the ST signal with a changed width does not affect the pulse signal caused by the existing ST signal. It won't happen. Accordingly, by using only one CLK signal like the timing controller of FIG. 6, the problem that the CLK signal changed according to the ST signal whose width has been changed affects the pulse signal caused by the existing ST signal is solved.

Meanwhile, the MUX 124 receives a plurality of clock signals from at least one clock input terminal and selects one clock signal among them. By using the MUX (124), the CLK signal that matches the PWM On Duty ratio applied to each line can be selected, so even if the emission time is changed to adjust the brightness of the subpixel, the output signal before the change is changed as the clock signal is changed. Since it is not affected by changed clock signals, it can have the effect of preventing errors from occurring.

As an example, the MUX 124 can receive two clock signals from two clock input terminals and select one clock signal among them. Specifically, the CLK 1 signal and the CLK 2 signal are received from the clock input terminal, and the MUX 124 selects one clock signal among them.

Meanwhile, the MUX 124 may receive a plurality of clock signals from at least one clock input terminal using a switch and select one clock signal among them.

In addition, the timing controller 120 may include at least one flip-flop including an output terminal connected to the pixel driving circuit and at least one MUX 124 that selects a clock signal input to the clock terminal of the at least one flip-flop. You can. As an example, the MUX 124 may receive a plurality of clock signals from at least one clock input terminal and select one clock signal input to the clock terminal of at least one flip-flop from among the plurality of clock signals. As another example, the MUX 124 can select one clock signal input to the clock terminal of at least one flip-flop using a switch.

Figure 8 is a timing diagram illustrating an example of a timing controller selecting a CLK signal according to an embodiment.

Referring to FIG. 8, for example, if the width of the ST signal is determined to drive the LED with PWM ON Duty 100%, the period of the CLK 1 signal, which is the corresponding clock signal, is determined to match the width of the ST signal and is output through the timing controller. Each ROW line is shifted by 1H and input. Afterwards, when the width of the ST signal is changed to drive the LED by adjusting the PWM ON Duty to 75%, the clock period of the corresponding CLK signal is also adjusted and the clock signal changed to the CLK 2 signal is input through the timing controller. At this time, in order to prevent the pulse signal output to the Nth pixel line by the ST signal for driving at the previous PWM ON Duty 100% from being affected by the signal of the changed CLK 2 signal and causing an error in the output, the CLK 2 signal Even if is input, the existing CLK 1 signal is also input through the MUX, so the shift master can select and use the CLK 1 signal or CLK 2 signal appropriate for the line.

Figure 9 is a block diagram schematically showing the configuration of a timing controller including a MUX according to an embodiment.

The timing controller 120 includes a multiplexer (MUX), a selection signal shift register (SEL SHIFT), and a PWM signal shift register (PWM SHIFT). The PWM signal shift register may be a clock signal shift register. Additionally, although not shown in FIG. 9, the timing controller 120 may include a clock signal selection unit (not shown). A clock signal selection unit (not shown) outputs a selection signal (SEL signal) that selects one clock signal among a plurality of clock signals based on driving information of the pixel driving circuit.

For convenience of explanation, two MUXs 124_1 and 124_2 are shown in FIG. 9, but they can be driven by one MUX, but are not limited to this.

The SEL signal is a signal that selects one CLK signal among a plurality of CLK signals, and the timing controller 120 can receive the SEL signal or generate the SEL signal and transmit the SEL signal to the MUX through SEL SHIFT. And, the MUX (124_1, 124_2) can select one CLK signal based on the SEL signal received from SEL SHIFT and transmit it to the shift register. As an example, SEL SHIFT provides a selection signal (SEL signal) for selecting the first clock signal (CLK1 signal) or the second clock signal (CLK2 signal) based on the driving information of the pixel driving circuit on a per-pixel line basis. It can be output as . And, the MUX can output a first clock signal or a second clock signal based on the selection signal (SEL signal). The first clock signal and the second clock signal operate independently of each other with respect to the pixel driving circuit.

Referring to FIG. 9, SEL SHIFT (121_1, 121_2) refers to a shift register that shifts the SEL signal in response to the clock cycle. The clock signal selection unit (not shown) transmits a selection signal (SEL signal) for selecting the first clock signal or the second clock signal to the SEL SHIFT (121_1) based on the driving information of the pixel driving circuit. The SEL signal is a signal that selects one signal among the CLK 1 signal and the CLK 2 signal. As an example, by transmitting a signal consisting of 0 or 1 to the MUX, if the SEL signal is configured as 1, the MUX will transmit the CLK 1 signal, and if the SEL signal is configured as 0, the MUX will transmit the CLK 2 signal. can be sent. SEL SHIFT (121_1) receives the SEL signal and CLK SEL signal. The SEL signal is input to SEL SHIFT, shifted, and sequentially output for each pixel line. PWM SHIFT (122_1, 122_2) refers to a shift register that outputs output for each pixel line by shifting the ST signal in response to the clock cycle. The CLK SEL signal is a clock signal for the SEL signal. As the ST signal is shifted in PWM SHIFT (122_1, 122_2) by the CLK signal, the SEL signal is also shifted in SEL SHIFT (121_1, 121_2) by the SEL CLK signal to achieve the same Allows selection of the same CLK signal for the ST signal. MUX (124_1) receives the SEL signal from SEL SHIFT (121_1). MUX 124_1 receives the ST 1 signal and ST 2 signal, and receives the CLK 1 signal and CLK 2 signal for the ST signal (ST 1 signal and ST 2 signal). Here, the MUX (124_1) selects the CLK 1 signal and the ST 1 signal based on the received SEL signal and transmits them to the PWM SHIFT (122_1). At this time, the MUX (124_1) can use a switch to select the clock signal. As an example, the MUX 124_1 may receive a SEL signal consisting of 1 and transmit a CLK 1 signal by turning on the switch. PWM SHIFT (122_1) shifts the ST 1 signal and transmits it to the 1st Line. Likewise, MUX (124_2) receives the SEL signal and CLK SEL signal from SEL SHIFT (121_2). Here, the SEL signal received by the MUX (124_2) is a signal shifted once by the SEL SHIFT (121_1). MUX (124_2) receives the CLK 1 signal and CLK 2 signal. Then, the MUX (124_2) selects the CLK 1 signal or the CLK 2 signal according to the received SEL signal and transmits it to the PWM SHIFT (122_2). Here, the MUX (124_2) selects the CLK 1 signal according to the SEL signal and transmits it to the PWM SHIFT (122_2). PWM SHIFT (122_2) shifts the ST 1 signal based on the ST 1 signal received from PWM SHIFT (122_1) and the CLK 1 signal received from MUX (124_2) and transmits it to the 2nd Line.

While the ST 1 signal and the CLK 1 signal are transmitted for each line through the shift register, the SEL SHIFT (121_1) is a selection signal that selects the CLK 2 signal and can transmit the SEL signal to the MUX (124_1). The MUX (124_1) selects the CLK 2 signal as the clock signal and the ST 2 signal as the ST signal according to the received SEL signal and transmits them to the PWM SHIFT (122_1). PWM SHIFT (122_1) shifts the ST 2 signal and transmits it to the 1st Line. Likewise, MUX (124_2) receives the SEL signal and CLK SEL signal from SEL SHIFT (121_2). Here, the SEL signal may be a signal shifted once by SEL SHIFT (121_1). MUX (124_2) receives the CLK 1 signal and CLK 2 signal. Then, the MUX (124_2) selects the CLK 1 signal or the CLK 2 signal according to the received SEL signal and transmits it to the PWM SHIFT (122_2). Here, the MUX (124_2) selects the CLK 2 signal according to the SEL signal and transmits it to the PWM SHIFT (122_2). PWM SHIFT (122_2) shifts the ST 2 signal based on the ST 2 signal received from PWM SHIFT (122_1) and the CLK 2 signal received from MUX (124_2) and transmits it to the 2nd Line.

Since the SEL signal is shifted for each pixel line through SEL SHIFT and input to the MUX, while the ST 1 signal and CLK 1 signal are shifted for each pixel line through PWM SHIFT, the ST 2 signal and CLK 2 signal are shifted by the SEL signal. will not be affected. That is, while the ST 1 signal and the CLK 1 signal are sequentially transmitted to the Nth pixel line through the first pixel line through the shift register, the ST 2 signal and the CLK 2 signal are transmitted back to the first pixel line through the shift register. Even if transmitted through 1 pixel line, the ST 1 signal and CLK 1 signal already being transmitted are not affected by the ST 2 signal and CLK 2 signal, so no error occurs.

Therefore, by using multiple clock signals, different clock signals are applied to each changed ST signal, so the clock signal after the change does not affect the shift register being driven based on the clock signal before the change, preventing errors from occurring. .

In FIG. 9, the MUXs 124_1 and 124_2 are shown as included in the timing controller 120, but they may be configured individually rather than included in the timing controller 120, and are not limited to this. In addition, MUX (124_1, 124_2) and SEL SHIFT (121_1, 121_2) are shown as components for selecting a clock signal, but they may be implemented by other components of the display driving device, but are not limited thereto.

The operations of the clock signal selection unit (not shown), MUX (124_1, 124_2), SEL SHIFT (121_1, 121_2), and PWM SHIFT (122_1, 122_2) described above are performed using a single device (e.g., timing controller, clock signal selection unit). , MUX, SEL SHIFT, and PWM SHIFT), and may be implemented by more devices.

Additionally, the timing controller 120 may include a pulse signal input terminal (ST) and a clock input terminal (CLK).

The pulse signal input terminals (ST 1, ST 2) receive pulse signals corresponding to the time the LED emits light in relation to PWM control. Pulse signals corresponding to the brightness of the display panel are input to the pulse signal input terminals (ST 1 and ST 2). Specifically, a pulse signal with a width adjusted according to the brightness adjustment of the display panel may be input to the pulse signal input terminals (ST 1 and ST 2).

A plurality of clock signals input to the MUX (124_1, 124_2) in the timing controller 120 are input to the clock input terminals (CLK 1, CLK 2). There may be at least one clock input terminal (CLK 1, CLK 2). The clock signal input terminals (CLK 1 and CLK 2) may receive a plurality of clock signals input to the clock terminals of the MUX (124_1 and 124_2).

FIG. 10 is a timing diagram illustrating an example of a PWM clock signal output by a timing controller according to an embodiment.

Referring to Figure 10, the 'VSYNC' signal and image data recording section for synchronizing frame to frame, the LED emission section according to the PWM clock signals (PWM1, PWM 2) output by the timing controller, You can check the timing of the SEL signal for selecting the CLK signal according to the PWM On Duty ratio for each VSYNC section.

For convenience of explanation, in the first frame section, the first PWM duty ratio (PWM ON Duty) is set to correspond to PWM 1, and in the second frame section, the second PWM duty ratio is set to correspond to PWM 2, and the As an example, in the 3-frame period, the first PWM duty ratio is again set to correspond to PWM 1, and in the 4th frame period, the second PWM duty ratio is again set to correspond to PWM 2.

Therefore, PWM 1 is a PWM clock signal output by the timing controller based on the ST 1 signal and the CLK 1 signal. PWM 2 is a PWM clock signal output by the timing controller based on the ST 2 signal and the CLK 2 signal. Each of PWM 1 and PWM 2 is expressed in a trapezoid to indicate that the output is sequentially shifted by 1H from the first pixel line to the Nth pixel line in pixel line units.

In PWM 1, the SEL signal becomes high and shifts from the 1st pixel line to the Nth pixel line, thereby selecting the CLK 1 signal. In PWM 2, the SEL signal is low and synchronized with the VSYNC period and shifted from the first pixel line to the Nth pixel line, so that the CLK 2 signal can be selected. At this time, when the PWM clock signal is being output from PWM 1 to the N-th pixel line through the 1st pixel line, even if the CLK 2 signal is selected from PWM 2 to the 1st pixel line, the CLK 1 signal of the N-th pixel line is already The CLK 2 signal is not affected by the heightened SEL signal. Likewise, in PWM 2, the SEL signal is low and shifted from the first pixel line to the Nth pixel line, thereby selecting the CLK 2 signal. If the PWM clock signal is being output from PWM 2 to the N-th pixel line through the 1st pixel line, even if the CLK 1 signal is selected from PWM 1 to the 1st pixel line, the CLK 2 signal of the N-th pixel line is already The CLK 1 signal is not affected by the low SEL signal.

FIG. 11 is a flowchart illustrating an example of a method for controlling a display driving device according to an embodiment.

Referring to FIG. 11, the timing controller selectively supplies a plurality of clock signals to the pixel driving circuit. Contents that overlap with those described in FIGS. 2 to 10 regarding the timing controller's supply of clock signals to the pixel driving circuit will be omitted.

In step 1001, the timing controller receives a first clock signal corresponding to the first frame period and a second clock signal corresponding to a second frame period consecutive to the first frame period.

At step 1002, the timing controller receives a first selection signal. The first selection signal is a selection signal that selects the first clock signal.

In step 1003, the timing controller transfers the first selection signal to the selection signal shift register corresponding to the first row of the plurality of LEDs, selects the first clock signal based on the first selection signal, and sends the first clock signal to It is transmitted to the clock signal shift register connected to the first row. Step 1003 is called the first frame driving step.

In step 1004, the timing controller sequentially performs the first frame driving step during the first frame period up to the Nth row of the plurality of LEDs. The selection signal shift register transfers the first selection signal by sequentially shifting it to the Nth row, and transfers the first clock signal to the clock signal shift register based on the sequentially transferred first selection signal.

At step 1005, a second selection signal is received. The second selection signal is a selection signal that selects the second clock signal.

In step 1006, the second selection signal is transferred to the selection signal shift register corresponding to the first row, the second clock signal is selected based on the second selection signal, and the second clock signal is connected to the first row. Passed to the shift register. Step 1006 is called the second frame driving step.

In step 1007, the second frame driving step is sequentially performed during the second frame period up to the Nth row. The selection signal shift register transfers the second selection signal by sequentially shifting it to the Nth row, and transfers the second clock signal to the clock signal shift register based on the sequentially transferred second selection signal. In the row where the first frame driving step and the second frame driving step overlap, the row is characterized in that it is operated only by the first clock signal. The first frame driving step is driven based on the first selection signal, and the second frame driving step is driven based on the second selection signal. Even if the first frame driving step and the second frame driving step are driven simultaneously at overlapping times, the first frame driving step is driven based on the first selection signal, so it does not affect the second clock signal based on the second selection signal. It runs independently without receiving any information.

Those skilled in the art related to the present embodiment will understand that the above-described substrate can be implemented in a modified form without departing from the essential characteristics. Therefore, the disclosed methods should be considered from an explanatory rather than a limiting perspective, and the scope of rights is indicated in the claims, not the foregoing description, and should be interpreted to include all differences within the equivalent scope.

100, 101: display driving device
110, 111: display panel
120: Timing controller
124:MUX
130: scan driving circuit
140: data driving circuit
150: control unit

Claims (10)

a pixel driving circuit each connected to a plurality of LEDs forming at least one row and column and driving the LEDs in a PWM method;
A control unit that determines a PWM duty ratio (PWM ON Duty) representing the light emission time period of the LED during one frame section; and
Generating a first clock signal corresponding to a first frame section and a first selection signal for selecting the first clock signal, and providing the pixel driving circuit in units of rows or columns through a shift register based on the first selection signal. It includes a timing controller that supplies the first clock signal,
The timing controller is,
Generating a second clock signal corresponding to a second frame period consecutive to the first frame period and a second selection signal for selecting the second clock signal,
Depending on the frame section being driven, the first clock signal or the second clock signal is selected based on the first selection signal or the second selection signal through a MUX and supplied to the pixel driving circuit,
The pixel driving circuit is,
When receiving the second clock signal while being driven based on the first clock signal, the drive is driven by the first clock signal without being affected by the second clock signal based on the first selection signal. A display driving device. According to claim 1,
The timing controller is,
Generate a first clock signal according to the PWM duty ratio, generate a PWM clock signal based on the first clock signal through a shift register, and supply the PWM clock signal to the pixel driving circuit in row or column units. ,
When the PWM duty ratio is changed, generate a second clock signal suitable for the changed PWM duty ratio, select the first clock signal or the second clock signal, and generate a PWM clock signal based on the selected clock signal, and , A display driving device, characterized in that supplying the PWM clock signal to the pixel driving circuit. According to claim 1,
The timing controller is,
Generating a first selection signal for selecting the first clock signal and a second selection signal for selecting the second clock signal, and generating the first selection signal and the second selection signal based on the first selection signal and the second selection signal. Selectively supplying a second clock signal to the pixel driving circuit,
The first clock signal and the second clock signal are,
A display driving device, characterized in that it operates independently of each other with respect to the pixel driving circuit. According to claim 1,
The timing controller is,
At least one flip-flop including an output terminal connected to the pixel driving circuit; and
A display driving device comprising: at least one MUX that selects a clock signal input to a clock terminal of the at least one flip-flop. According to clause 4,
The timing controller is,
A pulse signal input terminal where a pulse signal corresponding to the brightness of the LED is input; and
A display driving device further comprising: at least one clock input terminal through which a plurality of clock signals are input. According to clause 5,
The MUX is,
A display driving device that receives the plurality of clock signals from the at least one clock input terminal and selects one clock signal input to a clock terminal of the at least one flip-flop from among the plurality of clock signals. According to clause 6,
The MUX is,
A display driving device that selects one clock signal input to a clock terminal of the at least one flip-flop using a switch. According to claim 1,
The timing controller is,
a clock signal selection unit outputting a selection signal for selecting a first clock signal or a second clock signal based on driving information of the pixel driving circuit; and
A display driving device comprising a MUX that outputs a first clock signal or a second clock signal based on the selection signal output from the clock signal selection unit. a pixel driving circuit each connected to a plurality of LEDs forming at least one row and column and driving the LEDs in a PWM method;
a scan driving circuit sequentially outputting a first signal to LEDs arranged in a first direction among LEDs connected to the pixel driving circuit;
a data driving circuit that outputs a second signal to LEDs arranged in a second direction among the LEDs connected to the pixel driving circuit; and
It includes the timing controller of any one of claims 1 to 8,
The pixel driving circuit is,
When receiving the second clock signal while being driven based on the first clock signal, the drive is driven by the first clock signal without being affected by the second clock signal based on the first selection signal. A display driving device. In a method of controlling a display driving device,
Receiving a first clock signal corresponding to a first frame period and a second clock signal corresponding to a second frame period consecutive to the first frame period;
Receiving a first selection signal;
The first selection signal is transmitted to a selection signal shift register corresponding to the first row of a plurality of LEDs, the first clock signal is selected based on the first selection signal through a MUX, and the first clock signal is A first frame driving step of transmitting a clock signal to a shift register connected to the first row;
sequentially performing the first frame driving step during the first frame period up to the Nth row of the plurality of LEDs;
receiving a second selection signal;
The second selection signal is transmitted to the selection signal shift register corresponding to the first row, the second clock signal is selected based on the second selection signal through the MUX, and the second clock signal is transmitted to the first row. A second frame driving step of transmitting a clock signal to a shift register connected to row 1; and
A step of sequentially performing the second frame driving step during a second frame period up to the N-th row,
At least one row where the first frame driving step and the second frame driving step overlap,
When the second clock signal is supplied while being driven based on the first clock signal, the operation is performed by the first clock signal without being affected by the second clock signal based on the first selection signal. to do, how to do.

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