KR102578715B1 - Organic light emitting diode display - Google Patents

Abstract

The present invention includes a display panel with a plurality of pixels, a gate driving circuit that drives the scan lines and emission lines of the display panel, and a data driving circuit that drives the data lines of the display panel, and the pixels include organic light emitting diodes. A compensation unit is provided to apply a compensation current to the gate electrode of the driving transistor so that the gate voltage applied to the gate electrode of the driving transistor that controls the driving current is maintained during the emission period for emitting light.

Description

Organic light emitting diode display}

The present invention relates to an organic light emitting display device.

The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, and has the advantages of fast response speed, high luminous efficiency, brightness, and viewing angle.

OLED, a self-luminous device, has the structure shown in Figure 1. OLED includes an anode electrode and a cathode electrode, and an organic compound layer (HIL, HTL, EML, ETL, EIL) formed between them. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (Electron InjecPion layer). EIL). When a driving voltage is applied to the anode and cathode electrodes, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML) to form excitons, and as a result, the emitting layer (EML) Visible light is generated.

Organic light emitting display devices have advantages such as high contrast ratio and color gamut, but for low-power operation, one frame period is lengthened from 60Hz to 1Hz, resulting in a relatively longer emission period.

As the emission period increases, the gate voltage applied to the gate terminal of the driving transistor in the conventional pixel structure gradually decreases due to leakage current. In this way, as the gate voltage applied to the gate terminal of the driving transistor gradually decreases, the driving current according to the voltage between the source and gate of the driving transistor also gradually decreases. In the conventional pixel structure, flicker was generated due to a gradually lowering driving current.

The purpose of the present invention is to provide an organic light emitting display device that can maintain a constant gate voltage applied to the gate electrode of the driving transistor by blocking leakage current leaking from the gate electrode of the driving transistor during the emission period.

In order to achieve the above object, the present invention includes a display panel having a plurality of pixels, a gate driving circuit that drives the scan lines and emission lines of the display panel, and a data driving circuit that drives the data lines of the display panel. , the pixel is provided with a compensation unit that applies a compensation current to the gate electrode of the driving transistor so that the gate voltage applied to the gate electrode of the driving transistor that controls the driving current is maintained during the emission period during which the organic light emitting diode emits light.

The compensation unit includes a fourth transistor having a drain electrode connected to the input terminal of the high-potential driving voltage, a source electrode connected to the gate electrode of the driving transistor, and a gate electrode connected to the input terminal of the ground voltage, and the compensation current is generated by the fourth transistor. It can be applied to the gate electrode of the driving transistor through a switching operation.

Among the pixels, each pixel disposed in the nth pixel row (n is a natural number) is an organic light-emitting diode (OLED) having an anode electrode connected to a second node and a cathode electrode connected to an input terminal of a low-potential driving voltage, a first A driving transistor (TFT) that controls the driving current applied to the OLED, including a gate electrode connected to the node, a source electrode connected to the second node, and a drain electrode connected to the third node, between the data line and the first node A first transistor (TFT) connected to, a second transistor (TFT) connected between the second node and the initialization input terminal, a third transistor (TFT) connected between the third node and the input terminal of the high potential driving voltage, high potential A fourth transistor (TFT) connected between the input terminal of the driving voltage and the first node, a first capacitor connected between the first node and the second node, and a second connected between the second node and the input terminal of the high potential driving voltage. Contains a capacitor.

One frame period includes an initialization period for initializing the first node, a sampling period for sampling the threshold voltage of the driving transistor (TFT) and storing it in the first node, and the source-gate gap of the driving TFT, including the sampled threshold voltage. It includes a programming period for programming the voltage and an emission period for emitting the OLED with a driving current according to the programmed source-gate voltage, and the gate electrode of the first transistor is the nth first scan to which the nth scan signal is applied. line, the gate electrode of the second transistor is connected to the n+1th first scan line to which the n+1th scan signal is applied, and the gate electrode of the third transistor is connected to the nth first scan line to which the nth emission signal is applied. It is connected to the first emission line, and the gate electrode of the fourth transistor is connected to the ground voltage line. In the initialization period, the nth scan signal and the n+1th scan signal are applied at the on level, and the nth emission signal is is applied at an off level, and in the sampling period, the nth scan signal and the nth emission signal are applied at an on level, the n+1th scan signal is applied at an off level, and in the programming period, the nth scan signal is is applied at the on level, the n+1th scan signal and the nth emission signal are applied at the off level, and in the emission period, the nth emission signal is applied at the on level, and the nth scan signal and the nth+ 1 The scan signal may be applied at an off level.

The fourth transistor may block between the first node and the input terminal of the high-potential driving voltage during the initialization period or the programming period, and may apply a compensation current to the first node during the emission period.

A reference voltage may be supplied to the first node through the first transistor during the initialization period, sampling period, and edition period, and a data voltage may be supplied to the first node through the first transistor during the programming period.

A fourth transistor (TFT) connected between the first node and the fourth node, a fifth transistor (TFT) connected between the input terminal of the compensation voltage and the fourth node, and a third connected to the fourth node and the fifth node. It includes a capacitor, and the fifth node may be connected between the data line and the first transistor (TFT).

One frame period includes an initialization period for initializing the first node, a sampling period for sampling the threshold voltage of the driving transistor (TFT) and storing it in the first node, and the source-gate gap of the driving TFT, including the sampled threshold voltage. It includes a programming period for programming the voltage and an emission period for emitting light from the OLED with a driving current according to the programmed source-gate voltage,

The gate electrode of the first transistor is connected to the nth first scan line to which the nth scan signal is applied, and the gate electrode of the second transistor and the gate electrode of the fifth transistor are connected to the n+1th scan line to which the n+1th scan signal is applied. It is connected to the first scan line, the gate electrode of the third transistor is connected to the nth first emission line to which the nth emission signal is applied, the gate electrode of the fourth transistor is connected to the ground voltage line, and initialization In the period, the nth scan signal and the n+1th scan signal are applied at the on level, and the nth emission signal is applied at the off level; In the sampling period, the nth scan signal and the nth emission signal are applied at the on level, the n+1th scan signal is applied at the off level, and in the programming period, the nth scan signal is applied at the on level, and the nth scan signal is applied at the on level. The n+1 scan signal and the nth emission signal are applied at an off level. In the emission period, the nth emission signal is applied at an on level, and the nth scan signal and the n+1th scan signal are applied at an off level. may be approved.

The fourth transistor may block between the first node and the fourth node during the initialization period or the programming period, and may apply a compensation current to the first node during the emission period.

A reference voltage may be supplied to the first node through the first transistor during the initialization period and sampling period, and a data voltage may be supplied to the first node through the first transistor during the programming period and edition period.

The present invention can maintain the gate voltage applied to the gate electrode of the driving transistor constant during the emission period by compensating for leakage current leaking from the gate electrode of the driving transistor. The gate electrode of the driving transistor of the present invention can maintain the gate voltage and thus supply a constant driving current to the OLED. As a result, OLED image quality can be improved by reducing flicker defects.

1 is a diagram showing OLED and its light-emitting principle.
Figure 2 is a diagram showing an organic light emitting display device according to an embodiment of the present invention.
3 is an equivalent circuit diagram showing one pixel structure of the present invention.
FIG. 4 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 3.
FIGS. 5A, 5B, 5C, and 5D are equivalent circuit diagrams of pixels corresponding to the initialization period, sampling period, programming period, and emission period of FIG. 4, respectively.
FIG. 6 is an equivalent circuit diagram showing one modified example of the pixel structure shown in FIG. 3.
FIG. 7 is a waveform diagram showing a data signal and a gate signal applied to the pixel of FIG. 6.
FIGS. 8A, 8B, 8C, and 8D are equivalent circuit diagrams of pixels corresponding to the initialization period, sampling period, programming period, and emission period of FIG. 7, respectively.
Figure 9 is a diagram showing the change in gate voltage applied to the first node of the present invention during the emission period.
FIG. 10 is a diagram showing a driving current that changes depending on the gate voltage applied to the first node of FIG. 9.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 2 to 10.

Referring to FIG. 2, an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 on which pixels P are formed, a data driving circuit 12 for driving data lines 14, and It is provided with a gate driving circuit 13 for driving the gate lines 15 and a timing controller 11 for controlling the driving timing of the data driving circuit 12 and the gate driving circuit 13.

In the display panel 10, a plurality of data lines 14 and a plurality of gate lines 15 intersect, and pixels P are arranged in a matrix form in each intersection area. Pixels (P) arranged on the same horizontal line form one pixel row. Pixels P arranged in one pixel row are connected to one gate line 15, and one gate line 15 includes at least one scan line 15A, 15B and at least one emission line 15C. can do. That is, each pixel P may be connected to one data line 14, at least one scan line 15A, 15B, and an emission line 15C. The pixels P may commonly receive high and low potential driving voltages (ELVDD, ELVSS), initialization voltage (Vinit), ground voltage (GND), and compensation voltage (Vcp) from a power generator (not shown). To prevent unnecessary light emission of the OLED during the initialization period and sampling period, the initialization voltage (Vinit) is preferably selected within a voltage range sufficiently lower than the operating voltage of the OLED, and can be set equal to or lower than the low potential driving voltage (ELVSS). there is.

The TFTs constituting the pixel P may be implemented as oxide TFTs including an oxide semiconductor layer. Oxide TFT is advantageous for increasing the area of the display panel 10 when considering electron mobility, process deviation, etc. However, the present invention is not limited to this, and the semiconductor layer of the TFT may be formed of amorphous silicon, polysilicon, etc.

Each pixel (P) includes a plurality of TFTs and a storage capacitor to compensate for changes in the threshold voltage of the driving TFT. The present invention supplies a compensation current to the first node during the emission period so that the driving current is maintained constant. We propose a pixel structure that can This will be described in detail later with reference to FIGS. 3 to 10.

The timing controller 11 rearranges digital video data (RGB) input from the outside to match the resolution of the display panel 10 and supplies it to the data driving circuit 12. In addition, the timing controller 11 operates the data driving circuit 12 based on timing signals such as the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the dot clock signal (DCLK), and the data enable signal (DE). A data control signal (DDC) for controlling the operation timing of and a gate control signal (GDC) for controlling the operation timing of the gate driving circuit 13 are generated.

The data driving circuit 12 converts digital video data (RGB) input from the timing controller 11 into an analog data voltage based on the data control signal (DDC).

The gate driving circuit 13 can generate a scan signal and an emission signal based on the gate control signal (GDC). Although not shown, the gate driving circuit 13 may include a scan driver and an emission driver. The scan driver may generate scan signals in a row sequential manner to drive at least one scan line connected to each pixel row and supply the scan signals to the scan lines. The emission driver may generate an emission signal in a row sequential manner to drive at least one emission line connected to each pixel row and supply the emission signal to the emission lines.

This gate driving circuit 13 can be formed directly on the non-display area of the display panel 10 according to the GIP (GaPe-driver In Panel) method.

The compensation unit 16 is a gate electrode of the driving transistor (DT) so that the gate voltage applied to the gate electrode of the driving transistor (DT), which controls the driving current, is kept constant within the error range during the emission period during which the OLED emits light. Apply compensation current to. The compensation unit 16 includes a drain electrode connected to the input terminal of the high potential driving voltage (EVDD), a source electrode connected to the gate electrode of the driving transistor (DT), and a gate electrode connected to the input terminal of the ground voltage (GND). . This compensation unit 16 is provided with a fourth transistor (ST4) that applies a compensation current that compensates for leakage current leaking from the gate electrode of the driving transistor (DT) to the gate electrode of the driving transistor (DT). In this way, the present invention compensates for the leakage current leaking from the gate electrode of the driving transistor through the compensation unit, thereby preventing the gate voltage applied to the gate electrode of the driving transistor from being lowered during the emission period, thereby providing a constant driving current to the OLED. can be supplied.

Figure 3 is an equivalent circuit diagram showing one pixel structure of the present invention. FIG. 4 is a waveform diagram showing the data signal and gate signal applied to the pixel of FIG. 3. 5A to 5D show equivalent circuits of pixels for an initialization period, a sampling period, a programming period, and an emission period, respectively.

Referring to FIGS. 3 and 5D, each pixel (P) includes an OLED, a driving TFT (DT), first to fourth transistors (ST1 to ST4, hereinafter described as TFT), and first and second capacitors ( Cst1, Cst2). This pixel (P) has a 5T2C circuit structure including five NMOS type transistors and two capacitors.

One frame period of a pixel (P) is divided into an initialization period (Ti), a sampling period (Ts), a programming period (Tp), and an emission period (Te).

The first scan signal (SCAN1) is generated at an ON level during the initialization period (Ti), the sampling period (Ts), and the programming period (Tp) to turn on the first TFT (ST1). and is inverted to the OFF level in the emission period Te to turn off the first TFT (ST1).

The second scan signal (SCAN2) is generated at an ON level within the initialization period (Ti) to turn on the second TFT (ST2), and remains at an OFF level for the remaining period. Thus, the second TFT (ST2) is controlled to be in an off state.

The emission signal (EM) is generated at an ON level within the sampling period (Ts) to turn on the third TFT (ST3), and the initialization period (Ti) and programming period (Tp) is inverted to the OFF level to turn off the third TFT (ST3). Additionally, the emission signal EM maintains the ON level during the emission period Te to maintain the third TFT ST3 in the on state.

OLED emits light by driving current supplied from the driving TFT (DT). It includes an organic compound layer provided between the anode and cathode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). It may include, but is not limited to. The anode of the OLED is connected to the second node (N2), and the cathode is connected to the low-potential power supply voltage (EVSS).

The first TFT (ST1) is switched in response to the first scan signal (SCAN1) to turn on/off the current path between the data line 14 and the first node (N1). The gate electrode of the first TFT (ST1) is connected to the first scan line 15A, and the drain electrode is connected to the data line 14. The source electrode of the first TFT (ST1) is connected to the first node (N1).

The second TFT (ST2) is switched in response to the second scan signal (SCAN2) to turn on/off the current path between the input terminal of the initialization voltage (Vini) and the second node (N2). The gate electrode of the second TFT (ST2) is connected to the second scan line 15B, and the drain electrode is connected to the second node (N2). The source electrode of the second TFT (ST2) is connected to the input terminal of the initialization voltage (Vini).

The third TFT (ST3) is switched in response to the emission signal (EM), thereby turning on/off the current path between the input terminal of the high-potential power supply voltage (EVDD) and the third node (N3). . The third node N3 is connected between the input terminal of the high potential power supply voltage EVDD and the drain electrode of the driving TFT DT.

The gate electrode of the third TFT (ST3) is connected to the emission line 15C, and the drain electrode is connected to the input terminal of the high potential power supply voltage (EVDD). The source electrode of the third TFT (ST3) is connected to the third node (N3).

The driving TFT (DT) is a driving element that controls the driving current flowing through the OLED according to the voltage between its gate and source. The gate electrode of the driving TFT (DT) is connected to the first node (N1), and the drain electrode is connected to the third node (N3). The source electrode of the driving TFT (DT) is connected to the anode of the OLED through the second node (N2).

The fourth TFT (ST4) switches in response to the ground voltage (GND), thereby turning on/off the current path between the input terminal of the high-potential power supply voltage (EVDD) and the gate electrode of the driving TFT (DT). do. The gate electrode of the fourth TFT (ST4) is connected to the input terminal of the ground voltage (GND), and the drain electrode is connected to the input terminal of the high potential power supply voltage (EVDD). The source electrode of the fourth TFT (ST4) is connected to the first node (N1).

The first capacitor Cst1 is connected between the first node N1 and the second node N2 and stores the voltage difference between the two ends. The first capacitor (Cst1) samples the threshold voltage (Vth) of the driving TFT (DT) in a source-follower method.

The second capacitor Cst2 is connected between the input terminal of the high potential power supply voltage EVDD and the second node N2. When the potential of the first node (N1) changes according to the data voltage (Vdata) in the programming period (Tp), the first and second capacitors (Cst1, Cst2) distribute the change as a voltage to the second node (N2) It is reflected in

The operation of these pixels (P) is explained as follows.

Referring to FIG. 5A, during the initialization period Ti, the first and second TFTs (ST1, ST2) turn on in response to the first and second scan signals (SCAN1, SCAN2) at the ON level. on). The third TFT (ST3) is turned off in the initialization period (Ti) by the emission signal (EM) at the OFF level. The fourth TFT (ST4) is turned off in the initialization period (Ti) by the ground voltage (GND). During the initialization period Ti, a predetermined reference voltage Vref is supplied to the data line 14. During the initialization period Ti, the voltage of the first node N1 is initialized to the reference voltage Vref, and the voltage of the second node N2 is initialized to a predetermined initialization voltage Vini.

Referring to FIG. 5B, the third TFT (ST3) is turned on in response to the emission signal (EM) at the ON level during the sampling period (Ts). During the sampling period (Ts), the first TFT (ST1) is maintained in the ON state by the first scan signal (SCAN1) at the ON level, while the second TFT (ST2) is at the OFF level. It is turned off by the second scan signal SCAN2. The fourth TFT (ST4) continues to be in an OFF state by the ground voltage (GND). During the sampling period Ts, the reference voltage Vref is supplied to the data line 14. During the sampling period (Ts), the potential of the first node (N1) is maintained at the reference voltage (Vref), while the potential of the second node (N2) is connected to the drain-source current (Ids) of the driving TFT (DT). rises by According to this source-follower method, the gate-source voltage (Vgs) of the driving TFT (DT) is sampled as the threshold voltage (Vth) of the driving TFT (DT), and this sampled threshold voltage (Vth) is It is stored in the first capacitor (Cst1). During the sampling period Ts, the voltage of the first node N1 is “Vref” and the voltage of the second node N1 is “Vref-Vth”.

Referring to FIG. 5C, during the programming period (Tp), the first TFT (ST1) maintains an ON state according to the first scan signal (SCAN1) at the ON level, and the second and third TFTs (ST2, ST3) and the driving TFT (DT) are turned off. The fourth TFT (ST4) continues to be in an OFF state by the ground voltage (GND). The data voltage (Vdata) of the input image is supplied to the data line 14 during the programming period (Tp). The data voltage (Vdata) is applied to the first node (N1), and the voltage distribution result between the first and second capacitors (Cst1, Cst2) with respect to the potential change (Vdata-Vref) of the first node (N1) is the first node (N1). 2 The voltage (Vgs) between the gate and source of the driving TFT (DT) is programmed by being reflected in the node (N2).

During the programming period (Tp), the voltage of the first node (N1) is the data voltage (Vdata), and the voltage of the second node (N2) is the first and second nodes at “Vref-Vth” set through the sampling period (Ts). The voltage distribution result (C'*(Vdata-Vref)) between the 2 capacitors (Cst1, Cst2) is added to become "Vref-Vth+C'*(Vdata-Vref)". Ultimately, the voltage (Vgs) between the gate and source of the driving TFT (DT) is programmed as “Vdata-Vref+Vth-C'*(Vdata-Vref)” through the programming period (Tp). Here, C' is CST1/(CST1+CST2), where CST1 means the first capacitance of the first capacitor (Cst1), and CST2 means the second capacitance of the second capacitor (Cst2).

Referring to FIG. 5D, the emission period (Te) continues from the programming period (Tp) until the initialization period (Ti) of the next frame. The emission signal (EM) is input at an ON level to turn on the third TFT (ST3). The fourth TFT (ST4) continues to be in an OFF state by the ground voltage (GND). In the emission period (Te), a driving current (Ioled) is applied to the OLED according to the gate-source voltage (Vgs) programmed through the programming period (Tp) to cause the OLED to emit light. During the emission period Te, the first and second scan signals SCAN1 and SCAN2 are input at an OFF level to turn off the first and second TFTs ST1 and ST2. While the first TFT (ST1) is turned off, it is desirable to maintain the potential of the first node (N1) at the reference voltage (Vref). However, as the emission period (Te) becomes longer, the first TFT (ST1) The leakage current leaking through ST1) increases, lowering the reference voltage (Vref). In this way, while the leakage current leaks through the first TFT (ST1), the compensation current is supplied to the fourth TFT (ST4) by the potential difference between the input terminal of the high potential power supply voltage (EVDD) and the first node (N1). ) is applied to the first node (N1).

A compensation current is applied to the first node N1 through the fourth TFT (ST4) in proportion to the leakage current leaking through the first TFT (ST1) to compensate. The potential of the first node N1 can maintain the reference voltage Vref within an error range even if the emission period Te is prolonged. Accordingly, it is possible to prevent the driving current (Ioled) flowing through the OLED from being lowered during the emission period (Te).

The driving current (Ioled) that constantly flows through the OLED during the emission period (Te) is given in Equation 1. OLED emits light using this current to express the brightness of the input image.

In Equation 1, k indicates a proportionality constant determined by the electron mobility of the driving TFT (DT), parasitic capacitance, and channel capacity.

The driving current (Ioled) relation is k/2(Vgs-Vth)2. Since Vgs programmed through the programming period (Tp) includes Vth, the Vth component in the driving current (Ioled) relation is as shown in Equation 1. It is erased. Accordingly, the influence of changes in threshold voltage (Vth) on driving current (Ioled) is eliminated.

FIG. 6 is an equivalent circuit diagram showing one modified example of the pixel structure shown in FIG. 3. FIG. 7 is a waveform diagram showing the data signal and gate signal applied to the pixel of FIG. 6. FIGS. 8A, 8B, 8C, and 8D are equivalent circuit diagrams of pixels corresponding to the initialization period, sampling period, programming period, and emission period of FIG. 7, respectively.

Referring to FIGS. 6 and 8D, each pixel (P) includes an OLED, a driving TFT (DT), first to fifth TFTs (ST1 to ST4), and first to third capacitors (Cst1, Cst2, Ccp). do. This pixel (P) has a 6T3C circuit structure including 6 transistors and 3 capacitors of NMOS type.

The compensation unit 16 is a gate electrode of the driving transistor (DT) so that the gate voltage applied to the gate electrode of the driving transistor (DT), which controls the driving current, is kept constant within the error range during the emission period during which the OLED emits light. Apply compensation current to. The compensation unit 16 includes a fourth transistor (ST4) connected between the first node (N1) and the fourth node (N4), and a fourth transistor (ST4) connected between the input terminal of the compensation voltage (Vcp) and the fourth node (N4). 5 It includes a transistor (ST5) and a third capacitor (Ccp) connected to the fourth node (N4) and the fifth node (N5). The present invention compensates for the leakage current leaking from the gate electrode of the driving transistor (DT) through the compensation unit 16, thereby preventing the gate voltage applied to the gate electrode of the driving transistor (DT) from being lowered during the emission period. By preventing this, a constant driving current can be supplied to the OLED.

One frame period of a pixel (P) is divided into an initialization period (Ti), a sampling period (Ts), a programming period (Tp), and an emission period (Te).

The first scan signal (SCAN1) is generated at an ON level during the initialization period (Ti), the sampling period (Ts), and the programming period (Tp) to turn on the first TFT (ST1). and is inverted to the OFF level in the emission period Te to turn off the first TFT (ST1).

The second scan signal (SCAN2) is generated at the ON level within the initialization period (Ti) to turn on the second TFT (ST2) and the fifth TFT (ST5), and during the remaining period. By maintaining the OFF level, the second TFT (ST2) and the fifth TFT (ST5) are controlled to be in an off state.

The emission signal (EM) is generated at an ON level within the sampling period (Ts) to turn on the third TFT (ST3), and the initialization period (Ti) and programming period (Tp) is inverted to the OFF level to turn off the third TFT (ST3). Additionally, the emission signal EM maintains the ON level during the emission period Te to maintain the third TFT ST3 in the on state.

OLED emits light by driving current supplied from the driving TFT (DT). It includes an organic compound layer provided between the anode and cathode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). It may include, but is not limited to. The anode of the OLED is connected to the second node (N2), and the cathode is connected to the low-potential power supply voltage (EVSS).

The first TFT (ST1) is switched in response to the first scan signal (SCAN1) to turn on/off the current path between the data line 14 and the first node (N1). The gate electrode of the first TFT (ST1) is connected to the first scan line 15A, and the drain electrode is connected to the fourth node (N4). The source electrode of the first TFT (ST1) is connected to the first node (N1). The fourth node N4 is connected to the data line 14.

The second TFT (ST2) is switched in response to the second scan signal (SCAN2) to turn on/off the current path between the input terminal of the initialization voltage (Vini) and the second node (N2). The gate electrode of the second TFT (ST2) is connected to the second scan line 15B, and the drain electrode is connected to the second node (N2). The source electrode of the second TFT (ST2) is connected to the input terminal of the initialization voltage (Vini).

The third TFT (ST3) is switched in response to the emission signal (EM), thereby turning on/off the current path between the input terminal of the high potential power supply voltage (EVDD) and the drain electrode of the driving TFT (DT). )do. The gate electrode of the third TFT (ST3) is connected to the emission line 15C, and the drain electrode is connected to the input terminal of the high potential power supply voltage (EVDD). The source electrode of the third TFT (ST3) is connected to the drain electrode of the driving TFT (DT).

The driving TFT (DT) is a driving element that controls the driving current flowing through the OLED according to the voltage between its gate and source. The gate electrode of the driving TFT (DT) is connected to the first node (N1), and the drain electrode is connected to the source electrode of the third TFT (ST3). The source electrode of the driving TFT (DT) is connected to the anode of the OLED through the second node (N2).

The fourth TFT (ST4) switches in response to the ground voltage (GND), thereby turning on/off the current path between the input terminal of the high-potential power supply voltage (EVDD) and the gate electrode of the driving TFT (DT). do. The gate electrode of the fourth TFT (ST4) is connected to the input terminal of the ground voltage (GND), and the drain electrode is connected to the third node (N3). The source electrode of the fourth TFT (ST4) is connected to the first node (N1).

The fifth TFT (ST5) is switched in response to the second scan signal (SCAN2) to turn on/off the current path between the input terminal of the compensation voltage (Vcp) and the third node (N3). The gate electrode of the fifth TFT (ST2) is connected to the second scan line 15B, and the drain electrode is connected to the input terminal of the compensation voltage (Vcp). The source electrode of the fifth TFT (ST5) is connected to the second node (N2).

The first capacitor Cst1 is connected between the first node N1 and the second node N2 and stores the voltage difference between the two ends. The first capacitor (Cst1) samples the threshold voltage (Vth) of the driving TFT (DT) in a source-follower method.

The second capacitor Cst2 is connected between the input terminal of the high potential power supply voltage EVDD and the second node N2. When the potential of the first node (N1) changes according to the data voltage (Vdata) in the programming period (Tp), the first and second capacitors (Cst1, Cst2) distribute the change as a voltage to the second node (N2) It is reflected in

The third capacitor Ccp is connected between the third node N3 and the fourth node N4 and stores the voltage difference between both ends.

The operation of these pixels (P) is explained as follows.

Referring to FIG. 8A, during the initialization period Ti, the first TFT (ST1), the second TFT (ST2), and the fifth TFT (ST5) transmit the first and second scan signals (SCAN1, SCAN2) at the ON level. ) is turned on in response. The third TFT (ST3) is turned off in the initialization period (Ti) by the emission signal (EM) at the OFF level. The fourth TFT (ST4) is turned off in the initialization period (Ti) by the ground voltage (GND). During the initialization period Ti, a predetermined reference voltage Vref is supplied to the data line 14. During the initialization period Ti, the voltage of the first node N1 is initialized to the reference voltage Vref, and the voltage of the second node N2 is initialized to a predetermined initialization voltage Vini.

Additionally, during the initialization period Ti, a compensation voltage Vcp is supplied to the third node. The compensation voltage (Vcp) is stored in the third capacitor (Ccp).

Referring to FIG. 8B, the third TFT (ST3) is turned on in response to the emission signal (EM) at the ON level during the sampling period (Ts). During the sampling period (Ts), the first TFT (ST1) is maintained in the ON state by the first scan signal (SCAN1) at the ON level, while the second TFT (ST2) and the fifth TFT (ST5) are maintained in the ON state. ) is turned off by the second scan signal SCAN2 at the OFF level. The fourth TFT (ST4) continues to be in an OFF state by the ground voltage (GND). During the sampling period Ts, the reference voltage Vref is supplied to the data line 14. During the sampling period (Ts), the potential of the first node (N1) is maintained as the reference voltage (Vref), and the potential of the third node (N3) is maintained as the compensation voltage (Vcp), while the potential of the second node (N2) is maintained as the compensation voltage (Vcp). The potential of increases due to the drain-source current (Ids) of the driving TFT (DT). According to this source-follower method, the gate-source voltage (Vgs) of the driving TFT (DT) is sampled as the threshold voltage (Vth) of the driving TFT (DT), and this sampled threshold voltage (Vth) is It is stored in the first capacitor (Cst1). During the sampling period Ts, the voltage of the first node N1 is “Vref” and the voltage of the second node N1 is “Vref-Vth”.

Referring to FIG. 8C, during the programming period (Tp), the first TFT (ST1) maintains an ON state according to the first scan signal (SCAN1) at the ON level, and the second TFT (ST2) and the third TFT (ST2) The TFT (ST3), the fifth TFT (ST5), and the driving TFT (DT) are turned off. The fourth TFT (ST4) continues to be in an OFF state by the ground voltage (GND). The data voltage (Vdata) of the input image is supplied to the data line 14 during the programming period (Tp). When the data voltage Vdata is applied to the fourth node N4, the reference voltage Vref applied to the fourth node N4 increases to the data voltage Vdata. The result of the voltage increase between the third capacitors (Ccp) in relation to the potential change (Vdata-Vref) of the fourth node (N1) is reflected in the third node (N3), so that the compensation voltage applied to the third node (N3) ( Vcp) increases by the potential change (Vdata-Vref) of the fourth node (N1).

The data voltage (Vdata) is applied to the first node (N1) via the fourth node (N4), and the first and second capacitors (Cst1, Cst2) for the potential change (Vdata-Vref) of the first node (N1) ) is reflected in the second node (N2), thereby programming the gate-source voltage (Vgs) of the driving TFT (DT).

During the programming period (Tp), the voltage of the first node (N1) is the data voltage (Vdata), and the voltage of the second node (N2) is the first and second nodes at “Vref-Vth” set through the sampling period (Ts). The voltage distribution result (C'*(Vdata-Vref)) between the 2 capacitors (Cst1, Cst2) is added to become "Vref-Vth+C'*(Vdata-Vref)". Ultimately, the voltage (Vgs) between the gate and source of the driving TFT (DT) is programmed as “Vdata-Vref+Vth-C'*(Vdata-Vref)” through the programming period (Tp). Here, C' is CST1/(CST1+CST2), where CST1 means the first capacitance of the first capacitor (Cst1), and CST2 means the second capacitance of the second capacitor (Cst2).

In addition, the voltage of the fourth node N4 is the data voltage Vdata, and the voltage of the third node N2 is the storage value stored in the third capacitor Ccp at "Vcp" set through the sampling period Ts ( Ccp/(Ccp+Cpar)) is added to become “Vcp+(Ccp/(Ccp+Cpar))*(Vdata-Vref)”. Here, Ccp means the third capacitance of the third capacitor (Ccp).

Referring to FIG. 8D, the emission period (Te) continues from the programming period (Tp) until the initialization period (Ti) of the next frame. The emission signal (EM) is input at an ON level to turn on the third TFT (ST3). The fourth TFT (ST4) continues to be in an OFF state by the ground voltage (GND). In the emission period (Te), a driving current (Ioled) is applied to the OLED according to the gate-source voltage (Vgs) programmed through the programming period (Tp) to cause the OLED to emit light. During the emission period (Te), the first and second scan signals (SCAN1, SCAN2) are input at an OFF level to activate the first TFT (ST1), the second TFT (ST2), and the fifth TFT (ST5). Turn it off. While the first TFT (ST1) is turned off, it is desirable to maintain the potential of the first node (N1) at the data voltage (Vdata). However, as the emission period (Te) becomes longer, the first TFT ( The leakage current leaking through ST1) increases and the data voltage (Vdata) decreases. In this way, while the leakage current leaks through the first TFT (ST1), the compensation current is supplied to the fourth TFT (ST4) by the potential difference between the input terminal of the high potential power supply voltage (EVDD) and the first node (N1). ) is applied to the first node (N1). At this time, the data voltage (Vdata) is maintained at the fourth node (N4). By maintaining the data voltage Vdata at the fourth node N4, the potential of the third node N3 is prevented from being lower than the potential of the first node N1. Accordingly, it is possible to prevent the voltage applied to the first node (N1) from flowing to the third node (N3).

A compensation current is applied to the first node N1 through the fourth TFT (ST4) in proportion to the leakage current leaking through the first TFT (ST1) to compensate. The potential of the first node N1 can maintain the data voltage Vdata within an error range even if the emission period Te is prolonged. Accordingly, it is possible to prevent the driving current (Ioled) flowing through the OLED from being lowered during the emission period (Te).

The driving current (Ioled) that constantly flows through the OLED during the emission period (Te) is given in Equation 2. OLED emits light using this current to express the brightness of the input image.

In Equation 2, k indicates a proportionality constant determined by the electron mobility of the driving TFT (DT), parasitic capacitance, and channel capacity.

The driving current (Ioled) relation is k/2(Vgs-Vth)2. Since Vgs programmed through the programming period (Tp) includes Vth, the Vth component in the driving current (Ioled) relation is as shown in Equation 1. It is erased. Accordingly, the influence of changes in threshold voltage (Vth) on driving current (Ioled) is eliminated.

Figure 9 shows the change in gate voltage applied to the first node of the present invention during the emission period, and Figure 10 shows the driving current changed according to the gate voltage applied to the first node of Figure 9.

Referring to FIG. 9, the vertical direction represents the voltage applied to the first node, and the horizontal direction represents the emission period. Referring to FIG. 10, the vertical direction represents the current applied to the OLED, and the horizontal direction represents the emission period.

In a conventional pixel structure, as the emission period becomes longer, the voltage applied to the first node gradually decreases, making the driving current flowing through the driving TFT unstable. As a result, the brightness of the OLED that emits light when supplied with driving current was expressed differently, resulting in a flicker phenomenon.

On the other hand, as described above, the pixel structure of the present invention can input a compensation current to the first node equal to the leakage current leaking from the first node. Accordingly, in the pixel structure of the present invention, even if the emission period is prolonged, the leakage current leaking from the first node is compensated through compensation current, so that a stable voltage can be applied to the gate electrode of the driving TFT. In other words, it is possible to prevent a stable voltage from dropping on the gate electrode of the driving TFT.

In this way, by applying a stable voltage to the gate electrode of the driving TFT, the driving current flowing through the driving TFT can also flow stably. Accordingly, the OLED can express constant brightness of the OLED by receiving a stable supply of driving current and emitting light.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data lines 15: gate lines
15A: 1st scan line 15B: 2nd scan line
15C: Emission line

Claims (10)

A display panel equipped with a plurality of pixels;
a gate driving circuit that drives scan lines and emission lines of the display panel; and
It includes a data driving circuit that drives data lines of the display panel;
The pixel is,
A compensation unit for applying a compensation current to the gate electrode of the driving transistor so that the gate voltage applied to the gate electrode of the driving transistor that controls the driving current is maintained during the emission period during which the organic light emitting diode emits light,
Among the pixels, each pixel placed in the nth pixel row (n is a natural number) is,
the organic light emitting diode having an anode electrode connected to a second node and a cathode electrode connected to an input terminal of a low potential driving voltage;
the driving transistor including a gate electrode connected to a first node, a source electrode connected to the second node, and a drain electrode connected to a third node;
a first transistor connected between the data line and the first node;
a second transistor connected between the second node and an initialization input terminal;
a third transistor connected between the third node and an input terminal of a high potential driving voltage; and
It includes a fourth transistor connected between the input terminal of the high potential driving voltage and the first node, and the compensation unit
It includes the fourth transistor having a drain electrode connected to the input terminal of the high potential driving voltage, a source electrode connected to the gate electrode of the driving transistor, and a gate electrode connected to the input terminal of the ground voltage,
The compensation current is applied to the gate electrode of the driving transistor by a switching operation of the fourth transistor.

delete According to claim 1,
Among the pixels, each pixel placed in the nth pixel row (n is a natural number) is,
a first capacitor connected between the first node and the second node; and
The organic light emitting display device further includes a second capacitor connected between the second node and an input terminal of the high potential driving voltage.
According to claim 1,
One frame period is:
An initialization period for initializing the first node, a sampling period for sampling the threshold voltage of the driving transistor and storing it in the first node, and programming the source-gate voltage of the driving transistor including the sampled threshold voltage. a programming period, and an emission period for emitting light from the OLED with a driving current according to the programmed source-gate voltage,
The gate electrode of the first transistor is connected to the n-th first scan line to which the n-th scan signal is applied, and the gate electrode of the second transistor is connected to the n+1-th first scan line to which the n+1-th scan signal is applied. is connected to, the gate electrode of the third transistor is connected to the n-th first emission line to which the n-th emission signal is applied, the gate electrode of the fourth transistor is connected to the ground voltage line,
In the initialization period, the nth scan signal and the n+1th scan signal are applied at an on level, and the nth emission signal is applied at an off level;
In the sampling period, the nth scan signal and the nth emission signal are applied at an on level, and the n+1th scan signal is applied at an off level;
In the programming period, the nth scan signal is applied at an on level, and the n+1th scan signal and the nth emission signal are applied at an off level;
In the emission period, the nth emission signal is applied at an on level, and the nth scan signal and the n+1th scan signal are applied at an off level.
According to clause 4,
The fourth transistor is
Blocking between the first node and the input terminal of the high potential driving voltage during the initialization period to the programming period,
An organic light emitting display device that applies the compensation current to the first node during the emission period.
According to clause 4,
A reference voltage is supplied to the first node through the first transistor during the initialization period, the sampling period, and the emission period,
An organic light emitting display device in which a data voltage is supplied to the first node through the first transistor during the programming period.
A display panel equipped with a plurality of pixels;
a gate driving circuit that drives scan lines and emission lines of the display panel; and
It includes a data driving circuit that drives data lines of the display panel;
The pixel is,
A compensation unit for applying a compensation current to the gate electrode of the driving transistor so that the gate voltage applied to the gate electrode of the driving transistor that controls the driving current is maintained during the emission period during which the organic light emitting diode emits light,
Among the pixels, each pixel placed in the nth pixel row (n is a natural number) is,
the organic light emitting diode having an anode electrode connected to a second node and a cathode electrode connected to an input terminal of a low potential driving voltage;
the driving transistor including a gate electrode connected to a first node, a source electrode connected to the second node, and a drain electrode connected to a third node;
a first transistor connected between the data line and the first node;
a second transistor connected between the second node and an initialization input terminal; and
It includes a third transistor connected between the third node and an input terminal of a high potential driving voltage,
The compensation department
a fourth transistor connected between the first node and the fourth node;
a fifth transistor connected between the input terminal of the compensation voltage and the fourth node; and
An organic light emitting display device comprising: a third capacitor connected to the fourth node and the fifth node.
According to clause 7,
One frame period is:
An initialization period for initializing the first node, a sampling period for sampling the threshold voltage of the driving transistor and storing it in the first node, and programming the source-gate voltage of the driving transistor including the sampled threshold voltage. It includes a programming period and an emission period for emitting light from the OLED with a driving current according to the programmed source-gate voltage,
The gate electrode of the first transistor is connected to the n-th first scan line to which the n-th scan signal is applied, and the gate electrode of the second transistor and the gate electrode of the fifth transistor are connected to the n-th first scan line to which the n-th scan signal is applied. It is connected to the n+1th first scan line, the gate electrode of the third transistor is connected to the nth first emission line to which the nth emission signal is applied, and the gate electrode of the fourth transistor is connected to the ground voltage line. is connected to,
In the initialization period, the nth scan signal and the n+1th scan signal are applied at an on level, and the nth emission signal is applied at an off level;
In the sampling period, the nth scan signal and the nth emission signal are applied at an on level, and the n+1th scan signal is applied at an off level;
In the programming period, the nth scan signal is applied at an on level, and the n+1th scan signal and the nth emission signal are applied at an off level;
In the emission period, the nth emission signal is applied at an on level, and the nth scan signal and the n+1th scan signal are applied at an off level.
According to clause 8,
The fourth transistor is
Blocking between the first node and the fourth node during the initialization period to the programming period,
An organic light emitting display device that applies a compensation current to the first node during the emission period.
According to clause 8,
A reference voltage is supplied to the first node through the first transistor during the initialization period and the sampling period,
An organic light emitting display device in which a data voltage is supplied to the first node through the first transistor during the programming period and the emission period.

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