KR102533579B1 - Apparatus for correcting voltage gain of a comparator for noise shaping SAR ADC - Google Patents

Abstract

The present invention relates to an apparatus for correcting comparator voltage gain of an NS SAR ADC, for correcting the comparator voltage gain of an NS SAR ADC applied to various sensors such as temperature and pressure mainly used in smart devices so that the NTF is within a stable range. will be.
To this end, the present invention provides a CDAC for outputting an analog voltage according to a CDAC control code of a predetermined value or a CDAC inversion code input after charge sharing of an integrator to be corrected in an nth integrator; Generate residual voltage with the output of CDAC, sample residual voltage by charge-sharing the residual voltage sample capacitor with CDAC, and charge-share the residual voltage sample capacitor, 1st integrating capacitor, and 2nd integrating capacitor to obtain the 1st integral voltage and 2nd integral voltage an n-order integrator that generates an inverted residual voltage that is opposite to the residual voltage after generating each voltage; Residual voltage and inverted residual voltage generated by the n-order integrator are sequentially provided as inputs, and the 1st and 2nd integral voltages are received as the 1st and 2nd integrator inputs, respectively, and compared to change the output (n+ 1) -path comparator; and (n+1)-path comparator by sequentially adjusting and providing a 4-bit comparator voltage gain correction code, checking the output of the (n+1)-path comparator to determine the 4-bit comparator voltage at the time the output of the comparator changes. and a gain controller for correcting the voltage gain of the (n+1)-path comparator with a gain correction code value.

Description

Apparatus for correcting voltage gain of a comparator for noise shaping SAR ADC}

The present invention relates to a comparator voltage gain correction device of a Noise Shaping Successive Approximation Register Analog-Digital Converter (hereinafter abbreviated as 'NS SAR ADC'), and more particularly, to a smart Comparator voltage gain compensator of NS SAR ADC that maintains NTF (noise transform function) of NS SAR ADC applied to various sensors such as temperature and pressure, which are mainly used in devices, at a specific value or always stably. It is about.

Recently, as various systems used in daily life are implemented as digital electronic devices, analog-to-digital converters (ADCs) convert many analog signals that exist in nature into digital signals to be supplied to digital systems. ') is required.

Such an ADC uses a delta-sigma structure in the case of a sample rate of several tens of kHz and high resolution, and uses a sequential approximation (SAR) structure in the case of a sample rate of several tens of kHz to several tens of MHz.

However, the delta-sigma structure has the disadvantage of increasing static power consumption because the integrator is made using an amplifier, and the sequential approximation structure has limitations in increasing the resolution due to capacitor mismatch and resolution of the comparator. A noise-modified sequential approximation (NS SAR) structure with high power efficiency and high resolution is mainly used. This noise-modified sequential approximation structure has strength in quantization noise by using an oversampling technique and a noise shaping technique.

Recently, with the development of smart cars, the power engine of the car is changed from an internal combustion engine to an electric motor, and the interior of the car is controlled by various smart devices based on various types of main sensors. Analog data such as temperature, pressure, and load cell, which are signals, are selected through a multiplexer, converted into digital data through a filter and ADC, and transmitted to a smart device in the vehicle. The smart device analyzes these digital data and provides information to the driver. will provide

However, accuracy is more important than speed specifications for key sensors such as temperature, pressure, and load cells used in smart cars. Therefore, in the case of the sensor system of a smart car, the structure of the NS SAR ADC is widely used.

However, in the case of the conventional NS SAR ADC, there is a concern that the voltage gain of the comparator may change due to the influence of PVT (process, voltage, temperature), and as a result, the NTF (noise transform function) of the NS SAR ADC always has a stable value. There are downsides to maintaining it.

Therefore, there has been a need for a compensator capable of maintaining the NTF of an existing NS SAR ADC at a specific value or maintaining a stable value at all times when the NTF changes due to the influence of PVT.

KR 10-2170658 B1 2020.10.27 Announcement KR 10-1746063 B1 2017.09.04 Announcement

Therefore, the present invention is to solve the above problems, and the technical problem to be solved by the present invention is the voltage of the 3-PATH comparator of the NS SAR ADC applied to various sensors such as temperature and pressure, which are sensors mainly used in smart devices. Comparator voltage gain correction device of NS SAR ADC that can be usefully used when it is necessary to maintain the NTF of NS SAR ADC at a specific value or to keep it stable at all times by enabling the gain to be corrected using digital code that you want to provide.

An embodiment of the present invention for achieving the above object is to output an analog voltage according to a CDAC control code (CP, CM) of a preset value or a CDAC inversion code (CP', CM') opposite to the CDAC control code. CDACs; Residual voltages (V _RES, -V _RES ) and inverted residual voltages (-V _RES, V _RES ) are generated by the output of the CDAC, and the residual voltages (V _{RES ,} -V _RES ) and inverted residual voltage (-V _RES, V _RES ) are sampled, residual voltage sample capacitor (C _RES ) and 1st integrating capacitor (C _INT1 ), 1st integrating capacitor (C _INT1 ) and 2nd integral 1st integral voltage _{, 2nd} integral voltage,... _, n an nth-order integrator that generates a first order integral voltage (where n is a first, second, ...Nth order noise transform); Residual voltages (V _RES, -V _RES ) and inverted residual voltages (-V _RES, V _RES ) are sequentially supplied as inputs (INP,INM), and the first and second integral voltages,..., nth integral The voltage is provided as the 1st integrator input (INTP1,INTM1), 2nd integrator input (INTP2,INTM2), ..., nth integrator input (INTPn,INTMn), respectively, and compares them to change the output (comp_out) ( n+1)-path comparator; And while sequentially adjusting and providing voltage gain correction codes to the (n+1)-path comparator, (n+1)- A comparator voltage gain compensator of a noise transform sequential approximation type analog-to-digital converter, including a gain control unit for correcting the voltage gain of a path comparator.

According to the present invention, the voltage gain of the 3-path comparator of the NTF (noise transform function) of the NS SAR ADC applied to various sensors such as temperature and pressure, which are sensors mainly used in smart devices, can be corrected using a digital code By doing so, it can be usefully used when it is necessary to maintain the NTF of the NS SAR ADC at a specific value or to keep it stable all the time.

1 is a block diagram illustrating a comparator voltage gain compensator of a noise-transformed sequential approximation type analog-to-digital converter according to the present invention.
2 is a reference diagram illustrated to explain the flow of a second-order noise transform sequential approximation type analog-to-digital converter to which the present invention is applied.
3 (a) and (b) are detailed circuit diagrams of a preamplifier and a sense amplifier constituting a 3-path comparator.
4 (a) and (b) are graphs of FFT simulation results according to changes in comparator voltage gain (A) for the primary integrator.
5 (a) and (b) are graphs of FFT simulation results according to changes in comparator voltage gain (B) for a secondary integrator.
FIG. 6 is a graph of ENOB simulation results of a secondary noise modified sequential approximation type analog-to-digital converter for A with the comparator voltage gain fixed at 1:A:16.
FIG. 7 is a graph of ENOB simulation results of a secondary noise modified sequential approximation type analog-to-digital converter for B with the comparator voltage gain fixed at 1:B:16.
8 (a) to (d) are flow charts of a quadruple (x4) voltage gain correction operation of a comparator for a primary integrator output in a comparator voltage gain correction device of a noise-modified sequential approximation type analog-to-digital converter according to the present invention. .
9 (a) to (b) are flow charts of 16-multiple (x16) voltage gain correction operations of a comparator for a secondary integrator output in a comparator voltage gain correction device of a noise-transformed sequential approximation type analog-to-digital converter according to the present invention. .
10 (a) and (b) show the comparator voltage gain correction range for the first integrator output and the second integrator output in the comparator voltage gain correction device of the noise-modified sequential approximation type analog-to-digital converter according to the present invention. A graph illustrating the comparator voltage gain correction range.

Hereinafter, the configuration and operation of the comparator voltage gain compensator of the noise-modified sequential approximation type analog-to-digital converter according to the present invention and its effect will be described in detail with reference to the accompanying drawings.

The terms or words used in this specification and claims are not limited to the usual or dictionary meanings, and the inventor can properly define the concept of the term in order to explain his or her invention in the best way. Based on this, it should be interpreted as a meaning and concept consistent with the technical spirit of the present invention. Therefore, since the embodiments described in this specification and the configurations shown in the drawings are only the most preferred embodiments of the present invention, it is understood that there may be various equivalents and modifications that can replace them at the time of this application. shall.

1 is a block diagram illustrating a comparator voltage gain compensator of a noise-modified sequential approximation type analog-to-digital converter according to the present invention. )-path comparator 13 and a gain control unit 14, and FIG. 1 illustrates a comparator voltage gain correction device of a second-order noise transform sequential approximation type analog-to-digital converter.

The comparator voltage gain compensator of the noise-modified sequential approximation type analog-to-digital converter of the present invention is the comparator voltage gain compensator of the first-order noise-transformed sequential approximation-type analog-to-digital converter and the second-order noise-transformed sequential approximation analog-to-digital converter. Each may be implemented as a comparator voltage gain compensator or a comparator voltage gain compensator of an nth-order noise transform sequential approximation analog-to-digital converter. For example, the comparator voltage gain compensator of a first-order noise transforming sequential approximation type analog-to-digital converter can be implemented by replacing the nth-order integrator with a first-order integrator and the (n+1)-path comparator with a 2-path comparator. , The comparator voltage gain compensator of the second-order noise transform sequential approximation type analog-to-digital converter can be implemented by replacing the n-order integrator with a second-order integrator and the (n+1)-path comparator with a 3-path comparator. The comparator voltage gain compensator of the difference noise transformation sequential approximation type analog-to-digital converter can be implemented by replacing the n-order integrator with a 3-order integrator and replacing the (n+1)-path comparator with a 4-path comparator. Using the same principle as above, the comparator voltage gain compensator of the n-th noise transforming sequential approximation type analog-to-digital converter may be implemented as an n-th integrator and a (n+1)-path comparator.

In the following detailed description of the present invention, as illustrated in FIG. 1 , a comparator voltage gain correction device of a second-order noise transform sequential approximation type analog-to-digital converter will be described as an example.

The CDACs 11A and 11B are capacitor digital-to-analog converters (hereinafter, abbreviated as 'CDAC'), which are generated as outputs of the CDAC so that the voltage gain of the comparator can be corrected in a situation where the comparator compares minute voltages. A CDAC control code (CP, CM) input as a preset value (which may be set by a program or given at the time of initial design) to generate a voltage similar to the residual voltage (for example, 20 mV), or a primary integral voltage After (V _RES /4 ¹ ) is generated, the voltage supplied to the lower plate of the CDAC capacitor is controlled according to the CDAC inversion code (CP',CM') input as the opposite voltage value of the CDAC control code (CP,CM) to produce analog It outputs the voltage of the top plate of the capacitor of the CDAC of the form. The CDAC control code (CP) given in the present invention is a code for controlling the lower plate voltage of the positive CDAC. For example, CP[9:0] = 2b (binary)'1000001111', CDAC control code (CM) is the As a code for controlling the lower plate voltage, for example, CM[9:0] = 2b'0111110000'.

The n-order integrator 12 is a second-order integrator, that is, CDACs 11A and 11B operated by CDAC control codes (CP, CM) for 4-fold voltage gain correction of the comparator for the output of the first-order integrator. ) to generate residual voltages (V _RES, -V _RES ) and sample residual voltages (V RES, -V _RES ) by charge-sharing CDACs (11A _, 11B) and residual voltage sample capacitors (C _RES ), _{The CDAC} ^inverting _{code (} ^_ CDACs (11A, 11B) operated by CP', CM') and the residual voltage sample capacitor (C _RES ) charge share to obtain an inverted residual voltage (-V RES, -V _RES ) opposite to the residual voltage (V _RES, -V _{RES ).} V _RES ).

In addition, the n-order integrator 12 is output of the CDACs 11A and 11B operated by the CDAC control codes (CP, CM) to correct the quadruple voltage gain of the comparator for the output of the first integrator, and the residual voltage (V _RES, -V _RES ) and sample the residual voltage (V _RES, -V _RES ) by charge sharing the residual voltage sample capacitor (C _RES ) with the CDACs (11A, 11B), and the residual voltage sample capacitor (C _RES ) The 1st integrating capacitor (C _INT1 ) for gain correction is charge-shared to generate the 1st integrating voltage (V _RES /4 ¹ , -V _RES /4 ¹ ), and the 1st integrating capacitor (C _INT1 ) for gain correction _{CDAC (} ^_ _{_} ^_ 11A, 11B) and the residual voltage sample capacitor (C _RES ) are charge-shared to generate an inverted residual voltage (-V _RES, V _RES ) opposite to the residual voltage (V _RES, -V _RES ). Here, the first integrating capacitor (C _INT1 ) is a capacitor with a comparator voltage gain (A) for the first integrator, and the second integrating capacitor (C _INT2 ) is a capacitor with a comparator voltage gain (B) for the second integrator. .

The (n+1)-path comparator 13 is a 3-path comparator, and the residual voltages (V _RES, -V _RES ) and inverted residual voltages (-V _RES, V _RES ) generated by the nth integrator 12 are It is supplied sequentially as input (INP,INM), and the first integral voltage (V _RES /4 ¹ , -V _RES /4 ¹ ) and the second integral voltage (V _RES /4 ² , -V _RES /4 ² ) The integrator input (INTP1,INTM1) and the second integrator input (INTP2,INTM2) are received and compared, and the input (INP,INM) is 4 of the 1st integral voltage (V _RES /4 ¹ , -V _RES /4 ¹ ) ¹ times, that is, 4 times, or 4 ² times, that is, 16 times the second integral voltage (V _RES /4 ² , -V _RES /4 ² ) Output (comp_out) is, for example, '0' to '1 '.

The gain control unit 14 sequentially adjusts and provides a 4-bit comparator voltage gain correction code to the (n+1)-path comparator 13 while outputting the output (comp_out) of the (n+1)-path comparator 13. The point at which the output of the comparator changes by checking, the point at which the input of the comparator (INP,INM) becomes 4 times the first integral voltage (V _RES /4 ¹ , -V _RES /4 ¹ ), or the second integral voltage (V _RES /4 ² , -V _RES /4 ² ) stores the 4-bit comparator voltage gain correction code value at the time of 16 times, comparator voltage gain (A) for the 1st integrator and comparator voltage for the 2nd integrator The voltage gain of the (n+1)-path comparator 13 is corrected with the 4-bit comparator voltage gain correction code value stored above, in which the gain (B) falls within the range in which the NTF is stable.

)과 2차 적분기의 출력(

)은 3-path 비교기의 전압이득에 의해 증폭되어 출력된다.2 is a reference diagram illustrating the general configuration and flow of a second-order noise transformation sequential approximation type analog-to-digital converter to which the present invention is applied, and a second-order noise transformation sequential approximation type to which the present invention is applied. The analog-to-digital converter may include a first integrator, a second integrator, a 3-path comparator, and a SAR logic unit, and the output of the first integrator (

) and the output of the second integrator (

) is amplified and output by the voltage gain of the 3-path comparator.

)에 관련된 식을 나타낸 것으로서, 분모의 비교기 전압 이득 값이 Pole을 결정한다. 이때 비교기 전압 이득 값이 1차는 4, 2차는 16을 가지게 되면 Pole이 제거되어 항상 안정적인 하이패스 필터가 구현된다.Equation 1 is the final output of the second-order noise transform sequential approximation analog-to-digital converter (

), the value of the comparator voltage gain in the denominator determines the Pole. At this time, when the comparator voltage gain value is 4 for the first order and 16 for the second order, the pole is removed and a stable high-pass filter is always implemented.

) 및 2차 적분기의 출력(

)을 수학식 1에 대입한 것이며, NTF는 수학식 3이다.Equation 2 is the output of the first integrator (

) and the output of the second integrator (

) is substituted into Equation 1, and NTF is Equation 3.

(Equation 1)

(Equation 2)

(Equation 3)

는 2차 잡음 변형 축차근사형 아날로그-디지털 변환기의 최종 출력,

는 입력신호,

는 1차 적분기의 출력 ,

는 2차 적분기의 출력,

는 양자화 잡음이고, 1차 적분기의 출력(

)은 here,

is the final output of the second-order noise transformed sequential approximation analog-to-digital converter,

is the input signal,

is the output of the first integrator,

is the output of the second integrator,

is the quantization noise, and the output of the first integrator (

)silver

이고,

ego,

)은 The output of the second integrator (

)silver

이다.

am.

3 is a detailed circuit diagram of a pre-amplifier and a sense amplifier constituting a 3-path comparator, where (a) is a detailed circuit diagram of a pre-amplifier and (b) is a detailed circuit diagram of a sense-amplifier. am.

The preamplifier has the output voltage of the digital-to-analog converter, the output of the first integrator, and the output of the second integrator as input signals. The voltage gain value of the comparator is determined by the ratio of the transconductance (gm) of the MOSFET.

(Equation 4)

값은 제조공정에 의해 결정되는 양이고,

드레인 전류이며,

값은 소자 설계에 의해 결정되는 양으로서 트랜지스터의 외형 비를 나타내며 조절가능하다. 이러한 gm 값은 W, L, I_D 에 의해서 결정되며 목표하는 비율인 '4'를 얻기 위해서 제곱의 크기만큼 W 또는 I_D의 값을 증가시키거나 두 가지 값을 모두 증가시켜야 한다. 적당한 크기의 MOSFET의 크기를 고려하여 도 3 (a)와 같이 두 가지 값을 모두 변경하여 비율을 만든다. 실제로는 이상적인 비율로 비교기 전압 이득 값이 나타나지 않기 때문에 4비트의 디지털 코드로 비교기 전압 이득을 보정한다.Equation 4 is an equation used to calculate gm. here

The value is a quantity determined by the manufacturing process,

is the drain current,

The value represents the aspect ratio of the transistor as a quantity determined by device design and is adjustable. This gm value is determined by W, L, and I _D , and to obtain the target ratio of '4', the value of W or I _D must be increased by the size of the square or both values must be increased. Considering the size of a suitable size MOSFET, the ratio is made by changing both values as shown in FIG. 3 (a). Since the comparator voltage gain value does not appear in an ideal ratio in practice, the comparator voltage gain is calibrated with a 4-bit digital code.

The sense amplifier receives the output of the preamplifier and performs a comparison operation.

계수는 ‘

’보다 작아야 되며 수학식 6은 안정적인 NTF를 위한

계수의 범위이다.Equation 5 is the NTF when the comparator voltage gain ratio is 1:A:B. Here, A is the comparator voltage gain value for the first integrator output and B is the comparator voltage gain value for the second integrator output. For a stable NTF, the denominator

coefficient is '

', and Equation 6 is for a stable NTF.

range of coefficients.

(Equation 5)

(Equation 6)

계수는 '0'보다 커야 되며 수학식 7은 안정적인 NTF를 위한

계수의 범위이다. of the denominator for a stable NTF.

The coefficient must be greater than '0' and Equation 7 is for a stable NTF.

range of coefficients.

(Equation 7)

(Equation 8)

(Equation 9)

When Equation 6 and Equation 7 are calculated, B appears in the same range as Equation 8. The larger A, the smaller the magnitude of B relative to the margin of stability. When A is '4', '16', the central value of B, has a large margin for stability. Equation 9 calculates the range of A by Equation 6 when B is '16', and '4', which is the center value of Equations 7 and 9, has a large margin for stability.

4 (a) and (b) are graphs of FFT simulation results according to changes in comparator voltage gain (A) for the primary integrator. (a) is a result graph when the comparator voltage gain (A) for the primary integrator output is '1', and the shape of the noise side is unstable. (b) is the result graph when the comparator voltage gain (A) for the first integrator output is '8'. As the integrated output voltage passes through the voltage gain of the comparator, it has a value greater than the voltage of the lowest bit, resulting in harmonic distortion. characteristics appear low.

5 (a) and (b) are graphs of FFT simulation results according to changes in comparator voltage gain (B) for a secondary integrator. (a) is a result graph when the comparator voltage gain (B) for the output of the second integrator is '1', and it can be seen that the shape of the noise side is greatly reduced. (b) is a result graph when the comparator voltage gain (B) for the output of the second integrator is '32', and as in the case of A, the integrated output voltage passes through the voltage gain of the comparator and is higher than the lowest bit voltage. As it has a large value, harmonic distortion occurs, resulting in low characteristics.

FIG. 6 is a simulation of effective number of bits (ENOB) of a secondary noise modified sequential approximation analog-to-digital converter for the comparator voltage gain (A) for the primary integrator output with the comparator voltage gain fixed at 1:A:16. 7 is a graph of ENOB simulation results of a secondary noise modified sequential approximation analog-to-digital converter for comparator voltage gain (B) for the secondary integrator output with the comparator voltage gain fixed at 1:B:16. am. As a result, when A is '4 ¹ ' and B is '4 ² ', according to the simulation results, the margin of the stable state is large, the point of the pole in NTF disappears, and the stable state is reached, the ideal high pass with the most shape of the slope. become a filter

In order to stably maintain the comparator voltage gain ratio of 1:4:16, a correction circuit using the output of the capacitor digital-analog is configured.

8 is a flow chart of a quadruple (x4) voltage gain correction operation of a comparator for a primary integrator output in a comparator voltage gain correction device of a noise-modified sequential approximation type analog-to-digital converter according to the present invention, (a) is a residual voltage Generation operation, (b) exemplifies residual voltage sampling operation, (c) integrator charge sharing operation for correcting a quadruple (x4) gain, and (d) exemplifying correction operation after generating the opposite residual voltage.

8(a) is a diagram illustrating a residual voltage generation step, in which the output voltage of the capacitor digital-to-analog converter is, for example, a voltage of about 20 mV in order to perform voltage gain correction in a situation where the comparator compares minute voltages. CP[9:0] is 2b (binary)'1000001111', CM[9:0] is 2b This is the step of supplying '0111110000'. 8(b) is a diagram illustrating a residual voltage sampling step, which is a step of sampling the residual voltage generated by the CDAC control code (CP, CM) through charge sharing to C _RES . This voltage is called V _RES . 8(c) is a diagram illustrating an integrator charge sharing step for quadruple (x4) gain correction, charge sharing to an integrating capacitor (C _INT1 ) having a comparator voltage gain (A) to correct the sampled voltage V _RES It is a step. At this time, the voltage becomes V _RES /4. 8(d) is a correction step after generating the opposite residual voltage, resetting the voltage of the capacitor digital-analog converter and generating the opposite voltage. At this time, the provided 10-bit CDAC inversion code (CP',CM') is the opposite voltage value of the CDAC control code (CP,CM), and CP'[9:0] is 2b'0111110000', CM'[9:0] is Step 2b of supplying '1000001111'. At this time, the generated residual voltage of opposite polarity is sampled by charge sharing with C _RES , and -V _RES voltage is generated and supplied to the input of the comparator. The comparator input, which is not calibrated, is supplied with the same voltage, V _CM . At this time, the input of the comparator is located on the boundary immediately before comparison. By adjusting the 4-bit comparator voltage gain correction code, the comparator voltage gain is corrected with the value at the point where the comparator changes.

9 is a flowchart of a 16-multiple (x16) voltage gain correction operation of a comparator for a secondary integrator output in a comparator voltage-gain correction device of a noise-modified sequential approximation type analog-to-digital converter according to the present invention, (a) is a 16-multiple (x16) The integrator charge sharing operation for gain correction, (b) illustrates the correction operation after generating the opposite residual voltage. Here, the residual voltage generating operation and the residual voltage sampling operation proceed in the same manner as in FIGS. 8(a) and (b), respectively.

In FIG. 9 (a), charge is shared between the first integration capacitor having the comparator voltage gain for correcting the sampled voltage V _RES and the second integration capacitors C _INT1 and C _INT2 . At this time, the voltage becomes V _RES /16. 9 (b) resets the voltage of the digital-to-analog converter and generates the opposite voltage in the same way as in the operation at x4. At this time, the input of the comparator is located on the boundary immediately before comparison. By adjusting the 4-bit comparator voltage gain correction code, the comparator voltage gain is corrected with the value at the point where the comparator changes.

10 (a) and (b) show a correction range of the comparator voltage gain (A) for the first integrator output and a comparator voltage gain (B) for the second integrator output, respectively. The correction ratio range of the comparator voltage gain (A) for the first integrator output is 2-5.75 and the correction ratio range of the comparator voltage gain (B) for the second integrator output is 8-23. The comparator voltage gain (A) correction code for the first integrator output is 2b'1011, and the comparator voltage gain (B) correction code for the second integrator output is 2b'1010.

According to the present invention, the voltage gain of the 3-path comparator is obtained by using a 4-bit digital code so that the NTF of the NS SAR ADC applied to various sensors such as temperature and pressure, which are mainly used in smart devices, can always be stably maintained. can be corrected.

As described above, the present invention has been described by the limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art in the field to which the present invention belongs can make various modifications and transformation is possible Therefore, the spirit of the present invention should be grasped only by the scope of the claims described below, and all equivalent or equivalent modifications thereof will be said to belong to the scope of the spirit of the present invention.

11A, 11B: CDAC 12: nth integrator
13: (n + 1)-path comparator 14: gain control

Claims (9)

CDACs (11A, 11B) outputting analog voltages according to CDAC control codes (CP, CM) of preset values or CDAC inversion codes (CP', CM') opposite to the CDAC control codes;
Residual voltages (V _RES, -V _RES ) and inverted residual voltages (-V _RES, V _RES ) are generated as outputs of the CDACs 11A and 11B, and the CDACs 11A and 11B and the residual voltage sample capacitor (C _RES ) to sample residual voltages (V _RES, -V _RES ) and inverted residual voltages (-V _RES, V _RES ) by charge sharing, residual voltage sample capacitor (C _RES ) and primary integrating capacitor (C _INT1 ), 1st order integration by charge-sharing 1st order integrating capacitor (C _INT1 ) and 2nd order integrating capacitor (C _INT2 ), ..., n-1st order integrating capacitor (C _INTn-1 ) and nth order integrating capacitor (C _INTn ) an n-order integrator 12 that generates voltages, second-order integral voltages, ..., n-order integral voltages, where n is the 1st, 2nd,...Nth order noise transforms;
The residual voltages (V _RES, -V _RES ) and inverted residual voltages (-V _RES, V _RES ) are sequentially provided as inputs (INP, INM), and the first and second integrated voltages, ..., n order The integrated voltage is provided as the 1st integrator input (INTP1,INTM1), 2nd integrator input (INTP2,INTM2), ..., nth integrator input (INTPn,INTMn), respectively, and compares them to change the output (comp_out). (n+1)-path comparator 13; and
While sequentially adjusting and providing voltage gain correction codes to the (n+1)-path comparator 13, the voltage gain correction code value at the time when the output (comp_out) of the (n+1)-path comparator 13 changes A comparator voltage gain compensator of a noise transform sequential approximation type analog-to-digital converter, comprising: a gain controller 14 for correcting the voltage gain of the (n+1)-path comparator 13. According to claim 1,
The CDAC inversion code (CP', CM') input to the CDAC (11A, 11B) is a value input as a voltage value opposite to the CDAC control code (CP, CM) after charge sharing of the integrator for gain correction in the nth integrator. A comparator voltage gain compensator of a noise transform sequential approximation type analog-to-digital converter, characterized in that. The method of claim 1, wherein the CDACs (11A, 11B),
In a situation where the (n+1)-path comparator 13 compares microvoltages, a voltage value similar to the residual voltage generated as an output of the capacitor digital-to-analog converter (CDAC) to allow the voltage gain correction of the comparator to proceed. CDAC control code (CP,CM) of CDAC, or CDAC input as a voltage value opposite to CDAC control code (CP,CM) after the 1st integral voltage, 2nd integral voltage or nth integral voltage is generated from the nth integrator An apparatus for comparator voltage gain correction of a noise transform sequential approximation type analog-to-digital converter, characterized in that the residual voltage is generated by controlling the voltage supplied to the lower plate of the capacitor of the CDAC according to the inversion code (CP', CM'). The method of claim 1, wherein the nth integrator 12,
Residual voltages (V _RES , -V _RES ) are generated as outputs of the CDACs 11A and 11B, and charge is shared between the CDACs 11A and 11B and the residual voltage sample capacitors (C _RES ) to obtain residual voltages (V _RES , -V _RES ) is sampled, and the residual voltage sample capacitor (C _RES ) and the 1st integrating capacitor (C _INT1 ) are charge-shared to generate the 1st integral voltage, and then the residual voltage (V _RES ,-V _RES ) is reversed Residual voltage (-V _RES , V _RES ) is generated, the 1st integrating capacitor (C _INT1 ) and the 2nd integrating capacitor (C _INT2 ) are charge-shared to generate the 2nd integral voltage, and the residual voltage (V _RES , Inverted residual voltage (-V _RES , opposite to -V _RES ) A comparator voltage gain correction device for a noise-modified sequential approximation type analog-to-digital converter, characterized in that it generates V _RES ). The method of claim 4, wherein the nth integrator 12,
Noise transform sequential approximation, characterized in that the first order integral voltage is generated by charge sharing the residual voltage sample capacitor (C _RES ) and the first order integrating capacitor (C _INT1 ) having a comparator voltage gain (A) for the first integrator Analog-to-digital converter comparator voltage gain compensator. The method of claim 4, wherein the nth integrator 12,
The first integrating capacitor (C _INT1 ) with the residual voltage sample capacitor (C _RES ) and the comparator voltage gain (A) for the 1st integrator is charge-shared to generate the 1st integrating voltage, and the comparator voltage gain for the 2nd integrator Charge sharing a second order integrating capacitor (C _INT2 ) with (B) to generate a second order integral voltage and charge sharing an nth order integrating capacitor (C _INTn ) with comparator voltage gain (C) for the n order integrator to A comparator voltage gain correction device of a noise transform sequential approximation type analog-to-digital converter, characterized in that it generates a differential integral voltage. The method of claim 4, wherein the nth integrator 12,
After the 1st integral voltage, 2nd integral voltage or nth integral voltage is generated, the CDAC operated by the CDAC inversion code (CP', CM') input as the opposite voltage value to the CDAC control code (CP, CM) ( 11A, 11B) and charge sharing of the residual voltage sample capacitor (C _RES ) to generate an inverted residual voltage (-V _RES, V _RES ) opposite to the residual voltage (V _RES, -V _RES ). Comparator voltage gain compensator of sequential approximation type analog-to-digital converter. The method of claim 1, wherein the (n + 1) -path comparator 13,
A noise transformation axis characterized by changing the output (comp_out) when the input (INP,INM) becomes 4 ¹ times the first integral voltage, 4 ² times the second integral voltage, or 4 ⁿ times the nth integral voltage. Comparator voltage gain compensator of second approximation type analog-to-digital converter. The method of claim 1, wherein the gain control unit 14,
The point at which the output (comp_out) of the (n+1)-path comparator 13 changes, the point at which the comparator's inputs (INP, INM) become 4 ¹ times the first integral voltage, and 4 ² times the second integral voltage. By storing the 4-bit comparator voltage gain correction code value at the point in time and the point at which the nth integral voltage becomes 4 ⁿ times, the comparator voltage gain (A) for the first integrator and the comparator voltage gain (B) for the second integrator , and the (n + 1)-path comparator (13) with the stored 4-bit comparator voltage gain correction code value in which the comparator voltage gain (C) for the nth integrator comes within the range in which the noise transform function (NTF) is stable. Comparator voltage gain correction device of a noise transform sequential approximation type analog-to-digital converter, characterized in that for correcting the voltage gain of ).

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