KR102483533B1 - Semiconductor device array and method of manufacturing semiconductor device array using the same - Google Patents

Abstract

An embodiment is a substrate; a plurality of semiconductor structures disposed on the substrate; and an insulating layer disposed on the plurality of semiconductor structures, wherein the substrate includes a groove disposed between the plurality of semiconductor structures, and the insulating layer includes a first insulating layer disposed on the plurality of semiconductor structures. , and a second insulating layer disposed in the groove, wherein the first insulating layer and the second insulating layer are connected to each other. Disclosed is a semiconductor element array and a manufacturing method thereof.

Description

Semiconductor device array and manufacturing method thereof

The embodiment relates to a semiconductor element array and a manufacturing method thereof.

A light emitting diode (LED) is one of light emitting devices that emits light when a current is applied thereto. A light emitting diode can emit light with high efficiency at a low voltage and thus has an excellent energy saving effect. Recently, the luminance problem of light emitting diodes has been greatly improved, and they are applied to various devices such as backlight units of liquid crystal display devices, electronic signboards, displays, and home appliances.

Semiconductor devices including compounds such as GaN and AlGaN have many advantages, such as having a wide and easily adjustable band gap energy, and can be used in various ways such as light emitting devices, light receiving devices, and various diodes.

In particular, light emitting devices such as light emitting diodes or laser diodes using group 3-5 or group 2-6 compound semiconductor materials of semiconductors are developed in thin film growth technology and device materials to produce red, green, Various colors such as blue and ultraviolet can be realized, and white light with high efficiency can be realized by using fluorescent materials or combining colors. , safety, and environmental friendliness.

Recently, research on a technology for manufacturing a light emitting diode in a microscopic size and using it as a pixel of a display is being conducted.

However, it is difficult to selectively separate such micro-sized light emitting diodes from a wafer. In particular, there is a problem in that defects occur when the light emitting diode is transferred to another substrate due to particles remaining during separation.

The embodiment provides a semiconductor element array that can be easily separated from a substrate and a manufacturing method thereof.

The embodiment provides a method of manufacturing a semiconductor element array capable of preventing generation of particles when separated from a substrate.

The problem to be solved in the embodiment is not limited thereto, and it will be said that the solution to the problem described below or the purpose or effect that can be grasped from the embodiment is also included.

A semiconductor element array according to an embodiment of the present invention includes a substrate; a plurality of semiconductor structures disposed on the substrate; and an insulating layer disposed on the plurality of semiconductor structures, wherein the substrate includes a groove disposed between the plurality of semiconductor structures, and the insulating layer includes a first insulating layer disposed on the plurality of semiconductor structures. , and a second insulating layer disposed in the groove, wherein the first insulating layer and the second insulating layer are connected to each other.

The semiconductor structure may include a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer.

a first electrode electrically connected to the first conductivity-type semiconductor layer through the first insulating layer; and a second electrode electrically connected to the second conductivity-type semiconductor layer through the first insulating layer.

A method of manufacturing a semiconductor element array according to an embodiment of the present invention includes forming a semiconductor structure layer on a first substrate; Cutting the semiconductor structure layer into a plurality of semiconductor structures; Forming electrodes on the plurality of semiconductor structures; and forming an insulating layer on the plurality of semiconductor structures, and in the cutting, a groove is formed on the first substrate when the semiconductor structure layer is cut.

Forming the semiconductor structure layer may include forming a sacrificial layer on the first substrate; and forming the semiconductor structure layer on the sacrificial layer.

In the forming of the insulating layer, the insulating layer may be formed on the plurality of semiconductor structures and the groove.

After forming the insulating layer, selectively separating the plurality of semiconductor structures may be included.

The semiconductor structure may be selectively separated by irradiating a laser onto the rear surface of the first substrate.

The sacrificial layer may be separated by absorbing the laser.

The semiconductor structure may include a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer.

Sidewalls of the groove may have the same inclination angle as sidewalls of the plurality of semiconductor structures.

A step of forming a step in the semiconductor structure layer between the step of forming the semiconductor structure layer and the step of cutting, wherein the step of forming the step includes etching the semiconductor structure layer at regular intervals to perform the first conductive layer. The type semiconductor layer may be exposed.

According to an embodiment of the present invention, it is possible to improve a phenomenon in which an insulating layer is broken when a semiconductor device is separated from a wafer.

Various advantageous advantages and effects of the present invention are not limited to the above description, and will be more easily understood in the process of describing specific embodiments of the present invention.

1A to 1G are diagrams showing a method of manufacturing a semiconductor element array according to an embodiment of the present invention;
2 is a plan view of a semiconductor element array according to an embodiment of the present invention;
3A to 3E are diagrams showing a method of transferring a semiconductor device according to an embodiment of the present invention;
4A is a photograph of a semiconductor device before being separated from a substrate;
4B is a photograph after the semiconductor device is separated from the substrate;
5 is a photograph showing a state in which a semiconductor device is cleanly separated from a substrate according to an embodiment of the present invention;
6 is a view showing a method of separating a semiconductor device without etching a sacrificial layer;
7 is a view showing a state in which particles remain when the semiconductor device is separated by the method of FIG. 6;
8 is a diagram of a semiconductor device according to an embodiment of the present invention;
9 is a conceptual diagram of a display device to which a semiconductor element is transferred according to an exemplary embodiment.

The present embodiments may be modified in other forms or combined with each other, and the scope of the present invention is not limited to each of the embodiments described below.

Even if a matter described in a specific embodiment is not described in another embodiment, it may be understood as a description related to another embodiment, unless there is a description contrary to or contradictory to the matter in another embodiment.

For example, if the characteristics of component A are described in a specific embodiment and the characteristics of component B are described in another embodiment, the opposite or contradictory description even if the embodiment in which components A and B are combined is not explicitly described. Unless there is, it should be understood as belonging to the scope of the present invention.

In the description of the embodiment, in the case where an element is described as being formed “on or under” of another element, on or under (on or under) or under) includes both elements formed by directly contacting each other or by indirectly placing one or more other elements between the two elements. In addition, when expressed as "on or under", it may include the meaning of not only the upward direction but also the downward direction based on one element.

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily carry out the present invention.

Also, the semiconductor device package according to the present embodiment may include a micro-sized or nano-sized semiconductor device. Here, the small-sized semiconductor device may refer to the structural size of the semiconductor device. In addition, the size of the small-sized semiconductor device may be 1 μm to 100 μm. In addition, the semiconductor device according to the embodiment may have a size of 30 μm to 60 μm, but is not necessarily limited thereto. Also, the technical features or aspects of the embodiments can be applied to semiconductor devices on a smaller size scale.

1A to 1G are views illustrating a method of manufacturing a semiconductor device array according to an exemplary embodiment of the present invention.

A method of manufacturing a semiconductor element array according to an embodiment of the present invention includes forming a first substrate; forming a semiconductor structure layer on the first substrate; Cutting the semiconductor structure layer into a plurality of semiconductor structures; Forming electrodes on the plurality of semiconductor structures; And it may include forming an insulating layer on the plurality of semiconductor structures.

Referring to FIG. 1A , in the step of forming the first substrate, first, ions may be implanted into the donor substrate S. The donor substrate S may include an ion layer I. Due to the ion layer I, the donor substrate S may include an intermediate layer 170 disposed on one side and a first layer 171 disposed on the other side. Ions implanted into the donor substrate S may include hydrogen (H) ions, but are not limited to these materials.

Referring to FIG. 1B , the sacrificial layer 120 may be disposed between the substrate 110 and the bonding layer 130 .

The substrate 110 may be a light-transmitting substrate including sapphire (Al ₂ O ₃ ), glass, or the like. Accordingly, the substrate 110 may transmit laser light irradiated from the bottom. Accordingly, the sacrificial layer 120 may absorb laser light when the laser lift is off.

A sacrificial layer 120 and a bonding layer 130 may be stacked on the substrate 110 . The order of the sacrificial layer 120 and the bonding layer 130 may be reversed.

The bonding layer 130 disposed on the substrate may be disposed to face the bonding layer 130 disposed on the donor substrate S. The bonding layer 130 disposed on the substrate and the bonding layer 130 disposed on the donor substrate S may include SiO ₂ , but are not necessarily limited thereto.

The bonding layer 130 disposed on the sacrificial layer 120 may be bonded to the bonding layer 130 disposed on the donor substrate S through O ₂ plasma treatment. However, it is not limited thereto, and cutting may be performed by a material other than oxygen.

Thus, the sacrificial layer 120 is disposed on the substrate 110, the bonding layer 130 is disposed on the sacrificial layer 120, and the donor substrate S is disposed spaced apart from above the bonding layer 130. can

Referring to FIG. 1C , the ion layer I of FIG. 1B may be removed by fluid jet cleaving, so that the first layer 171 may be separated from the intermediate layer 170 .

At this time, the first layer 171 separated from the donor substrate may be reused as a substrate. Therefore, it is possible to provide an effect of reducing manufacturing cost and cost.

In the forming of the semiconductor structure layer on the first substrate, the semiconductor structure 140 may be formed on the intermediate layer 170 . The intermediate layer 170 may contact the semiconductor structure 140 . However, since the upper surface of the intermediate layer 170 has poor roughness due to voids generated by the ion implantation process, defects may occur during deposition of Red Epi.

Accordingly, a planarization process may be performed on the top surface of the intermediate layer 170 . For example, chemical mechanical planarization is performed on the upper surface of the intermediate layer 170, and the semiconductor structure 140 may be disposed on the upper surface of the intermediate layer 170 after planarization. Due to this configuration, electrical characteristics of the semiconductor structure 140 may be improved.

The semiconductor structure 140 includes a first conductivity-type semiconductor layer 141 disposed on the intermediate layer 170, a first cladding layer 144 disposed on the first conductivity-type semiconductor layer, and a first cladding layer 144 disposed on the intermediate layer 170. It may include an active layer 142 disposed on the active layer 142 and a second conductive semiconductor layer 143 disposed on the active layer 142 . A specific configuration of the semiconductor structure 140 will be described later.

Referring to FIG. 1D , primary etching may be performed to expose the first conductivity-type semiconductor layer 141 on the top of the semiconductor structure 140 .

The primary etching may be performed by wet etching or dry etching, but is not limited thereto, and various methods may be applied. Before the first etching is performed, the second electrode 152 of FIG. 1E may be disposed on the second conductive semiconductor layer 143 and patterned as shown in FIG. 1E. However, it is not limited to this method.

Referring to FIG. 1E , in the step of forming an electrode on a semiconductor structure, a first electrode 151 and a second electrode 152 may be formed on the semiconductor structure 140 .

The second electrode 152 may be electrically connected to the 2-2nd conductivity type semiconductor layer 143b. An area of a lower surface of the second electrode 152 may be smaller than an upper surface of the second conductive semiconductor layer 143 . For example, the second electrode 152 may be spaced apart from the edge of the 2-2 conductivity type semiconductor layer 143b by 1 μm to 3 μm.

For the first electrode 151 and the second electrode 152, any electrode formation method commonly used, such as stuffing, coating, or deposition, may be applied. However, it is not limited thereto.

In addition, as described above, the second electrode 152 is formed before the first etching, and after the first etching, the first electrode 151 is etched and disposed on the exposed upper surface of the first conductivity type semiconductor layer 41. can

The first electrode 151 and the second electrode 152 may be disposed at different positions from the substrate 110 . The first electrode 151 may be disposed on the first conductivity type semiconductor layer 141 . The second electrode 152 may be disposed on the second conductivity type semiconductor layer 143 . Accordingly, the second electrode 152 may be disposed above the first electrode 151 .

Referring to FIG. 1F , in the step of cutting into a plurality of semiconductor structures, secondary etching may be performed to the upper surface of the substrate 110 . The secondary etching may be performed by wet etching or dry etching, but is not limited thereto. In a semiconductor device, secondary etching may be performed to a greater thickness than primary etching.

The semiconductor structure disposed on the substrate through the secondary etching may be isolated in the form of a plurality of chips. For example, in FIG. 1F , two semiconductor structures may be disposed on the substrate 110 through secondary etching. The number of semiconductor structures may be variously set according to the size of the substrate and the size of the semiconductor structure. At this time, the step of separating the semiconductor structure and the step of forming the electrode may be reversed in order. That is, the electrode may be formed first and then the semiconductor structure may be separated, or the electrode may be formed after the semiconductor structure is separated. In addition, the electrode may be formed after the first etching of the semiconductor structure, and then the semiconductor structure may be separated.

In this case, the secondary etching may pass through the semiconductor structure and proceed to a partial area of the substrate 110 . Accordingly, the substrate 110 may have grooves H1 disposed between a plurality of semiconductor structures. Since the groove H1 of the substrate is formed in the process of etching the semiconductor structure 140 , the sidewall of the groove H1 may have the same inclination angle as that of the plurality of semiconductor structures 140 . However, it is not necessarily limited thereto, and the groove H1 of the substrate may be formed by a separate etching process.

According to this configuration, it is possible to reliably remove the bonding layer 120 and/or the sacrificial layer 130 disposed between the plurality of semiconductor structures. The depth of the groove H1 is not particularly limited as long as it can remove the bonding layer 120 and/or the sacrificial layer 130 disposed between the semiconductor structures.

If, when the bonding layer and/or the sacrificial layer of the semiconductor structure are connected to each other, when one semiconductor structure is separated from the substrate, neighboring semiconductor structures may be affected.

Illustratively, when only one semiconductor structure is separated from the substrate, a problem may occur in which the sacrificial layer of the adjacent semiconductor structure is also separated from the substrate.

Referring to FIG. 1G , in the forming of the insulating layer, the insulating layer 160 may be formed on the plurality of semiconductor structures 140 and the groove H1 as a whole. The insulating layer 160 may cover side surfaces of the sacrificial layer 120 , the bonding layer 130 , the intermediate layer 170 , and the semiconductor structure 140 .

The insulating layer 160 may cover even a portion of the upper surface of the first electrode 151 . A portion of the upper surface of the first electrode 151 may be exposed. The exposed upper surface of the first electrode 151 is electrically connected to an electrode pad, etc., so that current injection or the like can be performed.

In addition, the insulating layer 160 may cover a portion of the upper surface of the second electrode 152 . A portion of the upper surface of the second electrode 152 may be exposed. Like the first electrode 151, the exposed upper surface of the second electrode 152 is electrically connected to an electrode pad, etc., so that current injection or the like can be performed. A portion of the insulating layer 160 may be disposed on the upper surface of the substrate. The insulating layer 160 disposed between adjacent semiconductor chips may be disposed in contact with the substrate 110 .

Referring to FIG. 1G , the fabricated semiconductor device array may include a substrate 110 and a plurality of semiconductor devices 10 disposed on the substrate 110 . According to the embodiment, a plurality of semiconductor devices 10 may be disposed on the substrate 110 .

The plurality of semiconductor elements 10 include a first conductivity type semiconductor layer 144, a second conductivity type semiconductor layer 143, and between the first conductivity type semiconductor layer 144 and the second conductivity type semiconductor layer 143. The semiconductor structure 140 including the active layer 142 disposed on the semiconductor structure 140, the insulating layer 160 disposed on the semiconductor structure 140, and the first conductivity type semiconductor layer 144 passing through the insulating layer 160 and electrically It may include a first electrode 151 connected to and a second electrode 152 electrically connected to the second conductive semiconductor layer 143 through the insulating layer 160 .

As described above, the substrate 110 may include a groove H1 disposed between the plurality of semiconductor structures 140. The groove H1 may have a line shape, but is not necessarily limited thereto.

The insulating layer 160 may include a first insulating layer 161 disposed on top and side surfaces of the semiconductor structure 140 and a second insulating layer 162 disposed in the groove H1 of the substrate 110. there is. In this case, the first insulating layer 161 and the second insulating layer 162 may be connected to each other.

The insulating layer 160 may entirely cover the plurality of semiconductor structures 140 , one surface of the substrate 110 , and the groove H1 of the substrate 110 .

The upper surface of the semiconductor structure 140 includes a first upper surface S11 on which the first electrode 151 is disposed, a second upper surface S12 on which the second electrode 152 is disposed, and a first upper surface S1. and an inclined surface S13 disposed between the second upper surface S2.

At this time, the difference between the height P1 from the bottom surface of the semiconductor structure 140 to the second upper surface S12 and the height P2 from the bottom surface of the semiconductor structure 140 to the first upper surface S11 ( P3) may be greater than 0 and less than 2 μm.

When the height difference P3 between the first upper surface S11 and the second upper surface S12 is greater than 2 μm, the chip may be leveled during the transfer process. That is, as the step difference increases, it may be difficult to keep the chip level. The transfer process may mean an operation of transferring a chip from a growth substrate to another substrate as shown in FIG. 3 .

The first angle θ ₁ formed by the inclined surface S13 and the horizontal surface may be smaller than the second angle θ ₂ formed between the side surface of the semiconductor structure 140 and the horizontal surface. A first angle θ ₁ between the inclined surface S13 and the virtual horizontal surface may be 20° to 50°. When the first angle θ ₁ is smaller than 20°, the area of the second upper surface S12 is reduced, and thus light output may decrease. In addition, when the first angle θ ₁ is greater than 50°, the inclination angle increases, and thus the risk of damage due to external impact may increase.

The second angle θ ₂ between the side surface of the semiconductor structure 120 and the horizontal plane may be greater than 70° and smaller than 90°. When the second angle θ ₂ is less than 70°, the area of the second upper surface S12 is reduced, and thus light output may decrease. When the second angle θ ₂ formed by all side surfaces of the semiconductor structure 120 with the horizontal plane is less than 90°, the area of the inclined surface S13 gradually increases from the first upper surface S11 to the second upper surface S12. can be narrowed

2 is a plan view of a semiconductor element array according to an exemplary embodiment of the present invention.

Referring to FIG. 2 , each semiconductor device 10 may have a long side surface E1 and a short side surface on a plane, and the long side surface E1 may have a micro size smaller than 100 μm. For example, when the substrate 110 is 5 inches, a myriad of semiconductor devices may be disposed on the substrate 110 .

On a plane, the groove H1 may be disposed to surround one semiconductor element 10 . For example, the groove H1 may have a checkerboard shape in which the first direction groove H11 and the second direction groove H12 are formed, respectively. The semiconductor device 10 may be respectively disposed in a space surrounded by the first direction groove H11 and the second direction groove H12.

The insulating layer 160 may be entirely disposed on the substrate 110 on which the plurality of semiconductor structures are disposed. The insulating layer 160 may also be disposed on the first direction grooves H11 and the second direction grooves H12 of the substrate 110 . That is, the insulating layer 160 may be entirely disposed on the remaining area except for the holes 160a and 160b exposing the electrodes of the semiconductor device 10 .

3A to 3E are diagrams illustrating a method of transferring a semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 3A to 3E , in a method of transferring a semiconductor device according to an exemplary embodiment, a laser is selectively irradiated to a semiconductor device including a plurality of semiconductor devices disposed on a substrate 110 to separate the semiconductor device from the substrate. and disposing the separated semiconductor device on the panel substrate. Here, the semiconductor device before transfer may include the configurations of FIGS. 1A to 1G as they are.

First, referring to FIG. 3A , the substrate 110 may be the same as the substrate 110 described above with reference to FIGS. 1A to 1G . Also, as described above, a plurality of semiconductor devices may be disposed on the substrate 110 . For example, the plurality of semiconductor devices may include a first semiconductor device 10-1, a second semiconductor device 10-2, a third semiconductor device 10-3, and a fourth semiconductor device 10-4. there is. However, it is not limited to this number, and the semiconductor device may have various numbers.

Referring to FIG. 3B , at least one semiconductor device selected from among the plurality of semiconductor devices 10-1, 10-2, 10-3, and 10-4 may be separated into a growth substrate by using a transfer mechanism 210. . The transport mechanism 210 may include a first bonding layer 211 and a transport frame 212 disposed below. Illustratively, the transport frame 212 has a concavo-convex structure, so that the semiconductor element and the first bonding layer 211 can be easily bonded. At this time, since the step difference of the semiconductor device according to the embodiment is smaller than 2 μm, it can be maintained horizontally during the transfer process.

Referring to FIG. 3C , when a laser is selectively irradiated to the rear surface of the semiconductor elements 10-1 and 10-3 to be separated, the sacrificial layer of the semiconductor elements 10-1 and 10-3 is decomposed and the substrate 110 is formed. can be separated from Thereafter, when the transport mechanism 210 is moved upward, the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 may be separated from the transport mechanism 210 . Also, bonding between the second bonding layer 310 and the first semiconductor element 10-1 and the third semiconductor element 10-3 may be formed.

As a method of separating the semiconductor device from the substrate 110, laser lift-off (LLO) using a photon beam of a specific wavelength band may be applied. For example, the central wavelength of the irradiated laser may be 266 nm, 532 nm, or 1064 nm, but is not limited thereto.

In this case, the bonding layer 130 disposed between the semiconductor device and the substrate 110 may prevent physical damage between the semiconductor devices due to laser lift-off (LLO). The sacrificial layer may be separated from the semiconductor device by laser lift-off (LLO). For example, a part of the sacrificial layer may be removed due to separation and the remaining sacrificial layer may be separated together with the bonding layer. Accordingly, in the semiconductor device, the sacrificial layer, the bonding layer that is a layer disposed on the sacrificial layer, the semiconductor structure, the first electrode, and the second electrode may be separated into the substrate 110 .

In addition, a plurality of semiconductor elements separated by the substrate 110 may have a predetermined distance from each other. As described above, the first semiconductor element 10-1 and the third semiconductor element 10-3 are separated from the growth substrate, and the first semiconductor element 10-1 and the third semiconductor element 10-3 The second semiconductor element 10 - 2 and the fourth semiconductor element 10 - 4 having the same distance as the separation distance of may be separated in the same manner. Accordingly, semiconductor elements having the same separation distance may be transferred to the display panel.

Referring to FIG. 3D , a selected semiconductor device may be disposed on the panel substrate 300 . For example, the first semiconductor element 10 - 1 and the third semiconductor element 10 - 3 may be disposed on the panel substrate 300 .

Specifically, the second bonding layer 310 may be disposed on the panel substrate 300, and the first semiconductor element 10-1 and the third semiconductor element 10-3 are formed by the second bonding layer 310. can be placed on top. Accordingly, the first semiconductor element 10 - 1 and the third semiconductor element 10 - 3 may come into contact with the second bonding layer 310 . Through this method, the efficiency of the transfer process can be improved by arranging the semiconductor devices having spaced apart intervals on the panel substrate.

A laser may be irradiated to separate the first bonding layer 211 and the selected semiconductor device. For example, laser is irradiated onto the transport mechanism 210, and the first bonding layer 211 and the selected semiconductor device may be physically separated. For example, the bonding layer 211 may lose its adhesive function when laser is irradiated thereon.

Referring to FIG. 3E , when the transport mechanism 210 is moved upward after laser irradiation, the first semiconductor device 10-1 and the third semiconductor device 10-3 may be separated from the transport mechanism 210. there is. Also, bonding between the second bonding layer 310 and the first semiconductor element 10-1 and the third semiconductor element 10-3 may be formed.

4a is a picture before the semiconductor device is separated from the substrate, FIG. 4b is a picture after the semiconductor device is separated from the substrate, and FIG. 5 is a picture showing a state in which the semiconductor device is cleanly separated from the substrate according to an embodiment of the present invention. to be.

Referring to FIG. 4A , in the semiconductor device according to the embodiment, the first and second insulating layers 161 and 162 are formed on the side surface of the semiconductor structure 140 and in the groove H1 of the substrate 110 to form a sacrificial layer 130 ) can be seen to be completely separated. In addition, when some semiconductor elements are separated from the substrate 110 as shown in FIG. 4B , only the second insulating layer 162 disposed in the groove H1 remains, indicating that the first insulating layer 161 is cleanly separated. Referring to FIG. 5 , it can be confirmed that there are no particles generated when the sacrificial layer or the insulating layer is separated in the region F1 from which the semiconductor element is separated.

FIG. 6 is a view showing a method of separating a semiconductor device without etching the sacrificial layer, and FIG. 7 is a view showing a state in which particles remain when the semiconductor device is separated by the method of FIG. 6 .

As shown in FIG. 6 , when only the semiconductor structure is secondary etched and the sacrificial layer SL1 is not etched, adjacent semiconductor devices may be affected during the process of separating the semiconductor device.

For example, when the sacrificial layer SL1 is thick, there is a problem in that the sacrificial layer SL1 of the channel region CH is irregularly separated during a lift-off process. Here, the channel region may be defined as a region between adjacent semiconductor structures.

In addition, when the sacrificial layer remains thin in the channel region, particles may be formed while the remaining sacrificial layer SL1 is separated as shown in FIG. 7 . Such particles may cause defects in the transfer process. Therefore, in an embodiment of the present invention, such a defect can be prevented by etching the sacrificial layer of the channel region in advance.

8 is a diagram of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 8 , the semiconductor device according to the embodiment includes a sacrificial layer 120, a bonding layer 130 disposed on the sacrificial layer 120, an intermediate layer 170 disposed on the bonding layer 130, and an intermediate layer ( 170), a first conductivity-type semiconductor layer 141 disposed on the first conductive semiconductor layer, a first cladding layer 144 disposed on the first conductivity-type semiconductor layer, and an active layer 142 disposed on the first cladding layer 144 , a second conductivity type semiconductor layer 143 disposed on the active layer, a first electrode 151 electrically connected to the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer electrically connected to the second conductivity type semiconductor layer. The electrode 152, the sacrificial layer 120, the bonding layer 130, the first conductivity type semiconductor layer 141, the first cladding layer 144, the active layer 142, and the second conductivity type semiconductor layer 142 are formed. An enclosing insulating layer 160 may be included.

The sacrificial layer 120 may be a lowermost layer of the semiconductor device according to the embodiment. That is, the sacrificial layer 120 may be an outermost layer in the 1-2 direction (X ₂ axis direction). The sacrificial layer 120 may be disposed on a substrate (not shown).

The maximum width W ₁ of the sacrificial layer 120 in the second direction (Y-axis direction) may be 30 μm to 60 μm.

Here, the first direction includes a 1-1 direction and a 1-2 direction in the thickness direction of the semiconductor structure 140 . The 1-1 direction is a direction from the first conductivity type semiconductor layer 121 to the second conductivity type semiconductor layer 123 in the thickness direction of the semiconductor structure 140 . Also, the first-second direction is a direction from the second conductivity type semiconductor layer 123 to the first conductivity type semiconductor layer 121 in the thickness direction of the semiconductor structure 140 . Also, here, the second direction (Y-axis direction) may be a direction perpendicular to the first direction (X-axis direction). Further, the second direction (Y-axis direction) includes a 2-1 direction (Y1-axis direction) and a 2-2 direction (Y2-axis direction).

The sacrificial layer 120 may be a layer left while transferring a semiconductor device to a display device. For example, when a semiconductor device is transferred to a display device, a portion of the sacrificial layer 120 may be separated by a laser irradiated during transfer, and other portions may be left. At this time, the sacrificial layer 120 may include a material separable from the wavelength of the irradiated laser. In addition, the wavelength of the laser may be any one of 266 nm, 532 nm, and 1064 nm, but is not limited thereto.

The sacrificial layer 120 may include oxide or nitride. However, it is not limited thereto. For example, the sacrificial layer 120 may include an oxide-based material as a material with little deformation generated during epitaxial growth.

The sacrificial layer 120 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and indium gallium tin oxide (IGTO). ), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx , NiO, RuOx/ITO, Ni/IrOx/Au, or Ni/IrOx/Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt, At least one of Au and Hf may be included.

The sacrificial layer 120 may have a thickness d ₁ of 20 nm or more in the first direction (X-axis direction). Preferably, the sacrificial layer 120 may have a thickness (d ₁ ) of 40 nm or more in the first direction (X-axis direction).

The sacrificial layer 120 may be formed by E-beam evaporator, thermal evaporator, MOCVD (Metal Organic Chemical Vapor Deposition), sputtering, and PLD (Pulsed Laser Deposition). , but not limited thereto.

The bonding layer 130 may be disposed on the sacrificial layer 120 . The bonding layer 130 may include materials such as SiO ₂ , SiNx, TiO ₂ , polyimide, and resin.

The thickness (d ₂ ) of the bonding layer 130 may be 30 nm to 1 μm. However, it is not limited thereto. Here, the thickness may be a length in the X-axis direction. The bonding layer 130 may be annealed to bond the sacrificial layer 120 and the intermediate layer 170 to each other. At this time, peeling may occur as hydrogen ions in the bonding layer 130 are discharged. Accordingly, the bonding layer 130 may have a surface roughness of 1 nm or less. With this configuration, the separation layer and the bonding layer can be easily bonded. Placement positions of the bonding layer 130 and the sacrificial layer 120 may be interchanged.

The intermediate layer 170 may be disposed on the bonding layer 130 . The intermediate layer 170 may include GaAs. The intermediate layer 170 may be combined with the sacrificial layer 120 through the bonding layer 130 .

The semiconductor structure 140 may be disposed on the intermediate layer 170 . The semiconductor structure 140 includes a first conductivity-type semiconductor layer 141 disposed on the intermediate layer 170, a first cladding layer 144 disposed on the first conductivity-type semiconductor layer, and a first cladding layer 144 disposed on the intermediate layer 170. It may include an active layer 142 disposed on the active layer 142 and a second conductive semiconductor layer 143 disposed on the active layer 142 .

The first conductivity type semiconductor layer 141 may be disposed on the intermediate layer 170 . The thickness d ₄ of the first conductivity-type semiconductor layer 141 may be 1.8 μm to 2.2 μm. However, it is not limited thereto.

The first conductivity-type semiconductor layer 141 may be implemented with a compound semiconductor such as group III-V or group II-VI, and may be doped with a first dopant. The first conductivity type first semiconductor layer 112 is InxAlyGa1-x-yP (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or InxAlyGa1-x-yN (0≤x≤1 , 0≤y≤1, 0≤x+y≤1) may include a semiconductor material having a composition formula.

Also, the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te. When the first dopant is an n-type dopant, the first conductivity-type semiconductor layer 141 doped with the first dopant may be an n-type semiconductor layer.

The first conductive semiconductor layer 141 may include one or more of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

The first conductivity-type semiconductor layer 141 may be formed using a method such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering, or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto. .

The first cladding layer 144 may be disposed on the first conductivity type semiconductor layer 141 . The first cladding layer 144 may be disposed between the first conductivity type semiconductor layer 141 and the active layer 142 . The first clad layer 144 may include a plurality of layers. The first cladding layer 144 may include an AlInP-based layer/AlInGaP-based layer.

The thickness (d ₅ ) of the first cladding layer 144 may be 0.45 μm to 0.55 μm. However, it is not limited thereto.

The active layer 142 may be disposed on the first cladding layer 144 . The active layer 142 may be disposed between the first conductivity type semiconductor layer 141 and the second conductivity type semiconductor layer 143 . The active layer 142 is a layer where electrons (or holes) injected through the first conductivity type semiconductor layer 141 and holes (or electrons) injected through the second conductivity type semiconductor layer 143 meet. The active layer 142 transitions to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.

The active layer 142 may have a structure of any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the active layer 142 ) The structure of is not limited to this.

The active layer 142 may have a pair structure of one or more of GaInP/AlGaInP, GaP/AlGaP, InGaP/AlGaP, InGaN/GaN, InGaN/InGaN, GaN/AlGaN, InAlGaN/GaN, GaAs/AlGaAs, and InGaAs/AlGaAs. but not limited to

A thickness d ₆ of the active layer 142 may be 0.54 μm to 0.66 μm. However, it is not limited thereto.

As electrons are cooled in the first cladding layer 144 , more radiation recombination may occur in the active layer 142 .

The second conductivity type semiconductor layer 143 may be disposed on the active layer 142 . The second conductivity type semiconductor layer 143 may include a 2-1st conductivity type semiconductor layer 143a and a 2-2nd conductivity type semiconductor layer 143b.

The 2-1st conductivity type semiconductor layer 143a may be disposed on the active layer 142 . The 2-2nd conductivity type semiconductor layer 143b may be disposed on the 2-1st conductivity type semiconductor layer 143a.

The 2-1st conductivity type semiconductor layer 143a may include TSBR or P-AllnP. The thickness d ₇ of the 2-1st conductivity type semiconductor layer 143a may be 0.57 μm to 0.70 μm. However, it is not limited thereto.

The 2-1st conductivity type semiconductor layer 143a may be implemented with a compound semiconductor such as group III-V or group II-VI. A second dopant may be doped into the 2-1st conductivity type semiconductor layer 143a.

The 2-1 conductivity type semiconductor layer 143a is InxAlyGa1-x-yP (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or InxAlyGa1-x-yN (0≤x≤1 , 0≤y≤1, 0≤x+y≤1) may include a semiconductor material having a composition formula. When the second conductivity-type semiconductor layer 143 is a p-type semiconductor layer, Mg, Zn, Ca, Sr, Ba, or the like may be included as a p-type dopant.

The 2-1st conductivity type semiconductor layer 143a doped with the second dopant may be a p-type semiconductor layer.

The 2-2nd conductivity type semiconductor layer 143b may be disposed on the 2-1st conductivity type semiconductor layer 143a. The 2-2 conductivity type semiconductor layer 143b may include a p-type GaP-based layer.

The 2-2 conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer/InxGa1-xP layer (where 0≤x≤1).

For example, the 2-2 conductivity type semiconductor layer 143b may be doped with Mg at a concentration of about ^10X10-18 , but is not limited thereto.

In addition, the 2-2 conductivity type semiconductor layer 143b may consist of a plurality of layers and only some of the layers may be doped with Mg.

The thickness d ₈ of the 2-2nd conductivity type semiconductor layer 143b may be 0.9 μm to 1.1 μm. However, it is not limited thereto.

The first electrode 151 may be disposed on the first conductivity type semiconductor layer 141 . The first electrode 151 may be electrically connected to the first conductive semiconductor layer 141 .

The first electrode 151 may be disposed on a portion of the top surface of the first conductivity-type semiconductor layer 141 on which mesa etching is performed. Accordingly, the first electrode 151 may be disposed below the second electrode 152 disposed on the upper surface of the second conductivity type semiconductor layer 143 .

The shortest width (W ₂ ) in the 2-2 direction (Y ₂ axis direction) between the edge and the second electrode 152 in the 2-2 direction (Y ₂ axis direction) of the insulating layer 160 is 2.5 μm to It may be 3.5 μm. Similarly, the shortest width (W ₆ ) in the 2-1 direction (Y ₁ axis direction) between the edge and the first electrode 151 in the 2-1 direction (Y ₁ axis direction) of the insulating layer 160 is 2.5 μm. to 3.5 μm. However, it is not limited to this length.

The first electrode 151 may be indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), or indium gallium tin (IGTO). oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, or Ni/IrOx/Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt , Au, and may be formed including at least one of Hf, but is not limited to these materials.

For the first electrode 151, any electrode forming method commonly used, such as stuffing, coating, or deposition, may be applied.

As described above, the second electrode 152 may be disposed on the 2-2nd conductivity type semiconductor layer 143b. The second electrode 152 may be electrically connected to the 2-2nd conductivity type semiconductor layer 143b.

The second electrode 152 may be indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), or indium gallium tin (IGTO). oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, or Ni/IrOx/Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt , Au, and may be formed including at least one of Hf, but is not limited to these materials.

For the second electrode 152, any electrode forming method commonly used, such as stuffing, coating, or deposition, may be applied.

Also, the first electrode 151 may have a wider width than the second electrode 152 in the second direction (Y-axis direction). However, it is not limited to this length.

The insulating layer 160 may cover the sacrificial layer 120 , the bonding layer 130 and the semiconductor structure 140 . The insulating layer 160 may cover the side surfaces of the sacrificial layer 120 and the side surfaces of the bonding layer 130 . The insulating layer 160 may cover a portion of the upper surface of the first electrode 151 . According to this configuration, the first electrode 151 is electrically connected to the electrode or pad through the exposed upper surface so that current can be injected. Similarly, the second electrode 152 may include an exposed top surface like the first electrode 151 . The insulating layer 160 covers the bonding layer 130 and the sacrificial layer 120, so the sacrificial layer 120 and the bonding layer 130 may not be exposed to the outside.

The insulating layer 160 may cover a portion of the upper surface of the first electrode 151 . In addition, the insulating layer 160 may cover a portion of the upper surface of the second electrode 152 . A portion of the upper surface of the first electrode 151 may be exposed. A portion of the upper surface of the second electrode 152 may be exposed.

The exposed upper surface of the first electrode 151 and the exposed upper surface of the second electrode 152 may be circular, but are not limited thereto. Also, a distance W ₄ between the center point of the top surface of the exposed first electrode 151 and the center point of the top surface of the second electrode 152 in the second direction (Y-axis direction) may be 20 μm to 30 μm. Here, the central point refers to a point at which the widths of the exposed first electrode and the exposed second electrode are divided into two in the second direction (Y-axis direction).

_The maximum width ₍ W ₅ ) may be 5.5 μm to 7.5 μm. In addition, the maximum width in the 2-2 axis direction (Y ₂ axis direction) between the center point of the exposed second electrode 152 and the edge of the second electrode 152 in the 2-2 axis direction (Y ₂ axis direction) (W ₆ ) may be 5.5 μm to 7.5 μm. However, it is not limited to this length.

The insulating layer 160 may electrically separate the first conductivity type semiconductor layer 141 and the second conductivity type semiconductor layer 143 in the semiconductor structure 140 . The insulating layer 160 may be formed by selecting at least one from the group consisting of SiO ₂ , SixOy, Si ₃ N ₄ , Si _x N _y , SiO _x N _y , Al ₂ O ₃ , TiO ₂ , AlN, and the like. Not limited to this.

9 is a conceptual diagram of a display device to which a semiconductor element is transferred according to an exemplary embodiment.

Referring to FIG. 9 , in an exemplary embodiment, a display device including a semiconductor device includes a second panel substrate 410, a driving thin film transistor T2, a planarization layer 430, a common electrode CE, a pixel electrode AE, and A semiconductor device may be included.

The driving thin film transistor T2 includes a gate electrode GE, a semiconductor layer SCL, an ohmic contact layer OCL, a source electrode SE, and a drain electrode DE.

The driving thin film transistor is a driving element and may be electrically connected to the semiconductor element to drive the semiconductor element.

The gate electrode GE may be formed together with the gate line. The gate electrode GE may be covered with the gate insulating layer 440 .

The gate insulating layer 440 may be formed of a single layer or a plurality of layers made of an inorganic material, and may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like.

The semiconductor layer SCL may be disposed in a preset pattern (or island) shape on the gate insulating layer 440 to overlap the gate electrode GE. The semiconductor layer SCL may be made of a semiconductor material made of any one of amorphous silicon, polycrystalline silicon, oxide, and organic material, but is not limited thereto.

The ohmic contact layer OCL may be disposed on the semiconductor layer SCL in a preset pattern (or island) shape. The ohmic contact layer PCL may be for ohmic contact between the semiconductor layer SCL and the source/drain electrodes SE and DE.

The source electrode SE is formed on the other side of the ohmic contact layer OCL to overlap one side of the semiconductor layer SCL.

The drain electrode DE may be formed on the other side of the ohmic contact layer OCL to be spaced apart from the source electrode SE while overlapping the other side of the semiconductor layer SCL. The drain electrode DE may be formed together with the source electrode SE.

The planarization layer may be disposed on the entire surface of the second panel substrate 410 . A driving thin film transistor T2 may be disposed inside the planarization layer. The planarization layer according to one embodiment may include an organic material such as benzocyclobutene or photo acryl, but is not limited thereto.

The groove 450 is a predetermined light emitting area, and a semiconductor device may be disposed therein. Here, the light emitting area may be defined as an area other than the circuit area of the display device.

The groove 450 may be concavely formed in the planarization layer 430, but is not limited thereto.

A semiconductor device may be disposed in the groove 450 . The first and second electrodes of the semiconductor device may be connected to a circuit (not shown) of the display device.

The semiconductor device may be adhered to the groove 450 through the adhesive layer 420 . Here, the adhesive layer 420 may be the second bonding layer, but is not limited thereto.

The second electrode 152 of the semiconductor device may be electrically connected to the source electrode SE of the driving thin film transistor T2 through the pixel electrode AE. Also, the first electrode 151 of the semiconductor device may be connected to the common power line CL through the common electrode CE.

The first and second electrodes 151 and 152 may be stepped from each other, and the electrode 151 at a relatively low position among the first and second electrodes 151 and 152 has the same level as the upper surface of the planarization layer 430. It can be located on a horizontal line. However, it is not limited thereto.

The pixel electrode AE may electrically connect the source electrode SE of the driving thin film transistor T2 and the second electrode of the semiconductor device.

The common electrode CE may electrically connect the common power line CL and the first electrode of the semiconductor device.

Each of the pixel electrode AE and the common electrode CE may include a transparent conductive material. The transparent conductive material may include, but is not limited to, materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The display device according to an embodiment of the present invention has SD (Standard Definition) resolution (760 × 480), HD (High Definition) resolution (1180 × 720), FHD (Full HD) resolution (1920 × 1080), UH (Ultra HD) level resolution (3480 × 2160) or UHD level or higher resolution (eg, 4K (K = 1000), 8K, etc.) may be implemented. In this case, a plurality of semiconductor devices according to the embodiment may be arranged and connected according to the resolution.

In addition, the display device may be an electronic display board or TV having a diagonal size of 100 inches or more, and pixels may be implemented as light emitting diodes (LEDs). Therefore, it can be provided with low power consumption, low maintenance cost, long lifespan, and a high-brightness self-luminous display.

Since the embodiment implements video and images using a semiconductor device, it has advantages of excellent color purity and color reproduction.

Since the embodiment implements videos and images using a light emitting device package having excellent linearity, a clear large display of 100 inches or more can be implemented.

The embodiment can implement a large display device of 100 inches or more with high resolution at low cost.

The semiconductor device according to the embodiment may further include an optical member such as a light guide plate, a prism sheet, or a diffusion sheet to function as a backlight unit. In addition, the semiconductor device of the embodiment may be further applied to a display device, a lighting device, and a pointing device.

In this case, the display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter. The bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit.

A reflector is disposed on the bottom cover, and the light emitting module emits light. The light guide plate is disposed in front of the reflector to guide light emitted from the light emitting module forward, and the optical sheet includes a prism sheet and is disposed in front of the light guide plate. A display panel is disposed in front of the optical sheet, an image signal output circuit supplies image signals to the display panel, and a color filter is disposed in front of the display panel.

Further, the lighting device may include a light source module including a substrate and the semiconductor device of the embodiment, a heat dissipation unit dissipating heat from the light source module, and a power supply unit that processes or converts an electrical signal received from the outside and provides it to the light source module. . Furthermore, the lighting device may include a lamp, a head lamp, or a street lamp.

Also, the camera flash of the mobile terminal may include a light source module including the semiconductor device according to the embodiment.

Although the above has been described with reference to the embodiments, this is only an example and does not limit the present invention, and those skilled in the art to which the present invention belongs will not deviate from the essential characteristics of the present embodiment. It will be appreciated that various variations and applications are possible. For example, each component specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the present invention as defined in the appended claims.

Claims (20)

Board;
a plurality of semiconductor structures disposed on the substrate; and
Including an insulating layer disposed on the plurality of semiconductor structures,
The substrate includes a groove disposed between the plurality of semiconductor structures,
The insulating layer includes a first insulating layer disposed on the plurality of semiconductor structures, and a second insulating layer disposed in the groove,
The first insulating layer and the second insulating layer are connected to each other,
The semiconductor structure,
A first conductivity type semiconductor layer, a second conductivity type semiconductor layer, an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a sacrificial layer disposed between the first conductivity type semiconductor layer and the substrate contains layers,
The first insulating layer covers side surfaces of the first conductivity-type semiconductor layer, the second conductivity-type semiconductor layer, the active layer, and the sacrificial layer.
According to claim 1,
When the plurality of structures and the substrate are separated, the first insulating layer is separated from the second insulating layer.
According to claim 2,
a first electrode electrically connected to the first conductivity-type semiconductor layer through the first insulating layer; and
A semiconductor element array including a second electrode electrically connected to the second conductive semiconductor layer through the first insulating layer.
According to claim 3,
The upper surface of the semiconductor structure includes a first upper surface on which the first electrode is disposed, a second upper surface on which the second electrode is disposed, and an inclined surface disposed between the first upper surface and the second upper surface, ,
A difference between a height from the bottom surface of the semiconductor structure to the second upper surface and a height from the bottom surface of the semiconductor structure to the first upper surface is greater than 0 and less than 2 μm.
According to claim 4,
A first angle between the inclined plane and the horizontal plane is smaller than a second angle between the side surface of the semiconductor structure and the horizontal plane.
According to claim 5,
The first angle is 20° to 50°, and the second angle is 70° to 90°.
According to claim 1,
The semiconductor structure has a long side surface and a short side surface on a plane,
The long side surface is a semiconductor device array smaller than 100㎛.
According to claim 4,
The semiconductor device array of claim 1 , wherein a width of the inclined surface decreases from the first upper surface to the second upper surface.
delete According to claim 1,
The semiconductor structure includes a bonding layer disposed between the first conductivity-type semiconductor layer and the sacrificial layer.
Forming a sacrificial layer and a semiconductor structure layer on a first substrate;
Cutting the semiconductor structure layer into a plurality of semiconductor structures;
Forming an insulating layer on the plurality of semiconductor structures; and
Including the step of selectively separating the plurality of semiconductor structures,
In the cutting, a groove is formed on the first substrate when the semiconductor structure layer is cut,
Forming the insulating layer may include forming an insulating layer on a side surface of the semiconductor structure, a side surface of the sacrificial layer, and an inside of the groove;
In the separating step, when the plurality of semiconductor structures and the substrate are separated, an insulating layer formed on the semiconductor structure is separated from an insulating layer formed inside the groove.
delete delete delete According to claim 11,
A method of manufacturing a semiconductor element array in which the semiconductor structure is selectively separated by irradiating a laser onto the rear surface of the first substrate.
According to claim 15,
The sacrificial layer is separated by absorbing the laser.
According to claim 11,
The semiconductor structure
A method of manufacturing a semiconductor element array comprising a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer.
According to claim 17,
The active layer is a semiconductor element array manufacturing method for emitting light in the red wavelength range.
According to claim 11,
The sidewall of the groove has the same inclination angle as the sidewall of the plurality of semiconductor structures.
According to claim 17,
Between the step of forming the semiconductor structure layer and the step of cutting,
Forming a step in the semiconductor structure layer,
In the step of forming the step, the semiconductor structure layer is etched at regular intervals to expose the first conductivity-type semiconductor layer.

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