KR102462718B1 - Semiconductor device - Google Patents

Abstract

In an embodiment, a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer, wherein the semiconductor structure includes a first upper surface to which the first semiconductor layer is exposed, a second upper surface on which the second semiconductor layer is disposed, and the an inclined surface connecting the first upper surface and the second upper surface, and a groove formed between the first upper surface and the inclined surface, wherein the depth of the groove is between the first upper surface and the second upper surface Disclosed is a semiconductor device that is 30% or less of the vertical distance of .

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The embodiment relates to a semiconductor device.

A light emitting diode (LED) is one of light emitting devices that emits light when an electric current is applied thereto. Light-emitting diodes can emit high-efficiency light with a low voltage, and thus have an excellent energy-saving effect. Recently, the luminance problem of the light emitting diode has been greatly improved, and it is applied to various devices such as a backlight unit of a liquid crystal display device, an electric sign board, a display device, and a home appliance.

A semiconductor device containing a compound such as GaN or AlGaN has many advantages, such as having a wide and easily adjustable band gap energy, and thus can be used in various ways as a light emitting device, a light receiving device, and various diodes.

In particular, light emitting devices such as light emitting diodes or laser diodes using group 3-5 or group 2-6 compound semiconductor materials of semiconductors have developed red, green, and Various colors such as blue and ultraviolet light can be realized, and efficient white light can be realized by using fluorescent materials or combining colors. , safety, and environmental friendliness.

Recently, research has been conducted on a technology of manufacturing a light emitting diode in a micro size and using it as a pixel of a display. However, there is a problem that the light emitting diode is small to a micro size and is weak against external impact.

The embodiment provides a semiconductor device resistant to external impact.

In addition, a semiconductor device having improved light output is provided.

The problem to be solved in the embodiment is not limited thereto, and it will be said that the purpose or effect that can be grasped from the solving means or embodiment of the problem described below is also included.

A semiconductor device according to an aspect of the present invention includes: a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer, wherein the semiconductor structure includes a first upper surface to which the first semiconductor layer is exposed, a second upper surface on which the second semiconductor layer is disposed, and the an inclined surface connecting the first upper surface and the second upper surface, and a groove formed between the first upper surface and the inclined surface, wherein the depth of the groove is between the first upper surface and the second upper surface is less than 30% of the vertical distance of

The second semiconductor layer includes a first sub-semiconductor layer exposed to the first upper surface, and a second sub-semiconductor layer disposed on the first sub-semiconductor layer, wherein the first sub-semiconductor layer and the second The sub-semiconductor layer may have an etch rate difference of 30% or less under the same etch condition.

According to an embodiment, the semiconductor device may be robust against external impact. Accordingly, it is possible to solve the problem that the semiconductor device is damaged in the transfer process.

In addition, a semiconductor device having improved light output can be manufactured.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;
2 is a plan view of a semiconductor device according to an embodiment of the present invention;
3a to 3b are diagrams for explaining the reason why the grooves of FIG. 1 occur;
4 is a view for explaining the reason why the semiconductor device is damaged by the groove of FIG. 1;
5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;
6A to 6E are views showing a method of manufacturing a semiconductor device array according to an embodiment of the present invention;
7A to 7E are views showing a method of transferring a semiconductor device according to an embodiment of the present invention;
8 is a conceptual diagram of a display device to which a semiconductor device is transferred, according to an exemplary embodiment.

The present embodiments may be modified in other forms or various embodiments may be combined with each other, and the scope of the present invention is not limited to each of the embodiments described below.

Even if a matter described in a specific embodiment is not described in another embodiment, it may be understood as a description related to another embodiment unless a description contradicts or contradicts the matter in another embodiment.

For example, if the features of configuration A in one embodiment are described and features of configuration B in another embodiment are described, the opposite or contradictory descriptions are not explicitly described in the embodiment in which configuration A and configuration B are combined. Unless otherwise stated, it should be understood as belonging to the scope of the present invention.

In the description of the embodiment, in the case where one element is described as being formed on "on or under" of another element, on (above) or below (on) or under) includes both elements in which two elements are in direct contact with each other or one or more other elements are disposed between the two elements indirectly. In addition, when expressed as "up (up) or down (on or under)", it may include the meaning of not only an upward direction but also a downward direction based on one element.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art to which the present invention pertains can easily implement them.

In addition, the semiconductor device package according to the present embodiment may include a micro-sized or nano-sized semiconductor device. Here, the small semiconductor device may refer to a structural size of the semiconductor device. In addition, the small semiconductor device may have a size of 1 μm to 100 μm. In addition, the semiconductor device according to the embodiment may have a size of 30 μm to 60 μm, but is not limited thereto. In addition, the technical features or aspects of the embodiment may be applied to a semiconductor device on a smaller scale.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention, and FIGS. 3A to 3B explain why the grooves of FIG. 1 occur FIG. 4 is a view for explaining the reason why the semiconductor device is damaged by the groove of FIG. 1 .

1 and 2 , the semiconductor device according to the embodiment includes a first semiconductor layer 12 , a second semiconductor layer 14 , and a space between the first semiconductor layer 12 and the second semiconductor layer 14 . A semiconductor structure 11 including the disposed active layer 13 , a first electrode 15 electrically connected to the first semiconductor layer 12 , and a second electrode electrically connected to the second semiconductor layer 14 . (16).

The active layer 13 may generate light in any one or more wavelength bands of blue, green, and red wavelengths. That is, the semiconductor device may emit various visible light.

The insulating layer 18 is disposed on the upper surface S1 and the side surfaces S2, S3, S4, and S5 of the semiconductor structure 11, the first hole H1 through which the first electrode 15 is exposed, and the second A second hole H2 through which the second electrode 16 is exposed may be included. The insulating layer 18 may include a material such as SiO ₂ , SiNx, TiO ₂ , polyimide, or resin.

The upper surface S1 of the semiconductor structure includes a first upper surface S11 where the first semiconductor layer 12 is exposed, a second upper surface S13 on which the second semiconductor layer 14 is disposed, and a first upper surface It may include an inclined surface S12 connecting the (S11) and the second upper surface (S13).

The area of the first upper surface S11 may be 30% to 110% of the area of the second upper surface S13 . For example, the area of the first upper surface S11 may be 40% to 110% of the area of the second upper surface S13 .

Since the semiconductor device according to the embodiment is a micro semiconductor device having a small size, the mesa-etched area may be relatively large even if the minimum area of the first electrode 15 is secured. Accordingly, when the area of the first upper surface S11 is 30% or more, the first electrode 15 is widened, thereby reducing the ohmic resistance. Accordingly, the operating voltage can be reduced and the light output can be improved.

A first vertical height d1 from the bottom surface B1 of the semiconductor structure 11 to the second upper surface S13 and from the bottom surface B1 to the first upper surface S11 of the semiconductor structure 140 A ratio (d1:d2) of the second vertical height d2 may be 1:0.6 to 1:0.95. When the height ratio (d1: d2) is less than 1:0.6, the step difference becomes large, and the defect rate during the transfer process may increase. 141) may not be exposed.

The first vertical height d1 may be 5 μm to 8 μm. That is, the first vertical height d1 may be the entire thickness of the semiconductor structure 140 . The second vertical height d2 may be 3.0 μm to 7.6 μm. In this case, the difference d3 between the first vertical height d1 and the second vertical height d2 may be 350 nm or more and 2.0 μm or less. When the height difference d3 is greater than 2.0 μm, distortion occurs during the transfer of the semiconductor device, so that it is difficult to transfer the semiconductor device to a desired position. Also, when the height difference d3 is less than 350 nm, the first conductivity type semiconductor layer 121 may not be partially exposed.

When the difference d3 between the first vertical height d1 and the second vertical height d2 is 1.0 μm or less, the upper surface of the semiconductor structure is almost flat, so that transfer becomes easier and cracks can be suppressed. For example, the difference d3 between the first vertical height d1 and the second vertical height d2 may be 0.6 μm±0.2 μm, but is not necessarily limited thereto.

The first angle θ2 between the inclined surface S12 and the virtual horizontal plane may be 20° to 80° or 20° to 50°. When the first angle θ2 is less than 20°, the area of the second upper surface S13 may be reduced, and thus light output may be reduced. In addition, when the first angle θ2 is greater than 80°, the inclination angle may be increased, thereby increasing the risk of damage due to an external impact.

In addition, the second angle θ1 between the side surfaces S2 , S3 , S4 , and S5 of the semiconductor structure 140 with the horizontal plane may be 70° to 90°. When the second angle θ1 is less than 70°, the area of the second upper surface S13 may be reduced, and thus light output may be reduced. In this case, the first angle θ2 may be smaller than the second angle θ1 . In this case, since the inclined surface S12 is gentle, the risk of cracking due to external impact may be reduced.

At this time, when the side surfaces S2, S3, S4, and S5 of the semiconductor structure 140 are all inclined, the width of the inclined surface S12 (the width in the Y-axis direction) is from the first upper surface S11 to the second upper surface S13. ), it may become narrower in the direction of

The first semiconductor layer 12 may include a plurality of sub-semiconductor layers 12a and 12b. The plurality of sub-semiconductor layers 12a and 12b may include various semiconductor layers for improving epi-crystallization and/or light extraction efficiency. Alternatively, a semiconductor layer necessary for epitaxial growth may be included. The number of sub-semiconductor layers is not limited.

Exemplarily, the first semiconductor layer 12 includes a first sub-semiconductor layer 12a on which the first electrode 15 is disposed and a second sub-semiconductor layer 12a disposed between the first sub-semiconductor layer 12a and the active layer 13 . layer 12b.

The first sub-semiconductor layer 12a may be exposed by mesa etching. A plurality of sub-semiconductor layers may be further disposed under the first sub-semiconductor layer 12a.

The semiconductor structure 11 may include a groove 17 formed between the first upper surface S11 and the inclined surface S12 .

The groove 17 may be formed by a difference in etching rates of the semiconductor layers. The depth d4 of the groove 17 may be 30% or less of the vertical distance (etch depth, d3 ) between the first upper surface S11 and the second upper surface S13 . When the depth d4 of the groove 17 is greater than 30% of the vertical distance d3, a crack may occur in the groove 17 during the transfer process. Therefore, it is necessary to control the depth d4 of the groove 17 to be 30% or less of the vertical distance d3 between the first upper surface S11 and the second upper surface S13. In addition, when the depth d4 of the groove 17 is controlled to be 10% or less of the vertical distance d3 between the first upper surface S11 and the second upper surface S13, the semiconductor device becomes more resistant to external impact. can

The depth d4 of the groove 17 may be adjusted by controlling the etching rate of the sub-semiconductor layers 12a and 12b. For example, the difference in the etching rate of the sub-semiconductor layers 12a and 12b may be controlled to be 30% or less. If the etch rates of the sub-semiconductor layers 12a and 12b are the same, the groove 17 may not be formed.

3A and 3B , a portion of the semiconductor structure 11 may be mesa-etched to expose the first sub-semiconductor layer 12a to form the first electrode 15 . The first sub-semiconductor layer 12a may have a relatively low resistance and thus a low contact resistance with the first electrode 15 .

The second sub-semiconductor layer 12b may be a layer disposed between the active layer 13 and the first sub-semiconductor layer 12a. Exemplarily, the first sub-semiconductor layer 12a may be a contact layer in contact with the N-type ohmic electrode, and the second sub-semiconductor layer 12b may be an N-type semiconductor layer, but is not limited thereto.

The first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b may include the same dopant. Exemplarily, the first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b may include an N-type dopant, but is not limited thereto. For example, the first sub-semiconductor layer 12a may not include a dopant.

The first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b may have different compositions or different composition ratios. For example, when the semiconductor device is a red device, the first sub-semiconductor layer 12a may be a layer including GaAs, and the second sub-semiconductor layer 12b may be a semiconductor layer including AlInP, but is not limited thereto.

Referring to FIG. 3B , a mask 19 may be formed in a region not to be etched and the plasma E1 may be irradiated. At this time, the first upper surface S11 of the semiconductor structure 11 is irradiated with the etching plasma E1 almost vertically, but the boundary region RE1 between the first upper surface S11 and the inclined surface S12 is the etching plasma ( E1, E2) may be scattered. That is, since the plasma E1 irradiated vertically and the plasma E2 refracted by hitting the inclined surface S12 are simultaneously irradiated to the boundary region RE1, the plasma may be concentrated.

Accordingly, before the first sub-semiconductor layer 12a is completely removed, the first sub-semiconductor layer 12a may be already removed in the region RE1 close to the inclined surface S12 . On the other hand, the first sub-semiconductor layer 12c may still remain on a part of the first upper surface S11 .

Referring to FIG. 3C , when etching plasma is irradiated to remove the remaining first sub-semiconductor layer 12c, the second sub-semiconductor layer 12b exposed to the boundary region RE1 is etched to form a groove 17 . can be formed. In this case, if the etching rate of the second sub-semiconductor layer 12b is higher than the etching rate of the first sub-semiconductor layer 12a, the depth d4 of the groove 17 may be increased.

In the boundary region RE1 between the first upper surface S11 and the inclined surface S12 , plasma is concentrated and the etching rate of the second sub-semiconductor layer 12b is high, so that the remaining first sub-semiconductor layer 12c is completely removed. The groove 17 can be formed very deep before being removed.

Referring to FIG. 4 , the micro-semiconductor device may be selectively transferred to another substrate through a transfer process. For example, in order to form a pixel of the display, the micro-semiconductor device may be separated from the growth substrate by the transfer device 210 and then transferred to the substrate of the display.

In this process, a physical impact may be applied to the micro-semiconductor device, and a crack C1 may be generated in the groove 17 by the applied external stress. Accordingly, a problem may occur in which some pixels of the display malfunction.

Therefore, it may be important to control the depth of the groove 17 in the semiconductor device as it is a small chip. In the case of a general visible light semiconductor device, since the size of the chip is relatively large, such a groove may be ignored.

Referring back to FIGS. 1 and 2 , the difference in etch rate between the first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b may be 30% or less during etching under the same conditions. The same condition may be defined as maintaining the same various control factors, such as an etching source, temperature, and voltage, which can control the etching rate in the sputtering device.

When the difference in the etching rate is 30% or less, the depth of the groove 17 formed in the second sub-semiconductor layer 12b while removing the first sub-semiconductor layer 12a remaining on the first upper surface S11 is first It can be controlled within 30% of the vertical height d3 between the upper surface S11 and the second upper surface S13.

The etching rate of the semiconductor layer may be controlled by changing the composition of the semiconductor layer. For example, InP may have a slower etch rate than GaAs. In addition, as the amount of a specific factor such as indium (In) increases, the etching rate may be relatively slow. Exemplarily, in the case of the same InP composition, the etching rate may be relatively slow as the composition of indium increases.

When the first sub-semiconductor layer 12a includes GaAs and the second sub-semiconductor layer 12b includes AlInP, the etch rate of GaAs is relatively fast, so that the groove 17 can be formed deeper. In this case, when indium is added to the first sub-semiconductor layer 12a or when the first sub-semiconductor layer 12a is formed of AlInP, the depth of the groove 17 may be reduced.

If the first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b have the same composition, the depth of the groove 17 may be relatively small. For example, since both the first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b are formed of AlInP, the etching rate may be controlled to be the same. However, even in this case, if the plasma is concentrated on the inclined surface S12, the groove 17 may be formed near the inclined surface.

At this time, when the indium composition included in the first sub-semiconductor layer 12a is controlled to be greater than the indium composition of the second sub-semiconductor layer 12b, the etching rate of the first sub-semiconductor layer 12a is relatively low, so 17) can be controlled to be smaller. Accordingly, the depth of the groove 17 may be controlled by controlling the composition of the etch rate adjusting factor (eg, indium) within the limit of maintaining optical and/or electrical performance.

That is, when the etching rate of the first sub-semiconductor layer 12a is slower than the etching rate of the second sub-semiconductor layer 12b, the size of the groove 17 can be controlled to be smaller. In addition, when the first electrode 15 is disposed on the sub-semiconductor layer disposed closest to the lower portion of the active layer 13 , the difference in the etch rate between the sub-semiconductor layer and the active layer 13 may be controlled.

5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

The semiconductor device according to the embodiment includes a sacrificial layer 120 , a bonding layer 130 disposed on the sacrificial layer 120 , an intermediate layer 170 disposed on the bonding layer 130 , and an intermediate layer 170 disposed on the intermediate layer 170 . A first conductivity type semiconductor layer 141 , a first clad layer 144 disposed on the first conductivity type semiconductor layer, an active layer 142 disposed on the first clad layer 144 , disposed on the active layer A second conductivity-type semiconductor layer 143 to be formed, a first electrode 151 electrically connected to the first conductivity-type semiconductor layer, a second electrode 152 electrically connected to the second conductivity-type semiconductor layer, and a sacrifice The insulating layer 160 surrounding the layer 120 , the bonding layer 130 , the first conductivity type semiconductor layer 141 , the first clad layer 144 , the active layer 142 , and the second conductivity type semiconductor layer 142 . may include.

The sacrificial layer 120 may be a layer disposed at the bottom of the semiconductor device according to the embodiment. That is, the sacrificial layer 120 may be an outermost layer in the 1-2 direction (X ₂ axis direction). The sacrificial layer 120 may be disposed on a substrate (not shown).

The maximum width W ₁ in the second direction (Y-axis direction) of the sacrificial layer 120 may be 30 μm to 60 μm.

Here, the first direction includes a 1-1 direction and a 1-2 direction in a thickness direction of the semiconductor structure 140 . The 1-1 direction is a direction from the first conductivity type semiconductor layer 121 toward the second conductivity type semiconductor layer 123 among the thickness directions of the semiconductor structure 140 . In addition, the 1-2 direction is a direction from the second conductivity type semiconductor layer 123 toward the first conductivity type semiconductor layer 121 among the thickness directions of the semiconductor structure 140 . Also, here, the second direction (Y-axis direction) may be a direction perpendicular to the first direction (X-axis direction). In addition, the second direction (Y-axis direction) includes a 2-1 direction (Y1-axis direction) and a 2-2 direction (Y2-axis direction).

The sacrificial layer 120 may be a layer left while transferring the semiconductor device to the display device. For example, when the semiconductor device is transferred to the display device, the sacrificial layer 120 may be partially separated by a laser irradiated during transfer, and the other portion may be left. In this case, the sacrificial layer 120 may include a material separable at the wavelength of the irradiated laser. In addition, the wavelength of the laser may be any one of 266 nm, 532 nm, and 1064 nm, but is not limited thereto.

The sacrificial layer 120 may include oxide or nitride. However, the present invention is not limited thereto. For example, the sacrificial layer 120 may include an oxide-based material as a material with little deformation occurring during epitaxial growth.

The sacrificial layer 120 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and indium gallium tin oxide (IGTO). ), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx , NiO, RuOx/ITO, Ni/IrOx/Au, or Ni/IrOx/Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt, It may include at least one of Au and Hf.

The sacrificial layer 120 may have a thickness d ₁ of 20 nm or more in the first direction (X-axis direction). Preferably, the sacrificial layer 120 may have a thickness d ₁ of 40 nm or more in the first direction (X-axis direction).

The sacrificial layer 120 may be formed by E-beam evaporator, thermal evaporator, MOCVD (Metal Organic Chemical Vapor Deposition), sputtering, and PLD (Pulsed Laser Deposition) methods. , but is not limited thereto.

The bonding layer 130 may be disposed on the sacrificial layer 120 . The bonding layer 130 may include a material such as SiO ₂ , SiNx, TiO ₂ , polyimide, or resin.

The thickness d ₂ of the bonding layer 130 may be 30 nm to 1 μm. However, the present invention is not limited thereto. Here, the thickness may be a length in the X-axis direction. The bonding layer 130 may be annealed to bond the sacrificial layer 120 and the intermediate layer 170 to each other. At this time, exfoliation may occur as hydrogen ions in the bonding layer 130 are discharged. Accordingly, the bonding layer 130 may have a surface roughness of 1 nm or less. With this configuration, the separation layer and the bonding layer can be easily bonded. The arrangement positions of the bonding layer 130 and the sacrificial layer 120 may be exchanged with each other.

The intermediate layer 170 may be disposed on the bonding layer 130 . The intermediate layer 170 may include GaAs. The intermediate layer 170 may be coupled to the sacrificial layer 120 through the bonding layer 130 .

The semiconductor structure 140 may be disposed on the intermediate layer 170 . The semiconductor structure 140 includes a first conductivity-type semiconductor layer 141 disposed on the intermediate layer 170 , a first clad layer 144 disposed on the first conductivity-type semiconductor layer, and the first clad layer 144 . may include an active layer 142 disposed on the , and a second conductivity type semiconductor layer 143 disposed on the active layer 142 .

The first conductivity type semiconductor layer 141 may be disposed on the intermediate layer 170 . The thickness of the first conductivity type semiconductor layer 141 may be 1.8 μm to 2.2 μm. However, the present invention is not limited thereto.

The first conductivity-type semiconductor layer 141 may be implemented as a compound semiconductor of group III-V or group II-VI, and may be doped with a first dopant. The first conductivity type first semiconductor layer 112 is InxAlyGa1-x-yP (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or InxAlyGa1-x-yN (0≤x≤1) , 0≤y≤1, 0≤x+y≤1) may include a semiconductor material having a composition formula.

In addition, the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te. When the first dopant is an n-type dopant, the first conductivity-type semiconductor layer 141 doped with the first dopant may be an n-type semiconductor layer.

The first conductivity type semiconductor layer 141 may include at least one of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

The first conductivity type semiconductor layer 141 may be formed using a method such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto. .

The first clad layer 144 may be disposed on the first conductivity type semiconductor layer 141 . The first clad layer 144 may be disposed between the first conductivity-type semiconductor layer 141 and the active layer 142 . The first clad layer 144 may include a plurality of layers. The first clad layer 144 may include an AlInP-based layer/AlInGaP-based layer.

The thickness d ₅ of the first cladding layer 144 may be 0.45 μm to 0.55 μm. However, the present invention is not limited thereto.

According to an embodiment, when both the first conductivity-type semiconductor layer 141 and the first clad layer 144 are made of AlInP-based material, the etch rate becomes the same, so that a groove is formed between the first upper surface S11 and the interface S12. (17) can be suppressed from occurring. In this case, when the amount of indium included in the first conductivity-type semiconductor layer 141 is controlled to be higher than the amount of indium included in the first cladding layer 144 , the depth of the groove 17 may be controlled to be smaller.

The active layer 142 may be disposed on the first clad layer 144 . The active layer 142 may be disposed between the first conductivity type semiconductor layer 141 and the second conductivity type semiconductor layer 143 . The active layer 142 is a layer in which electrons (or holes) injected through the first conductivity type semiconductor layer 141 and holes (or electrons) injected through the second conductivity type semiconductor layer 143 meet. The active layer 142 may transition to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.

The active layer 142 may have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the active layer 142 may have a structure. ) structure is not limited thereto.

The active layer 142 may be formed of a pair structure of any one or more of GaInP/AlGaInP, GaP/AlGaP, InGaP/AlGaP, InGaN/GaN, InGaN/InGaN, GaN/AlGaN, InAlGaN/GaN, GaAs/AlGaAs, InGaAs/AlGaAs. However, the present invention is not limited thereto.

The thickness d ₆ of the active layer 142 may be 0.54 μm to 0.66 μm. However, the present invention is not limited thereto.

As electrons are cooled in the first cladding layer 144 , the active layer 142 may generate more radiation recombination.

The second conductivity type semiconductor layer 143 may be disposed on the active layer 142 . The second conductivity type semiconductor layer 143 may include a 2-1 conductivity type semiconductor layer 143a and a 2-2 conductivity type semiconductor layer 143b.

The 2-1-th conductivity type semiconductor layer 143a may be disposed on the active layer 142 . The 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.

The 2-1-th conductivity type semiconductor layer 143a may include TSBR and P-AllnP. The thickness d ₇ of the 2-1-th conductivity type semiconductor layer 143a may be 0.57 μm to 0.70 μm. However, the present invention is not limited thereto.

The 2-1-th conductivity type semiconductor layer 143a may be implemented with a compound semiconductor of group III-V, group II-VI, or the like. A second dopant may be doped into the 2-1-th conductivity type semiconductor layer 143a.

The 2-1-th conductivity type semiconductor layer 143a is InxAlyGa1-x-yP (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or InxAlyGa1-x-yN (0≤x≤1) , 0≤y≤1, 0≤x+y≤1) may include a semiconductor material having a composition formula. When the second conductivity-type semiconductor layer 143 is a p-type semiconductor layer, Mg, Zn, Ca, Sr, Ba, or the like may be included as a p-type dopant.

The 2-1-th conductivity-type semiconductor layer 143a is doped with a second dopant, and the 2-1-th conductivity-type semiconductor layer 143a may be a p-type semiconductor layer.

The 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a. The 2-2 conductivity type semiconductor layer 143b may include a p-type GaP-based layer.

The 2-2 conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer/InxGa1-xP layer (where 0≤x≤1).

For example, the 2-2 conductivity type semiconductor layer 143b may be doped with Mg having a concentration of about ^10X10-18 , but is not limited thereto.

In addition, the 2-2 conductivity type semiconductor layer 143b may be formed of a plurality of layers and only some layers may be doped with Mg.

The thickness d ₈ of the second-second conductivity type semiconductor layer 143b may be 0.9 μm to 1.1 μm. However, the present invention is not limited thereto.

The first electrode 151 may be disposed on the first conductivity type semiconductor layer 141 . The first electrode 151 may be electrically connected to the first conductivity-type semiconductor layer 141 .

The first electrode 151 may be disposed on a portion of the upper surface of the first conductivity-type semiconductor layer 141 on which the mesa etching is performed. Accordingly, the first electrode 151 may be disposed below the second electrode 152 disposed on the upper surface of the second conductivity type semiconductor layer 143 .

The shortest width W ₂ in the 2-2 direction (Y ₂ axis direction) between the edge and the second electrode 152 in the 2-2 direction (Y ₂ axis direction) of the insulating layer 160 is 2.5 μm to It may be 3.5 μm. Similarly, the shortest width W ₆ in the 2-1 direction (Y ₁ axis direction) between the edge and the first electrode 151 in the 2-1 direction (Y ₁ axis direction) of the insulating layer 160 is 2.5 μm to 3.5 μm. However, it is not limited to this length.

The first electrode 151 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and indium gallium tin (IGTO). oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, or Ni/IrOx/Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt , Au, may be formed including at least one of Hf, but is not limited to these materials.

For the first electrode 151 , any commonly used electrode formation method such as stuffing, coating, deposition, etc. may be applied.

As described above, the second electrode 152 may be disposed on the 2-2 conductivity type semiconductor layer 143b. The second electrode 152 may be electrically connected to the 2-2 conductive type semiconductor layer 143b.

The second electrode 152 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and indium gallium tin (IGTO). oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, or Ni/IrOx/Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt , Au, may be formed including at least one of Hf, but is not limited to these materials.

For the second electrode 152 , all of the commonly used electrode forming methods such as stuffing, coating, and deposition may be applied.

Also, the first electrode 151 may have a greater width in the second direction (Y-axis direction) than the second electrode 152 . However, it is not limited to this length.

The insulating layer 160 may cover the sacrificial layer 120 , the bonding layer 130 , and the semiconductor structure 140 . The insulating layer 160 may cover the side surface of the sacrificial layer 120 and the side surface of the bonding layer 130 . The insulating layer 160 may cover a portion of the upper surface of the first electrode 151 . With this configuration, the first electrode 151 may be electrically connected to the electrode or pad through the exposed upper surface, and current may be injected. Similarly, the second electrode 152 may include an exposed upper surface like the first electrode 151 . The insulating layer 160 may cover the bonding layer 130 and the sacrificial layer 120 so that the sacrificial layer 120 and the bonding layer 130 may not be exposed to the outside.

The insulating layer 160 may cover a portion of the upper surface of the first electrode 151 . Also, the insulating layer 160 may cover a portion of the upper surface of the second electrode 152 . A portion of the top surface of the first electrode 151 may be exposed. A portion of the top surface of the second electrode 152 may be exposed.

The exposed upper surface of the first electrode 151 and the exposed upper surface of the second electrode 152 may be circular, but are not limited thereto. In addition, the distance W ₄ in the second direction (Y-axis direction) between the center point of the exposed upper surface of the first electrode 151 and the center point of the upper surface of the second electrode 152 may be 20 μm to 30 μm. Here, the central point refers to a point that bisects the widths of the exposed first electrode and the exposed second electrode in the second direction (Y-axis direction).

The insulating layer 160 may electrically separate the first conductivity-type semiconductor layer 141 and the second conductivity-type semiconductor layer 143 in the semiconductor structure 140 . The insulating layer 160 may be formed by selecting at least one selected from the group consisting of SiO ₂ , SixOy, Si ₃ N ₄ , Si _x N _y , SiO _x N _y , Al ₂ O ₃ , TiO ₂ , AlN, etc. It is not limited to this.

6A to 6G are diagrams illustrating a method of manufacturing a semiconductor device array according to an embodiment of the present invention.

Referring to FIG. 6A , in the step of forming the first substrate, ions may be implanted into the donor substrate S first. The donor substrate S may include an ionic layer I. Due to the ion layer I, the donor substrate S may include an intermediate layer 170 disposed on one side and a first layer 171 disposed on the other side. The ions implanted into the donor substrate S may include hydrogen (H) ions, but are not limited thereto.

Referring to FIG. 6B , the sacrificial layer 120 may be disposed between the substrate 110 and the bonding layer 130 .

The substrate 110 may be a light-transmitting substrate including sapphire (Al ₂ O ₃ ), glass, or the like. Accordingly, the substrate 110 may transmit the laser light irradiated from the bottom. Accordingly, when the laser is lifted off, the sacrificial layer 120 may absorb the laser light.

A sacrificial layer 120 and a bonding layer 130 may be stacked on the substrate 110 . The order of the sacrificial layer 120 and the bonding layer 130 may be reversed.

The bonding layer 130 disposed on the substrate may be disposed to face the bonding layer 130 disposed on the donor substrate S. The bonding layer 130 disposed on the substrate and the bonding layer 130 disposed on the donor substrate S may include SiO ₂ , but are not limited thereto.

The bonding layer 130 disposed on the sacrificial layer 120 may be coupled to the bonding layer 130 disposed on the donor substrate S through O ₂ plasma treatment. However, the present invention is not limited thereto, and cutting may be performed using a material other than oxygen.

Accordingly, the sacrificial layer 120 is disposed on the substrate 110 , the bonding layer 130 is disposed on the sacrificial layer 120 , and the donor substrate S is disposed spaced apart on the bonding layer 130 . can

Referring to FIG. 6C , the ionic layer I of FIG. 6B may be removed by fluid jet cleaving, so that the first layer 171 may be separated from the intermediate layer 170 .

In this case, the first layer 171 separated from the donor substrate may be reused as a substrate. Therefore, it is possible to provide the effect of reducing the manufacturing cost and cost.

The forming of the semiconductor structure layer on the first substrate may include forming the semiconductor structure 140 on the intermediate layer 170 . The intermediate layer 170 may contact the semiconductor structure 140 . However, since the upper surface of the intermediate layer 170 has poor roughness due to voids generated by the ion implantation process, defects may occur during Red Epi deposition.

Accordingly, a planarization process may be performed on the upper surface of the intermediate layer 170 . For example, chemical mechanical planarization may be performed on the upper surface of the intermediate layer 170 , and the semiconductor structure 140 may be disposed on the upper surface of the intermediate layer 170 after planarization. With this configuration, the semiconductor structure 140 may have improved electrical characteristics.

The semiconductor structure 140 includes a first conductivity-type semiconductor layer 141 disposed on the intermediate layer 170 , a first clad layer 144 disposed on the first conductivity-type semiconductor layer, and the first clad layer 144 . may include an active layer 142 disposed on the , and a second conductivity type semiconductor layer 143 disposed on the active layer 142 . A specific configuration of the semiconductor structure 140 will be described later.

Referring to FIG. 6D , a primary etching process for exposing the first conductivity-type semiconductor layer 141 may be performed on the upper portion of the semiconductor structure 140 .

The primary etching may be performed by wet etching or dry etching, but is not limited thereto, and various methods may be applied. Before the first etching is performed, the second electrode 152 of FIG. 6E may be disposed on the second conductivity-type semiconductor layer 143 and patterned as shown in FIG. 6E . However, it is not limited to this method.

Referring to FIG. 6E , the forming of the electrode on the semiconductor structure may include forming the first electrode 151 and the second electrode 152 on the semiconductor structure 140 .

The second electrode 152 may be electrically connected to the 2-2 conductive type semiconductor layer 143b. The area of the lower surface of the second electrode 152 may be smaller than that of the upper surface of the second conductivity type semiconductor layer 143 . For example, the second electrode 152 may be spaced apart from the edge of the 2-2 conductivity type semiconductor layer 143b by 1 μm to 3 μm.

For the first electrode 151 and the second electrode 152 , all commonly used electrode forming methods such as stuffing, coating, and deposition may be applied. However, the present invention is not limited thereto.

In addition, as described above, the second electrode 152 is formed before the first etching, and the first electrode 151 is etched after the first etching to be disposed on the exposed upper surface of the first conductivity-type semiconductor layer 41 . can

The first electrode 151 and the second electrode 152 may be disposed at different positions from the substrate 110 . The first electrode 151 may be disposed on the first conductivity type semiconductor layer 141 . The second electrode 152 may be disposed on the second conductivity-type semiconductor layer 143 . Accordingly, the second electrode 152 may be disposed above the first electrode 151 .

Referring to FIG. 6F , in the step of cutting into a plurality of semiconductor structures, secondary etching may be performed up to the upper surface of the substrate 110 . The secondary etching may be performed by wet etching or dry etching, but is not limited thereto. In the semiconductor device, the second etching may be performed to a thickness greater than that of the first etching.

The semiconductor structure disposed on the substrate through the secondary etching may be isolated in the form of a plurality of chips. For example, two semiconductor structures may be disposed on the substrate 110 through secondary etching in FIG. 6F . The number of semiconductor structures may be variously set according to the size of the substrate and the size of the semiconductor structure. In this case, the step of separating the semiconductor structure and the step of forming the electrode may be in reverse order. That is, the semiconductor structure may be separated after forming the electrode first, or the electrode may be formed after the semiconductor structure is separated. In addition, an electrode may be formed after the semiconductor structure is first etched, and then the semiconductor structure may be separated.

In this case, the secondary etching may proceed to a partial region of the substrate 110 through the semiconductor structure. Accordingly, in the substrate 110 , a groove H1 disposed between the plurality of semiconductor structures may be formed. Since the groove H1 of the substrate is formed in the process of etching the semiconductor structure 140 , sidewalls of the groove H1 may have the same inclination angle as the side surfaces of the plurality of semiconductor structures 140 . However, the present invention is not limited thereto, and the groove H1 of the substrate may be formed by a separate etching process.

According to this configuration, it is possible to reliably remove the bonding layer 120 and/or the sacrificial layer 130 disposed between the plurality of semiconductor structures. The depth of the groove H1 is not particularly limited as long as it can remove the bonding layer 120 and/or the sacrificial layer 130 disposed between the semiconductor structures.

If the bonding layer and/or the sacrificial layer of the semiconductor structure are connected to each other, when one semiconductor structure is separated from the substrate, neighboring semiconductor structures may be affected.

For example, when only one semiconductor structure is separated from the substrate, a problem in that the sacrificial layer of the neighboring semiconductor structure is also separated from the substrate may occur.

Referring to FIG. 6G , in the forming of the insulating layer, the insulating layer 160 may be formed entirely on the plurality of semiconductor structures 140 and the grooves H1 . The insulating layer 160 may cover side surfaces of the sacrificial layer 120 , the bonding layer 130 , the intermediate layer 170 , and the semiconductor structure 140 .

The insulating layer 160 may cover up to a portion of the upper surface of the first electrode 151 . In addition, a portion of the upper surface of the first electrode 151 may be exposed. The exposed upper surface of the first electrode 151 may be electrically connected to an electrode pad, etc., so that current injection may be performed.

In addition, the insulating layer 160 may cover a portion of the top surface of the second electrode 152 . A portion of the top surface of the second electrode 152 may be exposed. Similar to the first electrode 151 , the exposed upper surface of the second electrode 152 may be electrically connected to an electrode pad or the like, so that current injection may be performed. In addition, a portion of the insulating layer 160 may be disposed on the upper surface of the substrate. The insulating layer 160 disposed between adjacent semiconductor chips may be disposed in contact with the substrate 110 .

Referring to FIG. 6G , the manufactured semiconductor device array may include a substrate 110 and a plurality of semiconductor devices 10 disposed on the substrate 110 . According to an embodiment, a plurality of semiconductor devices 10 may be disposed on the substrate 110 .

The plurality of semiconductor devices 10 include a first conductivity type semiconductor layer 144 , a second conductivity type semiconductor layer 143 , and between the first conductivity type semiconductor layer 144 and the second conductivity type semiconductor layer 143 . The semiconductor structure 140 including the active layer 142 disposed on the It may include a first electrode 151 connected to , and a second electrode 152 electrically connected to the second conductivity-type semiconductor layer 143 through the insulating layer 160 .

As described above, the substrate 110 may include a groove H1 disposed between the plurality of semiconductor structures 140 . The groove H1 may have a line shape, but is not limited thereto.

The insulating layer 160 may include a first insulating layer 161 disposed on the upper surface and side surfaces of the semiconductor structure 140 , and a second insulating layer 162 disposed in the groove H1 of the substrate 110 . have. In this case, the first insulating layer 161 and the second insulating layer 162 may be connected to each other.

The insulating layer 160 may entirely cover the plurality of semiconductor structures 140 , one surface of the substrate 110 , and the groove H1 of the substrate 110 .

The upper surface of the semiconductor structure 140 has a first upper surface S11 on which the first electrode 151 is disposed, a second upper surface S13 on which the second electrode 152 is disposed, and a first upper surface S1 on which the first upper surface S1 is disposed. and an inclined surface S12 disposed between the second upper surface S2 and the second upper surface S2.

At this time, the difference between the height d1 from the bottom surface of the semiconductor structure 140 to the second upper surface S13 and the height d2 from the bottom surface of the semiconductor structure 140 to the first upper surface S11 ( d3) may be greater than 0 and less than 2 μm.

When the height difference P3 between the first upper surface S11 and the second upper surface S13 is greater than 2 μm, the chip may be horizontally shifted during the transfer process. That is, as the step difference increases, it may be difficult for the chip to remain horizontal. The transfer process may refer to an operation of transferring a chip from a growth substrate to another substrate as shown in FIG. 3 .

The first angle θ ₁ between the inclined surface S12 and the horizontal plane may be smaller than the second angle θ ₂ between the side surface of the semiconductor structure 140 and the horizontal plane. The first angle θ ₁ between the inclined surface S12 and the virtual horizontal plane may be 20° to 50°. When the first angle θ ₁ is less than 20°, the area of the second upper surface S13 may be reduced, and thus light output may be reduced. In addition, when the first angle (θ ₁ ) is greater than 50°, the inclination angle is increased and the risk of damage due to an external impact may increase.

The second angle θ ₂ formed by the side surface of the semiconductor structure 120 with the horizontal plane may be greater than 70° and less than 90°. When the second angle θ ₂ is less than 70°, the area of the second upper surface S13 may be reduced, and thus light output may be reduced. When the second angle θ ₂ formed by all sides of the semiconductor structure 120 with the horizontal plane is less than 90°, the area of the inclined surface S12 increases from the first upper surface S11 to the second upper surface S13. can be narrowed.

7A to 7E are diagrams illustrating a method of transferring a semiconductor device according to an embodiment of the present invention.

7A to 7E , in the method of transferring a semiconductor device according to an exemplary embodiment, a semiconductor device including a plurality of semiconductor devices disposed on a substrate 110 is selectively irradiated with a laser to separate the semiconductor device from the substrate. and disposing the separated semiconductor device on the panel substrate. Here, the semiconductor device before transfer may include the configuration of FIGS. 1A to 1G as it is.

First, referring to FIG. 7A , the substrate 110 may be the same as the substrate 110 described with reference to FIGS. 1A to 1G . Also, as described above, a plurality of semiconductor devices may be disposed on the substrate 110 . For example, the plurality of semiconductor devices may include a first semiconductor device 10-1, a second semiconductor device 10-2, a third semiconductor device 10-3, and a fourth semiconductor device 10-4. have. However, the number is not limited thereto, and the semiconductor device may have various numbers.

Referring to FIG. 7B , at least one semiconductor device selected from among the plurality of semiconductor devices 10 - 1 , 10 - 2 , 10 - 3 and 10 - 4 may be separated into a growth substrate using the transfer mechanism 210 . . The transport mechanism 210 may include a first bonding layer 211 and a transport frame 212 disposed thereunder. For example, the transport frame 212 has a concave-convex structure, so that the semiconductor device and the first bonding layer 211 can be easily bonded. In this case, since the step difference of the semiconductor device according to the embodiment is smaller than 2 μm, it is possible to maintain a horizontal level during the transfer process.

Referring to FIG. 7C , when a laser is selectively irradiated to the rear surface of the semiconductor devices 10-1 and 10-3 to be separated, the sacrificial layers of the semiconductor devices 10-1 and 10-3 are decomposed and the substrate 110 is can be separated from Thereafter, when the transfer mechanism 210 is moved upward, the first semiconductor element 10 - 1 and the third semiconductor element 10 - 3 may be separated from the transfer mechanism 210 . In addition, coupling between the second bonding layer 310 and the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 may be formed.

As a method of separating the semiconductor device from the substrate 110 , laser lift-off (LLO) using a photon beam of a specific wavelength band may be applied. For example, the central wavelength of the irradiated laser may be 266 nm, 532 nm, or 1064 nm, but is not limited thereto.

In this case, the bonding layer 130 disposed between the semiconductor device and the substrate 110 may prevent physical damage between the semiconductor devices due to laser lift-off (LLO). The sacrificial layer may be separated from the semiconductor device by laser lift-off (LLO). For example, the sacrificial layer may be partially removed due to separation and the remaining sacrificial layer may be separated together with the bonding layer. Accordingly, in the semiconductor device, the sacrificial layer and the bonding layer disposed on the sacrificial layer, the semiconductor structure, and the first electrode and the second electrode may be separated by the substrate 110 .

In addition, the plurality of semiconductor devices separated by the substrate 110 may have a predetermined spacing from each other. As described above, the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from the growth substrate, and the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated. The second semiconductor device 10 - 2 and the fourth semiconductor device 10 - 4 having the same separation distance as the separation distance may be separated in the same manner. Accordingly, semiconductor devices having the same separation distance may be transferred to the display panel.

Referring to FIG. 7D , a selected semiconductor device may be disposed on the panel substrate 300 . For example, the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 may be disposed on the panel substrate 300 .

Specifically, the second bonding layer 310 may be disposed on the panel substrate 300 , and the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 are formed by the second bonding layer 310 . may be placed on the Accordingly, the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 may contact the second bonding layer 310 . Through this method, the efficiency of the transfer process may be improved by arranging semiconductor devices having spaced apart intervals on the panel substrate.

In addition, a laser may be irradiated to separate the first bonding layer 211 from the selected semiconductor device. For example, a laser may be irradiated onto the transfer mechanism 210 to physically separate the first bonding layer 211 from the selected semiconductor device. Exemplarily, the bonding layer 211 may lose its adhesive function when irradiated with a laser.

Referring to FIG. 7E , when the transport mechanism 210 is moved upward after laser irradiation, the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 may be separated from the transport mechanism 210 . have. In addition, coupling between the second bonding layer 310 and the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 may be formed.

8 is a conceptual diagram of a display device to which a semiconductor device is transferred, according to an exemplary embodiment.

Referring to FIG. 8 , in an embodiment, a display device including a semiconductor device includes a second panel substrate 410 , a driving thin film transistor T2 , a planarization layer 430 , a common electrode CE, a pixel electrode AE, and a semiconductor. It may include elements.

The driving thin film transistor T2 includes a gate electrode GE, a semiconductor layer SCL, an ohmic contact layer OCL, a source electrode SE, and a drain electrode DE.

The driving thin film transistor is a driving device and may be electrically connected to the semiconductor device to drive the semiconductor device.

The gate electrode GE may be formed together with the gate line. The gate electrode GE may be covered with a gate insulating layer 440 .

The gate insulating layer 440 may be formed of a single layer or a plurality of layers made of an inorganic material, and may be made of silicon oxide (SiOx), silicon nitride (SiNx), or the like.

The semiconductor layer SCL may be disposed in the form of a preset pattern (or island) on the gate insulating layer 440 to overlap the gate electrode GE. The semiconductor layer SCL may be made of a semiconductor material made of any one of amorphous silicon, polycrystalline silicon, oxide, and an organic material, but is not limited thereto.

The ohmic contact layer OCL may be disposed in a preset pattern (or island) shape on the semiconductor layer SCL. The ohmic contact layer PCL may be for ohmic contact between the semiconductor layer SCL and the source/drain electrodes SE and DE.

The source electrode SE is formed on the other side of the ohmic contact layer OCL to overlap one side of the semiconductor layer SCL.

The drain electrode DE may be formed on the other side of the ohmic contact layer OCL to be spaced apart from the source electrode SE while overlapping the other side of the semiconductor layer SCL. The drain electrode DE may be formed together with the source electrode SE.

The planarization layer may be disposed over the entire surface of the second panel substrate 410 . A driving thin film transistor T2 may be disposed inside the planarization layer. The planarization layer according to an embodiment may include an organic material such as benzocyclobutene or photo acryl, but is not limited thereto.

The groove 450 is a predetermined light emitting area, and a semiconductor device may be disposed therein. Here, the light emitting area may be defined as an area other than the circuit area in the display device.

The groove 450 may be concavely formed in the planarization layer 430 , but is not limited thereto.

The semiconductor device may be disposed in the groove 450 . The first and second electrodes of the semiconductor device may be connected to a circuit (not shown) of the display device.

The semiconductor device may be adhered to the groove 450 through the adhesive layer 420 . Here, the adhesive layer 420 may be the second bonding layer, but is not limited thereto.

The second electrode 152 of the semiconductor device may be electrically connected to the source electrode SE of the driving thin film transistor T2 through the pixel electrode AE. In addition, the first electrode 151 of the semiconductor device may be connected to the common power line CL through the common electrode CE.

The first and second electrodes 151 and 152 may have a step difference from each other, and the electrode 151 located at a relatively lower position among the first and second electrodes 151 and 152 is the same as the top surface of the planarization layer 430 . It may be located on a horizontal line. However, the present invention is not limited thereto.

The pixel electrode AE may electrically connect the source electrode SE of the driving thin film transistor T2 and the second electrode of the semiconductor device.

The common electrode CE may electrically connect the common power line CL and the first electrode of the semiconductor device.

Each of the pixel electrode AE and the common electrode CE may include a transparent conductive material. The transparent conductive material may include a material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

A display device according to an embodiment of the present invention includes a standard definition (SD) level resolution (760×480), a high definition (HD) level resolution (1180×720), a full HD (Full HD) level resolution (1920×1080), and UH (Ultra HD) level resolution (3480×2160), or UHD level or higher resolution (eg, 4K (K=1000), 8K, etc.) may be implemented. In this case, a plurality of semiconductor devices according to the embodiment may be arranged and connected to suit the resolution.

In addition, the display device may be an electric billboard or TV having a diagonal size of 100 inches or more, and the pixel may be implemented as a light emitting diode (LED). Accordingly, power consumption is reduced, and a long lifespan can be provided with a low maintenance cost, and a high-brightness self-luminous display can be provided.

Since the embodiment implements an image and an image using a semiconductor device, color purity and color reproduction are excellent.

Since the embodiment implements images and images using a light emitting device package having excellent straightness, a large display device of 100 inches or more can be implemented with clarity.

The embodiment may implement a high-resolution, 100-inch or larger large display device at a low cost.

The semiconductor device according to the embodiment may further include an optical member such as a light guide plate, a prism sheet, and a diffusion sheet to function as a backlight unit. In addition, the semiconductor device of the embodiment may be further applied to a display device, a lighting device, and an indicator device.

In this case, the display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter. The bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit.

The reflector is disposed on the bottom cover, and the light emitting module emits light. The light guide plate is disposed in front of the reflection plate to guide the light emitted from the light emitting module to the front, and the optical sheet includes a prism sheet and the like, and is disposed in front of the light guide plate. A display panel is disposed in front of the optical sheet, an image signal output circuit supplies an image signal to the display panel, and a color filter is disposed in front of the display panel.

In addition, the lighting device may include a light source module including a substrate and the semiconductor device of the embodiment, a heat dissipation unit for dissipating heat from the light source module, and a power supply unit for processing or converting an electrical signal provided from the outside and providing it to the light source module. . Furthermore, the lighting device may include a lamp, a head lamp, or a street lamp.

In addition, the camera flash of the mobile terminal may include a light source module including the semiconductor device of the embodiment.

In the above, the embodiment has been mainly described, but this is only an example and does not limit the present invention, and those of ordinary skill in the art to which the present invention pertains are not exemplified above in a range that does not depart from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiment may be implemented by modification. And the differences related to these modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

Claims (10)

a semiconductor structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer;
a first electrode electrically connected to the first semiconductor layer; and
a second electrode electrically connected to the second semiconductor layer;
The semiconductor structure includes a first upper surface to which the first semiconductor layer is exposed, a second upper surface on which the second semiconductor layer is disposed, and an inclined surface connecting the first upper surface and the second upper surface, and the second upper surface 1 It includes a groove formed between the upper surface and the inclined surface,
The depth of the groove is 30% or less of a vertical distance between the first upper surface and the second upper surface,
the first semiconductor layer includes a first sub-semiconductor layer exposed to the first upper surface, and a second sub-semiconductor layer disposed on the first sub-semiconductor layer;
The first sub-semiconductor layer has a faster etch rate than the second sub-semiconductor layer.
According to claim 1,
An etch rate difference between the first sub-semiconductor layer and the second sub-semiconductor layer is 30% or less under the same etch condition.
delete 3. The method of claim 2,
The first sub-semiconductor layer includes GaAs,
The second sub-semiconductor layer is a semiconductor device including AlInP.
5. The method of claim 4,
The first sub-semiconductor layer further comprises In,
The In composition of the first sub-semiconductor layer is higher than the In composition of the second sub-semiconductor layer.
delete According to claim 1,
A ratio of a first vertical height from the bottom surface of the semiconductor structure to the second upper surface to a second vertical height from the bottom surface of the semiconductor structure to the first upper surface is 1:0.6 to 1:0.95. .
8. The method of claim 7,
A difference between the first vertical height and the second vertical height is less than 2 μm.
According to claim 1,
A first angle between the inclined plane and the horizontal plane is smaller than a second angle between the side surface of the semiconductor structure and the horizontal plane.
10. The method of claim 9,
The first angle is 20° to 80°, and the second angle is 70° to 90°.

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