KR102360333B1 - Semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a semiconductor device capable of improving device performance by variously adjusting a threshold voltage of a transistor having a gate all-around structure. The semiconductor device may include: a substrate including a first region and a second region; a first wire pattern on the substrate in the first region and spaced apart from the substrate; a second wire pattern on the substrate in the second region, the second wire pattern being spaced apart from the substrate and the first wire pattern; a first gate electrode crossing the first wire pattern and overlapping the first wire pattern by a first width; and a second gate electrode crossing the second wire pattern and overlapping the second wire pattern by a second width different from the first width.

Description

semiconductor device

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a gate all around structure.

As one of the scaling techniques for increasing the density of a semiconductor device, a gate all-around structure in which a silicon body in a nanowire shape is formed on a substrate and a gate is formed to surround the silicon body has been proposed. .

Since the gate all-around structure uses a three-dimensional channel, it is easy to scale. In addition, the current control capability can be improved without increasing the length of the gate. In addition, it is possible to effectively suppress a short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage.

An object of the present invention is to provide a semiconductor device capable of improving device performance by variously adjusting a threshold voltage of a transistor having a gate all-around structure.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of a semiconductor device of the present invention for solving the above problems is a substrate including a first region and a second region; a first wire pattern on the substrate in the first region and spaced apart from the substrate; a second wire pattern on the substrate in the second region, the second wire pattern being spaced apart from the substrate and the first wire pattern; a first gate electrode crossing the first wire pattern and overlapping the first wire pattern by a first width; and a second gate electrode crossing the second wire pattern and overlapping the second wire pattern by a second width different from the first width.

In some embodiments of the present disclosure, the first width is a width at which the first gate electrode and the first wire pattern overlap between the first wire pattern and the substrate, and the second width is the second wire pattern A width at which the second gate electrode and the second wire pattern overlap between the substrate and the substrate.

In some embodiments of the present invention, a first gate spacer positioned at both ends of the first wire pattern, a second gate spacer positioned at both ends of the second wire pattern, and disposed on both sides of the first wire pattern A first epitaxial pattern and a second epitaxial pattern disposed on both sides of the second wire pattern, wherein the first gate electrode is disposed between the first gate spacer, the second gate electrode is the It is disposed between the second gate spacers.

In some embodiments of the present disclosure, a width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the substrate and the first wire pattern may be determined by a width between the substrate and the second wire. A width between the patterns is different from a width of the second gate spacer interposed between the second epitaxial pattern and the second gate electrode.

In some embodiments of the present invention, further comprising: a first gate insulating layer between the first gate spacer and the first gate electrode; and a second gate insulating layer between the second gate spacer and the second gate electrode; The thickness of the first gate insulating layer is different from the thickness of the second gate insulating layer.

In some embodiments of the present invention, the first gate spacer includes an inner spacer positioned between the first wire pattern and the substrate, and an outer spacer positioned on the first wire pattern, wherein the inner spacer includes the It contains a material different from the outer spacer.

In some embodiments of the present disclosure, the first gate spacer defines a first trench, and the second gate spacer defines a second trench, along sidewalls of the first trench and a perimeter of the first wire pattern. The display device further includes a first gate insulating layer extending and a second gate insulating layer extending along a sidewall of the second trench and a circumference of the second wire pattern.

In some embodiments of the present disclosure, on the first wire pattern in the first region, a third wire pattern crossing the first gate electrode, and on the second wire pattern in the second region, the second A fourth wire pattern intersecting the second gate electrode is further included.

In some embodiments of the present invention, the overlapping width of the first gate electrode and the first wire pattern between the first wire pattern and the substrate is the width between the first wire pattern and the third wire pattern. The overlapping width of the first gate electrode and the first wire pattern is substantially the same as the overlapping width of the second gate electrode and the second wire pattern between the second wire pattern and the substrate, and the second wire pattern overlaps with each other. An overlapping width of the second gate electrode and the second wire pattern between the pattern and the fourth wire pattern is substantially the same.

In some embodiments of the present invention, the overlapping width of the first gate electrode and the first wire pattern between the first wire pattern and the substrate is the width between the first wire pattern and the third wire pattern. The overlapping width of the first gate electrode and the first wire pattern is greater than the overlapping width of the second gate electrode and the second wire pattern between the second wire pattern and the substrate, the overlapping width of the second wire pattern and the second wire pattern An overlapping width between the second gate electrode and the second wire pattern between the fourth wire patterns is greater.

In some embodiments of the present disclosure, a height of the first gate electrode between the first wire pattern and the substrate is substantially the same as a height of the first gate electrode between the first wire pattern and the third wire pattern. and a height of the second gate electrode between the second wire pattern and the substrate is substantially the same as a height of the second gate electrode between the second wire pattern and the fourth wire pattern.

In some embodiments of the present disclosure, a height of the first gate electrode between the first wire pattern and the substrate is greater than a height of the first gate electrode between the first wire pattern and the third wire pattern, and the A height of the second gate electrode between the second wire pattern and the substrate is greater than a height of the second gate electrode between the second wire pattern and the fourth wire pattern.

In some embodiments of the present invention, an interlayer insulating film is further included on the substrate of the first region and the second region, wherein a top surface of the interlayer insulating film in the first region is flush with a top surface of the first gate electrode and an upper surface of the interlayer insulating film in the second region is on the same plane as an upper surface of the second gate electrode.

In some embodiments of the present invention, the substrate includes a semiconductor substrate and an insulating film substrate formed on the semiconductor substrate.

In some embodiments of the present invention, it protrudes from the upper surface of the substrate and further includes a first fin-shaped protrusion and a second fin-shaped protrusion spaced apart from each other, wherein the first wire pattern vertically overlaps with the first fin-shaped protrusion and , the second wire pattern is vertically overlapped with the second pin-shaped protrusion.

In some embodiments of the present disclosure, in a longitudinal cross-section of the first wire pattern, the thickness of the first wire pattern is constant as it moves away from the first gate spacer.

In some embodiments of the present disclosure, in a longitudinal cross-section of the first wire pattern, a thickness of the first wire pattern decreases as it moves away from the first gate spacer.

In some embodiments of the present invention, in a longitudinal section of the first wire pattern, the first wire pattern includes a first portion having a first thickness and a second portion having a second thickness smaller than the first thickness, , The first portion of the first wire pattern is disposed on both sides with respect to the second portion of the first wire pattern.

In some embodiments of the present invention, the cross section of the first wire pattern is one of a figure made of a combination of straight lines, a figure made of a combination of straight lines and curved lines, and a figure made of a combination of curves.

Another aspect of the semiconductor device of the present invention for solving the above problems is a substrate including a first region and a second region; a first wire pattern on the substrate in the first region and spaced apart from the substrate; a second wire pattern on the first wire pattern, the second wire pattern being spaced apart from the first wire pattern; a third wire pattern on the substrate in the second region and spaced apart from the substrate; a fourth wire pattern on the third wire pattern, the fourth wire pattern being spaced apart from the third wire pattern; a first gate spacer positioned at both ends of the first wire pattern and the second wire pattern; a second gate spacer positioned at both ends of the third wire pattern and the fourth wire pattern, and a distance by which the second gate spacer is spaced apart between the third wire pattern and the fourth wire pattern is the first wire pattern and a second gate spacer that is smaller than a distance between the second wire patterns by which the first gate spacer is spaced apart; a first gate electrode intersecting the first wire pattern and the second wire pattern between the first gate spacers; and a second gate electrode intersecting the third wire pattern and the fourth wire pattern between the second gate spacers.

In some embodiments of the present invention, further comprising a first epitaxial pattern disposed on both sides of the first gate electrode and a second epitaxial pattern disposed on both sides of the second gate electrode, the first wire pattern and a width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the second wire patterns is the width of the second epitaxial pattern between the third wire pattern and the fourth wire pattern. It is smaller than a width of the second gate spacer interposed between the taxial pattern and the second gate electrode.

In some embodiments of the present disclosure, a width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the substrate is the width of the third wire pattern and the first gate electrode. A width of the second gate spacer interposed between the second epitaxial pattern and the second gate electrode between the substrates is smaller.

In some embodiments of the present disclosure, a width of the first gate electrode between the first wire pattern and the second wire pattern is a width of the second gate electrode between the third wire pattern and the fourth wire pattern. bigger than

In some embodiments of the present disclosure, a width of the first gate electrode between the first wire pattern and the second wire pattern is substantially equal to a width of the first gate electrode between the first wire pattern and the substrate. The width of the second gate electrode between the third wire pattern and the fourth wire pattern is substantially the same as the width of the second gate electrode between the third wire pattern and the substrate.

In some embodiments of the present invention, a width of the first gate electrode between the first wire pattern and the second wire pattern is smaller than a width of the first gate electrode between the first wire pattern and the substrate, A width of the second gate electrode between the third wire pattern and the fourth wire pattern is smaller than a width of the second gate electrode between the third wire pattern and the substrate.

In some embodiments of the present disclosure, a height of the first gate electrode between the first wire pattern and the substrate is substantially the same as a height of the first gate electrode between the first wire pattern and the second wire pattern. and a height of the second gate electrode between the third wire pattern and the substrate is substantially the same as a height of the second gate electrode between the third wire pattern and the fourth wire pattern.

In some embodiments of the present disclosure, a height of the first gate electrode between the first wire pattern and the substrate is greater than a height of the first gate electrode between the first wire pattern and the second wire pattern, and the A height of the second gate electrode between the third wire pattern and the substrate is greater than a height of the second gate electrode between the third wire pattern and the fourth wire pattern.

In some embodiments of the present invention, between the first wire pattern and the substrate, the first gate electrode includes a first electrode layer and a second electrode layer sequentially stacked on the first wire pattern, and the first wire Between the pattern and the second wire pattern, the first gate electrode includes the first electrode layer on the first wire pattern and does not include the second electrode layer.

In some embodiments of the present disclosure, the first gate electrode includes an air gap between the first wire pattern and the second wire pattern, and the first gate electrode includes an air gap between the first wire pattern and the substrate. does not include gaps.

In some embodiments of the present disclosure, a first gate insulating layer extending along a sidewall of the first gate spacer, a perimeter of the first wire pattern, and a perimeter of the second wire pattern, a sidewall of the second gate spacer, and the A second gate insulating layer extending along the circumference of the third wire pattern and the circumference of the fourth wire pattern is further included.

Another aspect of the semiconductor device of the present invention for solving the above problems is a substrate including a first region and a second region; a first wire pattern on the substrate in the first region and spaced apart from the substrate; a second wire pattern on the substrate in the second region and spaced apart from the substrate; first gate spacers positioned at both ends of the first wire pattern; a second gate spacer positioned at both ends of the second wire pattern; a first gate electrode intersecting the first wire pattern between the first gate spacers; a second gate electrode intersecting the second wire pattern between the second gate spacers; a first epitaxial pattern disposed on both sides of the first gate electrode and connected to the first wire pattern; and a second epitaxial pattern disposed on both sides of the second gate electrode and connected to the second wire pattern, wherein the first epitaxial pattern and the first gate are disposed between the first wire pattern and the substrate. A width of the first gate spacer interposed between the electrodes is different from a width of the second gate spacer interposed between the second epitaxial pattern and the second gate electrode between the second wire pattern and the substrate.

In some embodiments of the present disclosure, a width of the first gate electrode between the first wire pattern and the substrate is different from a width of the second gate electrode between the second wire pattern and the substrate.

Another aspect of the semiconductor device of the present invention for solving the above problems is a substrate including a first region and a second region; a first wire pattern on the substrate in the first region and spaced apart from the substrate; a second wire pattern on the substrate in the second region and spaced apart from the substrate; first gate spacers positioned at both ends of the first wire pattern; a second gate spacer positioned at both ends of the second wire pattern; a first gate electrode intersecting the first wire pattern between the first gate spacers; and a second gate electrode intersecting the second wire pattern between the second gate spacers, wherein a height of the first gate spacer between the first wire pattern and the substrate is equal to that of the second wire pattern and the substrate. It is greater than the height of the second gate spacer between the substrates.

In some embodiments of the present disclosure, a height of the first gate electrode between the first wire pattern and the substrate is greater than a height of the second gate electrode between the second wire pattern and the substrate.

In some embodiments of the present invention, the first gate electrode includes a first metal layer and a second metal layer that are sequentially stacked, and the second gate electrode includes a third metal layer and a fourth metal layer that are sequentially stacked.

In some embodiments of the present invention, the first gate electrode between the first wire pattern and the substrate includes the first metal layer and the second metal layer, and the first gate electrode between the second wire pattern and the substrate The gate electrode includes the third metal layer and does not include the fourth metal layer.

In some embodiments of the present invention, the second gate electrode includes an air gap between the substrate and the second wire pattern, and the first gate electrode has an air gap between the substrate and the first wire pattern. include

In some embodiments of the present disclosure, on the first wire pattern in the first region, a third wire pattern crossing the first gate electrode, and on the second wire pattern in the second region, the second A fourth wire pattern intersecting the second gate electrode is further included.

In some embodiments of the present disclosure, a first epitaxial pattern disposed on both sides of the first gate electrode and connected to the first wire pattern, a first epitaxial pattern disposed on both sides of the second gate electrode, and the second wire pattern and a second epitaxial pattern connected to , wherein a first air gap is formed between the first epitaxial pattern and the first gate spacer.

In some embodiments of the present invention, a second air gap is formed between the second epitaxial pattern and the second gate spacer.

Another aspect of the semiconductor device of the present invention for solving the above problems is a substrate including a first region and a second region; a first wire pattern on the substrate in the first region and spaced apart from the substrate; a second wire pattern on the substrate in the second region and spaced apart from the substrate; first gate spacers positioned at both ends of the first wire pattern; a second gate spacer positioned at both ends of the second wire pattern; a first gate electrode intersecting the first wire pattern between the first gate spacers; and a second gate electrode intersecting the second wire pattern between the second gate spacers, wherein the thickness of the first wire pattern as it moves away from the first gate spacer in a longitudinal section of the first wire pattern is constant, in a longitudinal cross-section of the second wire pattern, the first wire pattern includes a first portion having a first thickness and a second portion having a second thickness smaller than the first thickness, the first wire The first portion of the pattern is disposed on both sides with respect to the second portion of the first wire pattern.

In some embodiments of the present disclosure, a height of the first gate electrode between the first wire pattern and the substrate is smaller than a height of the second gate electrode between the second wire pattern and the substrate.

In some embodiments of the present disclosure, a height of the first gate spacer between the first wire pattern and the substrate is substantially the same as a height of the second gate spacer between the second wire pattern and the substrate.

Another aspect of the semiconductor device of the present invention for solving the above problems is a substrate including a first region and a second region; a first wire pattern on the substrate in the first region and spaced apart from the substrate; a second wire pattern on the substrate in the second region and spaced apart from the substrate; first gate spacers positioned at both ends of the first wire pattern; a second gate spacer positioned at both ends of the second wire pattern; a first gate insulating layer extending along sidewalls of the first gate spacer and a circumference of the first wire pattern; a second gate insulating layer extending along a sidewall of the second gate spacer and a circumference of the second wire pattern, the second gate insulating layer having a thickness different from that of the first gate insulating layer; a first gate electrode intersecting the first wire pattern on the first gate insulating layer; and a second gate electrode on the second gate insulating layer that crosses the second wire pattern.

In some embodiments of the present disclosure, a height of the first gate electrode between the first wire pattern and the substrate is different from a height of the second gate electrode between the second wire pattern and the substrate.

In some embodiments of the present disclosure, a height of the first gate spacer between the first wire pattern and the substrate is substantially the same as a height of the second gate spacer between the second wire pattern and the substrate.

Other specific details of the invention are included in the detailed description and drawings.

1 is a schematic plan view for explaining a semiconductor device according to some embodiments of the present invention.
FIG. 2 is a cross-sectional view taken along lines A - A and D - D of FIG. 1 .
3 is a cross-sectional view taken along lines B - B and E - E of FIG. 1 .
4 is a cross-sectional view taken along lines C - C and F - F of FIG. 1 .
5A to 5E are various cross-sectional views taken along line B - B of the first wire pattern of FIG. 1 .
6A to 6C are various cross-sectional views taken along line A - A of the first wire pattern of FIG. 1 .
7 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
8 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
9 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
10 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
11A and 11B are exemplary views for explaining the first wire pattern of FIG. 10 .
12 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
13 is an exemplary view for explaining a first wire pattern of FIG. 12 .
14 and 15 are diagrams for explaining a semiconductor device according to some embodiments of the present invention.
16 and 17 are diagrams for explaining a semiconductor device according to some embodiments of the present invention.
18 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
19 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
20 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
21 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
22 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
23 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
24 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
25 is a schematic plan view for explaining a semiconductor device according to some embodiments of the present invention.
26 is a cross-sectional view taken along lines A - A and D - D of FIG. 25 .
27A and 27B are cross-sectional views taken along lines B - B and E - E of FIG. 25 .
28 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
29 is a view for explaining a semiconductor device according to some embodiments of the present invention.
30 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
31 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
32 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
33 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
34 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
35 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
36 to 46 are intermediate steps for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.
47 is a block diagram of a SoC system including a semiconductor device according to embodiments of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Relative sizes of layers and regions in the drawings may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout.

When one element is referred to as “connected to” or “coupled to” with another element, it means that it is directly connected or coupled to another element, or with the other element intervening. including all cases. On the other hand, when one element is referred to as “directly connected to” or “directly coupled to” with another element, it indicates that another element is not interposed therebetween. Like reference numerals refer to like elements throughout. “and/or” includes each and every combination of one or more of the recited items.

Reference to an element or layer “on” or “on” another element or layer includes not only directly on the other element or layer, but also with other layers or other elements intervening. include all On the other hand, reference to an element "directly on" or "directly on" indicates that no intervening element or layer is interposed.

It should be understood that although first, second, etc. are used to describe various elements, components, and/or sections, these elements, components, and/or sections are not limited by these terms. These terms are only used to distinguish one element, component, or sections from another. Accordingly, it goes without saying that the first element, the first element, or the first section mentioned below may be the second element, the second element, or the second section within the spirit of the present invention.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, "comprises" and/or "comprising" refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless clearly defined in particular.

In the drawings of semiconductor devices according to some embodiments of the present invention, a gate all-around transistor (GAA FET) including a channel region having a nanowire shape or a nanosheet shape is illustrated, but the present invention is not limited thereto. A semiconductor device according to some embodiments of the present invention may include a tunneling transistor (FET), a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), and the like.

A semiconductor device according to some exemplary embodiments will be described with reference to FIGS. 1 to 6C .

1 is a schematic plan view for explaining a semiconductor device according to some embodiments of the present invention. FIG. 2 is a cross-sectional view taken along lines A - A and D - D of FIG. 1 . 3 is a cross-sectional view taken along lines B - B and E - E of FIG. 1 . 4 is a cross-sectional view taken along lines C - C and F - F of FIG. 1 . 5A to 5E are various cross-sectional views taken along line B - B of the first wire pattern of FIG. 1 . 6A to 6C are various cross-sectional views taken along line A - A of the first wire pattern of FIG. 1 . For convenience of description, the interlayer insulating film 190 and the like are not shown in FIG. 1 .

1 to 4 , a semiconductor device according to some embodiments of the present disclosure includes a substrate 100 , a first wire pattern 110 , a second wire pattern 210 , and a first gate insulating layer 130 . ), a second gate insulating layer 230 , a first gate electrode 120 , and a second gate electrode 220 .

The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be spaced apart from each other or may be connected to each other. In the first region I and the second region II, transistors of different types may be formed, or transistors of the same type may be formed in each other.

Also, each of the first region and the second region II may be, for example, one of a logic region, an SRAM region, and an input/output (IO) region. That is, the first region I and the second region II may be regions having the same function or regions having different functions.

In addition, although it is illustrated that the first gate electrode 120 and the second gate electrode 220 are different gate electrodes in FIG. 1 , the present invention is not limited thereto.

When the first region I and the second region II are connected to each other, and the first wire pattern 110 and the second wire pattern 210 spaced apart from each other are adjacent to each other, they intersect the first wire pattern 110 . The first gate electrode 120 and the second gate electrode 220 intersecting the second wire pattern 210 may be the same gate electrode.

The substrate 100 may be a silicon substrate, or may include another material, for example, silicon germanium, indium antimonide, lead tellurium, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 may have an epitaxial layer formed on the base substrate.

The first fin-shaped protrusion 100P may be formed in the first region I, and the second fin-shaped protrusion 200P may be formed in the second region II. The first fin-shaped protrusion 100P and the second fin-shaped protrusion 200P may protrude from the upper surface of the substrate 100 .

The field insulating layer 105 may surround at least a portion of a sidewall of the first fin-shaped protrusion 100P and at least a portion of a sidewall of the second fin-shaped protrusion 200P. The first fin-shaped protrusion 100P and the second fin-shaped protrusion 200P may be defined by the field insulating layer 105 .

The field insulating layer 105 may include, for example, one of an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof.

In FIG. 3 , the sidewalls of the first fin-shaped protrusion 100P and the second fin-shaped protrusion 200P are illustrated as being entirely surrounded by the field insulating film 105 , but this is only for convenience of description, and the present invention is not limited thereto.

The first fin-shaped protrusion 100P may extend long in the first direction X1 , and the second fin-shaped protrusion 200P may extend long in the second direction X2 .

Each of the first fin-shaped protrusion 100P and the second fin-shaped protrusion 200P may be formed by etching a portion of the substrate 100 , and may include an epitaxial layer grown from the substrate 100 .

Each of the first fin-shaped protrusion 100P and the second fin-shaped protrusion 200P may include silicon or germanium, which is an elemental semiconductor material. In addition, each of the first fin-shaped protrusion 100P and the second fin-shaped protrusion 200P may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The group IV-IV compound semiconductor is, for example, a binary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), and a ternary compound (ternary). compound) or a compound doped with a group IV element.

The group III-V compound semiconductor includes, for example, at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements and phosphorus (P), arsenic (As) and antimonium ( It may be one of a binary compound, a ternary compound, or a quaternary compound formed by combining one of Sb).

The first wire pattern 110 may be formed on the substrate 100 in the first region I. The second wire pattern 210 may be formed on the substrate 100 in the second region II. The first wire pattern 110 and the second wire pattern 210 may be formed to be spaced apart from the substrate 100 , respectively.

The first wire pattern 110 may be formed to extend in the first direction X1 like the first fin-shaped protrusion 100P. The second wire pattern 210 may be formed to extend in the second direction X2 like the second pin-shaped protrusion 200P.

The first wire pattern 110 may be formed on the first fin-shaped protrusion 100P to be spaced apart from the first fin-shaped protrusion 100P. The first wire pattern 110 may vertically overlap the first pin-shaped protrusion 100P. The first wire pattern 110 may not be formed on the field insulating layer 105 , but may be formed on the first fin-shaped protrusion 100P.

The second wire pattern 210 may be formed on the second fin-shaped protrusion 200P to be spaced apart from the second fin-shaped protrusion 200P. The second wire pattern 210 may vertically overlap the second pin-shaped protrusion 200P. The second wire pattern 210 may not be formed on the field insulating layer 105 , but may be formed on the second fin-shaped protrusion 200P.

Each of the first wire pattern 110 and the second wire pattern 210 may include silicon or germanium, which is an elemental semiconductor material. In addition, each of the first wire pattern 110 and the second wire pattern 210 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The first wire pattern 110 and the second wire pattern 210 may each be used as a channel region of a transistor.

Depending on whether the semiconductor device including the first wire pattern 110 and the second wire pattern 210 is PMOS or NMOS, the first wire pattern 110 and the second wire pattern 210 may include the same material. or may include different materials.

In addition, the first wire pattern 110 and the second wire pattern 210 may be formed of the same material depending on a transistor that the semiconductor device including the first wire pattern 110 and the second wire pattern 210 has. may include, or may include different materials.

Also, the first wire pattern 110 may include the same material as the first fin-shaped protrusion 100P or a material different from that of the first fin-shaped protrusion 100P. Similarly, the second wire pattern 210 may include the same material as the second fin-shaped protrusion 200P or a material different from that of the second fin-shaped protrusion 200P.

The first gate spacer 140 may extend in the third direction Y1 . The first gate spacer 140 may cross the first wire pattern 110 .

The first gate spacers 140 may be positioned at both ends of the first wire pattern 110 extending in the first direction X1 . The first gate spacers 140 may be formed on both sides of the first wire pattern 110 to face each other. The first gate spacer 140 may include a through portion through which the first wire pattern 110 passes.

The first wire pattern 110 may pass through the first gate spacer 140 . The first gate spacer 140 may be in full contact with the periphery of the end of the first wire pattern 110 .

The first gate spacer 140 may include a first outer spacer 141 and a first inner spacer 142 . The first inner spacer 142 may be disposed between the first fin-shaped protrusion 100P and the first wire pattern 110 .

3 and 4 , the first inner spacer 142 may be formed at a position vertically overlapping with the first wire pattern 110 and/or the first pin-shaped protrusion 100P. The first inner spacer 142 may not be formed on the field insulating layer 105 that does not overlap the first wire pattern 110 and/or the first fin-shaped protrusion 100P. That is, the first outer spacers 141 may be formed on the top surface of the field insulating layer 105 . A first outer spacer 141 may be positioned on the first wire pattern 110 .

The first gate spacer 140 may define a first trench 140t crossing the first wire pattern 110 .

The second gate spacer 240 may extend in the fourth direction Y2 . The second gate spacer 240 may cross the second wire pattern 210 .

The second gate spacers 240 may be positioned at both ends of the second wire pattern 210 extending in the second direction X2 . The second gate spacers 240 may be formed on both sides of the second wire pattern 210 to face each other. The second gate spacer 240 may include a through portion through which the second wire pattern 110 passes.

The second wire pattern 210 may pass through the second gate spacer 240 . The second gate spacer 240 may entirely contact the periphery of the end of the second wire pattern 210 .

The second gate spacer 240 may include a second outer spacer 241 and a second inner spacer 242 . The second inner spacer 242 may be disposed between the second pin-shaped protrusion 200P and the second wire pattern 210 .

3 and 4 , the second inner spacer 242 may be formed at a position vertically overlapping with the second wire pattern 210 and/or the second pin-shaped protrusion 200P. The second inner spacer 242 may not be formed on the field insulating layer 105 that does not overlap the second wire pattern 210 and/or the second fin-shaped protrusion 200P. That is, the second outer spacers 241 may be formed on the top surface of the field insulating layer 105 . A second outer spacer 241 may be positioned on the second wire pattern 210 .

The second gate spacer 240 may define a second trench 240t crossing the second wire pattern 210 .

The first outer spacer 141 and the second outer spacer 241 are, respectively, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon oxycarbonitride (SiOCN), and their It may include at least one of the combinations.

The first inner spacer 142 and the second inner spacer 242 are, respectively, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon oxycarbonitride (SiOCN) and their It may include at least one of the combinations.

In FIG. 2 , the first outer spacer 141 and the first inner spacer 142 may be made of the same material, and the second outer spacer 241 and the second inner spacer 242 may be made of the same material.

The first gate insulating layer 130 may be formed along the circumference of the first wire pattern 110 . That is, the first gate insulating layer 130 may surround the first wire pattern 110 .

Also, the first gate insulating layer 130 may be formed on the top surface of the field insulating layer 105 and on the first fin-shaped protrusion 100P. The first gate insulating layer 130 may extend along an inner wall of the first gate spacer 140 .

In other words, the first gate insulating layer 130 may extend along sidewalls and bottom surfaces of the first trench 140t and the circumference of the first wire pattern 110 .

Although not shown, an interface layer may be formed between the first gate insulating layer 130 and the first wire pattern 110 and between the first gate insulating layer 130 and the first fin-shaped protrusion 100P. In addition, depending on the method of forming the interface layer, the interface layer may be formed to have the same profile as that of the first gate insulating layer 130 .

The second gate insulating layer 230 may be formed along the circumference of the second wire pattern 210 . That is, the second gate insulating layer 230 may surround the second wire pattern 210 .

Also, the second gate insulating layer 230 may be formed on the top surface of the field insulating layer 105 and on the second fin-shaped protrusion 200P. The second gate insulating layer 230 may extend along an inner wall of the second gate spacer 240 .

In other words, the second gate insulating layer 230 may extend along sidewalls and bottom surfaces of the second trench 240t and the circumference of the second wire pattern 210 .

Although not shown, an interface layer may be formed between the second gate insulating layer 230 and the second wire pattern 210 and between the second gate insulating layer 230 and the second fin-shaped protrusion 200P. In addition, depending on the method of forming the interface layer, the interface layer may be formed to have the same profile as that of the second gate insulating layer 230 .

Each of the first gate insulating layer 130 and the second gate insulating layer 230 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide.

The high-k material is, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide), zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide oxide), strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate may include

In addition, although the above-described high dielectric constant insulating film has been mainly described with respect to the oxide, the present invention is not limited thereto. Unlike the above, the high-k insulating layer may include at least one of a nitride (eg, hafnium nitride) or an oxynitride (eg, hafnium oxynitride) of a metallic material, but is limited thereto. it is not

The first gate insulating layer 130 and the second gate insulating layer 230 may include the same material or different materials.

2 to 4 , the thickness of the first gate insulating layer 130 and the thickness of the second gate insulating layer 230 may be the same.

The first gate electrode 120 may cross the substrate 100 and the first wire pattern 110 formed to be spaced apart from the first fin-shaped protrusion 100P. The first gate electrode 120 may be formed to surround the circumference of the first wire pattern 110 .

The first gate electrode 120 may also be formed in a space spaced apart between the first wire pattern 110 and the first fin-shaped protrusion 100P.

The first gate electrode 120 may be disposed between the first gate spacers 140 . The first gate electrode 120 may be formed on the first gate insulating layer 130 . The first gate electrode 120 may fill the first trench 140t.

The first gate electrode 120 may include M metal layers. Here, M may be a natural number greater than 2. 2 to 4 , the first gate electrode 120 may include the first lower metal layer 122 and the first upper metal layer 124 , but is only for convenience of description and is not limited thereto.

The first lower metal layer 122 may be formed on the first gate insulating layer 130 . The first lower metal layer 122 may be formed along a profile of the first gate insulating layer 130 .

The first lower metal layer 122 may be formed along the circumference of the first wire pattern 110 . The first lower metal layer 122 may surround the first gate insulating layer 130 .

Also, the first lower metal layer 122 may be formed on the top surface of the field insulating layer 105 and the first fin-shaped protrusion 100P. The first lower metal layer 122 may extend along an inner wall of the first gate spacer 140 .

In other words, the first lower metal layer 122 may extend along sidewalls and bottom surfaces of the first trench 140t and the circumference of the first wire pattern 110 .

The first upper metal layer 124 may be formed on the first lower metal layer 122 . The first upper metal layer 124 may fill the first trench 140t in which the first lower metal layer 122 is formed.

The second gate electrode 220 may cross the substrate 100 and the second wire pattern 210 formed to be spaced apart from the second fin-shaped protrusion 200P. The second gate electrode 220 may be formed to surround the circumference of the second wire pattern 210 .

The second gate electrode 220 may also be formed in a space spaced apart between the second wire pattern 210 and the second fin-shaped protrusion 200P.

The second gate electrode 220 may be disposed between the second gate spacers 240 . The second gate electrode 220 may be formed on the second gate insulating layer 230 . The second gate electrode 220 may fill the second trench 240t.

The second gate electrode 220 may include N metal layers. Here, N may be a natural number greater than 2. 2 to 4 , the second gate electrode 220 may include the second lower metal layer 222 and the second upper metal layer 224 , but is only for convenience of description and is not limited thereto.

The second lower metal layer 222 may be formed on the second gate insulating layer 230 . The second lower metal layer 222 may be formed along a profile of the second gate insulating layer 230 .

The second lower metal layer 222 may be formed along the circumference of the second wire pattern 210 . The second lower metal layer 222 may surround the second gate insulating layer 230 .

Also, the second lower metal layer 222 may be formed on the top surface of the field insulating layer 105 and the second fin-shaped protrusion 200P. The second lower metal layer 222 may extend along an inner wall of the second gate spacer 240 .

In other words, the second lower metal layer 222 may extend along sidewalls and bottom surfaces of the second trench 240t and the circumference of the second wire pattern 110 .

The second upper metal layer 224 may be formed on the second lower metal layer 222 . The second upper metal layer 224 may fill the second trench 240t in which the second lower metal layer 222 is formed.

The first lower metal layer 122 and the second lower metal layer 222 are, respectively, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum carbonitride (TaCN), titanium silicon nitride ( TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum It may include at least one of carbide (TiAlC), titanium aluminum carbonitride (TiAlC-N), titanium carbide (TiC), and combinations thereof.

In addition, each of the first lower metal layer 122 and the second lower metal layer 222 may include an oxidized form of the above-described material.

Although each of the first lower metal layer 122 and the second lower metal layer 222 is illustrated as a single layer, it is only for convenience of description and is not limited thereto.

Each of the first upper metal layer 124 and the second upper metal layer 224 is, for example, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), or titanium nitride (TiN). ), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), poly-Si, SiGe, or at least one of a metal alloy, but is not limited thereto.

The first lower metal layer 122 and the second lower metal layer 222 may or may not have the same material as each other. 2 to 4 , the first lower metal layer 122 and the second lower metal layer 222 may have a stacked structure including the same number of metal layers.

In addition, the first upper metal layer 124 and the second upper metal layer 224 may or may not include the same material.

The first epitaxial pattern 150 may be formed on both sides of the first gate electrode 120 . The first epitaxial pattern 150 may be disposed on both sides of the first wire pattern 110 and may be connected to the first wire pattern 110 . The first epitaxial pattern 150 may be formed on the first fin-shaped protrusion 100P.

The second epitaxial pattern 250 may be formed on both sides of the second gate electrode 220 . The second epitaxial pattern 250 may be disposed on both sides of the second wire pattern 210 and may be connected to the second wire pattern 210 . The second epitaxial pattern 250 may be formed on the second fin-shaped protrusion 200P.

The first epitaxial pattern 150 and the second epitaxial pattern 250 may be included in the source/drain region, respectively.

The relationship between the first inner spacer 142 and the second inner spacer 242 will be described with reference to FIG. 2 .

In addition, the width of the first gate electrode 120 formed between the first inner spacers 142 according to the relationship between the first inner spacers 142 and the second inner spacers 242 and the second inner spacers 242 A change in the width of the second gate electrode 220 formed therebetween will be described.

For example, the distance between the first epitaxial pattern 150 and the outer wall of the first gate spacer 140 facing is the distance between the second epitaxial pattern 250 and the outer wall of the second gate spacer 240 facing the second epitaxial pattern 250 . may be substantially equal to the distance.

A width SW11 of the first inner spacer 142 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the substrate 100 is a second It may be different from the width SW21 of the second inner spacer 242 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the wire pattern 210 and the substrate 100 .

For example, in FIG. 2 , the width SW11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is between the second wire pattern 210 and the substrate 100 . It may be smaller than the width SW21 of the second inner spacer 242 .

In other words, the distance G11 by which the first gate spacer 140 is spaced apart between the first wire pattern 110 and the substrate 100 is the second gate space between the second wire pattern 210 and the substrate 100 . The spacer 240 may be different from the spaced distance G21.

More specifically, the distance G11 by which the first inner spacers 142 are spaced apart between the first wire pattern 110 and the substrate 100 is a second distance G11 between the second wire pattern 210 and the substrate 100 . The distance G21 by which the inner spacers 242 are spaced apart may be different.

For example, in FIG. 2 , a distance G11 by which the first gate spacer 140 is spaced apart between the first wire pattern 110 and the substrate 100 is between the second wire pattern 210 and the substrate 100 . In , the second gate spacer 240 may be greater than the distance G21 spaced apart from each other.

On the other hand, the height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is the second gate spacer 240 between the second wire pattern 210 and the substrate 100 . ) may be substantially equal to the height SH21.

In other words, the height SH11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is the second inner spacer between the second wire pattern 210 and the substrate 100 . It may be substantially equal to the height SH21 of 242 .

Since the spaced distance G11 of the first inner spacer 142 is different from the spaced distance G21 of the second inner spacer 242 , the first gate is disposed between the first wire pattern 110 and the substrate 100 . A width W11 of the electrode 120 may be different from a width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 .

Since the spaced distance G11 of the first inner spacer 142 is greater than the spaced distance G21 of the second inner spacer 242 , the first gate is disposed between the first wire pattern 110 and the substrate 100 . The width W11 of the electrode 120 may be greater than the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 .

In other words, the width W11 at which the first gate electrode 120 and the first wire pattern 110 overlap between the first wire pattern 110 and the substrate 100 is equal to that of the second wire pattern 210 and the second wire pattern 210 . The width W21 at which the second gate electrode 220 and the second wire pattern 210 overlap between the substrate 100 may be different from each other.

For example, the width W11 at which the first gate electrode 120 and the first wire pattern 110 overlap between the first wire pattern 110 and the substrate 100 is the second wire pattern 210 and The overlapping width W21 between the second gate electrode 220 and the second wire pattern 210 between the substrate 100 may be greater.

Meanwhile, in FIG. 2 , the first wire pattern 110 may include a first side and a second side facing each other. The first side of the first wire pattern 110 may be closer to the substrate 100 than the second side of the first wire pattern 110 .

A width W11 at which the first side of the first wire pattern 110 overlaps with the first gate electrode 120 is a width W11 at which the second side of the first wire pattern 110 overlaps with the first gate electrode 120 . It may be different from the width W12.

In FIG. 2 , the second wire pattern 210 may include third and fourth sides facing each other. The third side of the second wire pattern 210 may be closer to the substrate 100 than the fourth side of the second wire pattern 210 .

A width W21 at which the third side of the second wire pattern 210 overlaps with the second gate electrode 220 is a width W21 at which the fourth side of the second wire pattern 210 overlaps with the second gate electrode 220 . Although shown as the same as the width W22, it is not limited thereto.

A width W11 at which the first gate electrode 120 and the first wire pattern 110 overlap between the first wire pattern 110 and the substrate 100 is the second wire pattern 210 and the substrate 100 . By different from the width W21 at which the second gate electrode 220 and the second wire pattern 210 overlap each other, the threshold voltage of the transistor in the first region I is increased by the threshold voltage of the transistor in the second region II. voltage may be different.

Through this, device performance of the semiconductor device may be improved by manufacturing the semiconductor device having various threshold voltages.

The interlayer insulating layer 190 may be formed on the substrate 100 . The interlayer insulating layer 190 may surround an outer wall of the first gate spacer 140 defining the first trench 140t and an outer wall of the second gate spacer 240 defining the second trench 240t.

The interlayer insulating layer 190 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low dielectric constant material is, for example, Flowable Oxide (FOX), Tonen SilaZene (TOSZ), Undoped Silica Glass (USG), Borosilica Glass (BSG), PhosphoSilica Glass (PSG), BoroPhosphoSilica Glass (BPSG), Plasma Enhanced Tetra (PETEOS). Ethyl Ortho Silicate), FSG(Fluoride Silicate Glass), CDO(Carbon Doped silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG(Organo Silicate Glass), Parylene, BCB(bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material or a combination thereof, but is not limited thereto.

In FIG. 2 , the top surface of the interlayer insulating layer 190 of the first region (I) is on the same plane as the top surface of the first gate electrode 120 , and the top surface of the interlayer insulating layer 190 of the second region (II) is Although it is illustrated as being on the same plane as the top surface of the second gate electrode 220 , the present invention is not limited thereto.

Unlike the one illustrated in FIG. 2 , a capping pattern may be formed on the upper surfaces of the first gate electrode 120 and the second gate electrode 220 , respectively. When the capping pattern is formed, a top surface of the capping pattern on the first gate electrode 120 may be on the same plane as the top surface of the interlayer insulating layer 190 of the first region (I). Similarly, a top surface of the capping pattern on the second gate electrode 220 may be coplanar with a top surface of the interlayer insulating layer 190 of the second region II.

A cross section of the first wire pattern 110 will be described with reference to FIGS. 5A to 5E . Of course, the description of the first wire pattern 110 may also be applied to the second wire pattern 210 .

In FIG. 5A , the cross-section 110s of the first wire pattern 110 may be a figure formed by a combination of straight lines 110m. The cross-section 110s of the first wire pattern 110 may be, for example, a rectangle. In the cross section 110s of the first wire pattern 110 , the width L1 of the first wire pattern 110 and the height L2 of the first wire pattern 110 may be the same. More specifically, the cross-section 110s of the first wire pattern 110 may be a square, but is not limited thereto.

Unlike FIG. 5A , in FIG. 5B , in the cross-section 110s of the first wire pattern 110 , the width L1 of the first wire pattern 110 and the height L2 of the first wire pattern 110 are different from each other. can More specifically, the cross-section 110s of the first wire pattern 110 may be rectangular, but is not limited thereto.

Unlike FIG. 5A , in FIG. 5C , in the cross-section 110s of the first wire pattern 110 , the width L11 of one side of the first wire pattern 110 facing each other and the other side of the first wire pattern 110 are The width L12 may be different from each other. More specifically, the cross-section 110s of the first wire pattern 110 may be a trapezoid, but is not limited thereto.

Unlike FIG. 5A , in FIG. 5D , the cross-section 110s of the first wire pattern 110 may be a figure formed by a combination of a straight line 110m and a curved line 110n. The cross-section 110s of the first wire pattern 110 may be, for example, a quadrangle with rounded corners.

Unlike FIG. 5A , in FIG. 5E , the cross-section 110s of the first wire pattern 110 may be a figure formed by a combination of curves 110n.

5A to 5E , the cross-section 110s of the first wire pattern 110 may be one of a figure formed by a combination of straight lines, a figure formed by a combination of straight lines and curves, and a figure formed by a combination of curves.

A longitudinal cross-section of the first wire pattern 110 will be described with reference to FIGS. 6A to 6C . Of course, the description of the first wire pattern 110 may also be applied to the second wire pattern 210 .

6A , as the first epitaxial pattern 150 and the first gate spacer 140 move away from each other, the thickness of the first wire pattern 110 may be substantially the same. For example, a thickness t1_a of a terminal portion of the first wire pattern 110 adjacent to the first epitaxial pattern 150 may be substantially equal to a thickness t1_b of a central portion of the first wire pattern 110 . can

6B , as the distance from the first epitaxial pattern 150 and the first gate spacer 140 increases, the thickness of the first wire pattern 110 may decrease. For example, a thickness t1_a of a terminal portion of the first wire pattern 110 adjacent to the first epitaxial pattern 150 may be thicker than a thickness t1_b of a central portion of the first wire pattern 110 .

6C , as the distance from the first epitaxial pattern 150 and the first gate spacer 140 increases, the thickness of the first wire pattern 110 may increase. For example, a thickness t1_a of a terminal portion of the first wire pattern 110 adjacent to the first epitaxial pattern 150 may be thinner than a thickness t1_b of a central portion of the first wire pattern 110 .

6B and 6C , the thickness of the first wire pattern 110 may change continuously as it moves away from the first epitaxial pattern 150 and the first gate spacer 140 .

7 is a diagram for describing a semiconductor device according to some embodiments of the present invention. 8 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. 9 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. For convenience of description, the points different from those described with reference to FIGS. 1 to 6C will be mainly described.

Referring to FIG. 7 , in the semiconductor device according to some embodiments of the present disclosure, a first inner spacer 142 is further formed on the first wire pattern 110 , and a second inner spacer 142 is further formed on the second wire pattern 210 . An inner spacer 242 may be further formed.

For example, the width of the first inner spacer 142 on the first wire pattern 110 may be the same as the width of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 . have.

Also, the width of the second inner spacer 242 on the second wire pattern 210 may be the same as the width of the second inner spacer 242 between the second wire pattern 210 and the substrate 100 .

The first wire pattern 110 may include a first side and a second side facing each other. The first side of the first wire pattern 110 may be closer to the substrate 100 than the second side of the first wire pattern 110 .

In FIG. 7 , the width W11 at which the first side of the first wire pattern 110 and the first gate electrode 120 overlap is the second side of the first wire pattern 110 and the first gate electrode 120 . ) may be substantially equal to the overlapping width W12.

If the width of the first inner spacer 142 on the first wire pattern 110 is different from the width of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 , the first The overlapping width W11 of the first side of the wire pattern 110 and the first gate electrode 120 is the overlapping width W11 of the second side of the first wire pattern 110 and the first gate electrode 120 . W12) may be different.

Referring to FIG. 8 , in the semiconductor device according to some embodiments of the present disclosure, the first inner spacer 142 may include a material different from that of the first outer spacer 141 . Also, the second inner spacer 242 may include a material different from that of the second outer spacer 241 .

The first outer spacer 141 and the second outer spacer 241 are, respectively, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon oxycarbonitride (SiOCN), and their It may include at least one of the combinations.

The first inner spacer 142 and the second inner spacer 242 are each formed of a low-k material, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon oxycarbonitride (SiOCN), and silicon boron. It may include at least one of nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. The low-k material may be, for example, a material having a dielectric constant smaller than that of silicon oxide.

Alternatively, each of the first inner spacer 142 and the second inner spacer 242 includes at least one element selected from the group consisting of carbon (C), nitrogen (N), oxygen (O), and hydrogen (H) and silicon ( Si) may be included.

For example, when the dielectric constant of the material included in the first outer spacer 141 is the first dielectric constant and the dielectric constant of the material included in the first inner spacer 142 is the second dielectric constant, the first dielectric constant and the second dielectric constant are may be different.

For example, the first dielectric constant of the material included in the first outer spacer 141 may be greater than the second dielectric constant of the material included in the first inner spacer 142 . By making the second dielectric constant smaller than the first dielectric constant, a fringing capacitance between the first gate electrode 120 and the first epitaxial pattern 150 may be reduced.

Referring to FIG. 9 , in the semiconductor device according to some embodiments of the present invention, the first outer spacer 141 includes a first spacer layer 141a and a second spacer layer 141b, and the second outer spacer ( 241 may include a third spacer layer 241a and a fourth spacer layer 241b.

However, each of the first inner spacer 142 and the second inner spacer 242 may be a single layer.

For example, each of the first spacer layer 141a and the third spacer layer 241a may have an L-shape. That is, at least one of the first outer spacer 141 and the second outer spacer 241 made of a multilayer film may have an L-shape.

In addition, at least one of the first outer spacer 141 and the second outer spacer 241 made of a multilayer film may include a silicon oxycarbonitride film (SiOCN).

9 , each of the first inner spacer 142 and the second inner spacer 242 may be a multilayer film. In this case, the number of films forming the first outer spacer 141 may be different from the number of films forming the first inner spacer 142 . Also, the number of layers forming the second outer spacer 241 may be different from the number of layers forming the second inner spacer 242 .

10 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. 11A and 11B are exemplary views for explaining the first wire pattern of FIG. 10 . 12 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. 13 is an exemplary view for explaining a first wire pattern of FIG. 12 .

For reference, FIGS. 11A, 11B and 13 are longitudinal cross-sections taken along line A - A of FIG. 1 , respectively.

10 to 11B , in the semiconductor device according to some embodiments of the present invention, the first wire pattern 110 and the second wire pattern 210 may each be a trimmed wire pattern.

Also, in FIG. 10 , the first wire pattern 110 may include a first side and a second side facing each other. The first side of the first wire pattern 110 may be closer to the substrate 100 than the second side of the first wire pattern 110 . In this case, the width of the first gate spacer 140 positioned between the first side of the first wire pattern 110 and the substrate 100 is equal to the width of the first gate spacer 140 on the second side of the first wire pattern 110 . 140) may be different.

For example, the first wire pattern 110 may include a first portion 110a, a second portion 110b, and a third portion 110c.

The second portion 110b of the first wire pattern may be disposed on both sides of the first portion 110a of the first wire pattern. The third portion 110c of the first wire pattern may be disposed on both sides of the first portion 110a of the first wire pattern. The third portion 110c of the first wire pattern may be disposed between the first portion 110a of the first wire pattern and the second portion 110b of the first wire pattern.

The thickness t13 of the third portion 110c of the first wire pattern is greater than the thickness t11 of the first portion 110a of the first wire pattern, and the thickness of the second portion 110b of the first wire pattern ( t12).

11B shows a connection portion between the third portion 110c of the first wire pattern and the second portion 110b of the first wire pattern is rounded, and the third portion 110c of the first wire pattern and the first wire pattern are rounded. It is a view showing that the connection part of the first part 110a of the can be rounded.

In FIGS. 11A and 11B , the width of the first portion 110a of the first wire pattern is illustrated as being constant irrespective of the position, but it is only for convenience of description and is not limited thereto. That is, of course, the width of the first portion 110a of the first wire pattern may be changed as shown in FIG. 6B or 6C.

10 and 12 , the shape of the trimmed second wire pattern 210 is similar to that of FIGS. 11A and 11B according to the width of the second gate spacer 240 on which the second wire pattern 210 is positioned above and below. This may be done, or it may be similar to FIG. 13, which will be described later.

12 and 13 , in the semiconductor device according to some embodiments of the present disclosure, the first wire pattern 110 and the second wire pattern 210 may be trimmed wire patterns, respectively.

Also, in FIG. 12 , the first wire pattern 110 may include a first side and a second side facing each other. The first side of the first wire pattern 110 may be closer to the substrate 100 than the second side of the first wire pattern 110 . In this case, the width of the first gate spacer 140 positioned between the first side of the first wire pattern 110 and the substrate 100 is equal to the width of the first gate spacer 140 on the second side of the first wire pattern 110 . 140) may be substantially equal to the width.

The second portion 110b of the first wire pattern may be disposed on both sides of the first portion 110a of the first wire pattern.

A thickness t12 of the second portion 110b of the first wire pattern is greater than a thickness t11 of the first portion 110a of the first wire pattern.

It goes without saying that the connection portion between the second portion 110b of the first wire pattern and the first portion 110a of the first wire pattern may be rounded, unlike the one illustrated in FIG. 13 .

In addition, although in FIG. 13 , the width of the first portion 110a of the first wire pattern is shown to be constant regardless of the position, it is only for convenience of description, and is not limited thereto. That is, of course, the width of the first portion 110a of the first wire pattern may be changed as shown in FIG. 6B or 6C.

14 and 15 are diagrams for explaining a semiconductor device according to some embodiments of the present invention. For convenience of description, points different from those described with reference to FIGS. 1 to 6C will be mainly described.

For reference, FIG. 14 is a cross-sectional view taken along lines A - A and D - D of FIG. 1 , and FIG. 15 is a cross-sectional view taken along lines B - B and E - E of FIG. 1 .

14 and 15 , in a semiconductor device according to some embodiments of the present invention, a first insulating pattern 100pi formed on the first fin-shaped protrusion 100P and a first insulating pattern 100pi formed on the second fin-shaped protrusion 200P 2 may further include an insulating pattern 200pi.

The first insulating pattern 100pi may be formed on the upper surface of the first fin-shaped protrusion 100P. The first insulating pattern 100pi may be in contact with the first fin-shaped protrusion 100P. The first insulating pattern 100pi may not be formed on the top surface of the field insulating layer 105 .

A width of the first insulating pattern 100pi may correspond to a width of the first fin-shaped protrusion 100P under the first insulating pattern 100pi.

The second insulating pattern 200pi may be formed on the upper surface of the second fin-shaped protrusion 200P. The second insulating pattern 200pi may be in contact with the second fin-shaped protrusion 200P. The second insulating pattern 200pi may not be formed on the top surface of the field insulating layer 105 .

The width of the second insulating pattern 200pi may correspond to the width of the second fin-shaped protrusion 200P under the second insulating pattern 200pi.

The first insulating pattern 100pi and the second insulating pattern 200pi may include an insulating material.

In FIG. 15 , the upper surface of the first insulating pattern 100pi and the second insulating pattern 200pi are illustrated as being on the same plane as the upper surface of the field insulating layer 105 , but it is only for convenience of explanation, and the present invention is not limited thereto. no.

15, the first insulating pattern 100pi is formed entirely along the upper surface of the first fin-shaped protrusion 100P, and the second insulating pattern 200pi is formed entirely along the upper surface of the second fin-shaped protrusion 200P. Although illustrated, it is only for convenience of description, and is not limited thereto.

For example, the first insulating pattern 100pi may be formed on a portion overlapping the first gate electrode 120 , but may not be formed on a portion overlapping the first source/drain region 150 . Conversely, the first insulating pattern 100pi may not be formed on a portion overlapping the first gate electrode 120 , but may be formed on a portion overlapping the first source/drain region 150 .

In other words, the first insulating pattern 100pi may be formed on a portion of the upper surface of the first fin-shaped protrusion 100P, and may not be formed on the rest.

Since the description of the second insulating pattern 200pi is substantially similar to the description of the first insulating pattern 100pi, it will be omitted.

16 and 17 are diagrams for explaining a semiconductor device according to some embodiments of the present invention. For convenience of description, points different from those described with reference to FIGS. 1 to 6C will be mainly described.

For reference, FIG. 16 is a cross-sectional view taken along lines A - A and D - D of FIG. 1 , and FIG. 17 is a cross-sectional view taken along lines B - B and E - E of FIG. 1 .

16 and 17 , in the semiconductor device according to some embodiments of the present disclosure, the substrate 100 may include a lower substrate 101 and an upper substrate 103 formed on one surface of the lower substrate 101 . can

For example, the lower substrate 101 may be a semiconductor substrate, and the upper substrate 103 may be an insulating film substrate.

The substrate 100 may include a semiconductor substrate and an insulating film substrate formed on one surface of the semiconductor substrate, and may be, for example, silicon on insulator (SOI) or silicon-germanium on insulator (SGOI), but is limited thereto. it is not

18 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. 19 is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of description, points different from those described with reference to FIGS. 1 to 6C will be mainly described.

For reference, FIGS. 18 and 19 are cross-sectional views taken along lines A - A and D - D of FIG. 1 .

Referring to FIG. 18 , in the semiconductor device according to some embodiments of the present disclosure, a thickness ti1 of the first gate insulating layer 130 may be different from a thickness ti2 of the second gate insulating layer 230 .

For example, the thickness ti1 of the first gate insulating layer 130 may be smaller than the thickness ti2 of the second gate insulating layer 230 .

The height SH11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is the height SH11 of the second inner spacer 242 between the second wire pattern 210 and the substrate 100 . It may be substantially equal to the height SH21.

The first gate electrode 120 and the first gate insulating layer 130 are formed between the first wire pattern 110 and the substrate 100 , and the second gate electrode 220 and the second gate insulating layer 230 are It may be formed between the two wire pattern 210 and the substrate 100 .

More specifically, between the first wire pattern 110 and the substrate 100 , the first gate insulating layer 130 is between the first wire pattern 110 and the first gate electrode 120 , and the substrate 100 . and the first gate electrode 120 .

Between the second wire pattern 210 and the substrate 100 , the second gate insulating layer 230 is formed between the second wire pattern 210 and the second gate electrode 220 , and between the substrate 100 and the second gate electrode formed between 220 .

The height SH11 of the first inner spacer 142 is substantially the same as the height SH21 of the second inner spacer 242 , and the thickness ti1 of the first gate insulating layer 130 is the second gate insulating layer 230 . ) is different from the thickness ti2 , so the height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is between the second wire pattern 210 and the substrate 100 . may be different from the height h21 of the second gate electrode 220 .

When the thickness ti1 of the first gate insulating layer 130 is smaller than the thickness ti2 of the second gate insulating layer 230 , the first gate electrode 120 between the first wire pattern 110 and the substrate 100 . The height h11 may be greater than that of the second gate electrode h21 between the second wire pattern 210 and the substrate 100 .

The width SW11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is the width SW11 of the second inner spacer 242 between the second wire pattern 210 and the substrate 100 . It may be substantially equal to the width SW21.

Between the first wire pattern 110 and the substrate 100 , the first gate insulating layer 130 is formed between the first gate spacer 140 and the first gate electrode 120 . Between the second wire pattern 210 and the substrate 100 , the second gate insulating layer 230 is formed between the second gate spacer 240 and the second gate electrode 220 .

At this time, since the thickness ti1 of the first gate insulating layer 130 is different from the thickness ti2 of the second gate insulating layer 230 , the first gate electrode between the first wire pattern 110 and the substrate 100 . The width W11 of 120 may be different from the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 .

In other words, the width W11 at which the first gate electrode 120 and the first wire pattern 110 overlap between the first wire pattern 110 and the substrate 100 is equal to that of the second wire pattern 210 and the second wire pattern 210 . The width W21 at which the second gate electrode 220 and the second wire pattern 210 overlap between the substrate 100 may be different from each other.

When the thickness ti1 of the first gate insulating layer 130 is smaller than the thickness ti2 of the second gate insulating layer 230 , the first gate electrode 120 between the first wire pattern 110 and the substrate 100 . The width W11 may be greater than the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 .

Unlike the above, the width SW11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is the second inner spacer between the second wire pattern 210 and the substrate 100 . When the width of 242 is smaller than SW21, according to the relationship between the thickness ti1 of the first gate insulating layer 130 and the thickness ti2 of the second gate insulating layer 230, the first wire pattern 110 The width W11 of the first gate electrode 120 between the substrate 100 and the second wire pattern 210 may be different from the width W21 of the second gate electrode 220 between the substrate 100 and the second wire pattern 210 , , may be the same.

Referring to FIG. 19 , in a semiconductor device according to some embodiments of the present disclosure, a first wire pattern 110 may be a trimmed wire pattern, and a second wire pattern 210 may be an untrimmed wire pattern.

11A, 11B and 13 , the trimmed first wire pattern 110 includes a first portion 110a of a first wire pattern having different thicknesses and a second portion 110b of the first wire pattern. may include The second portion 110b of the first wire pattern may be disposed on both sides of the first portion 110a of the first wire pattern.

Meanwhile, since the second wire pattern 210 is not trimmed, the thickness of the second wire pattern 210 may be constant as it moves away from the second gate spacer 240 .

The height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is the height SH11 of the second gate spacer 240 between the second wire pattern 210 and the substrate 100 . It may be substantially equal to the height SH21. That is, the height SH11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is the second inner spacer 242 between the second wire pattern 210 and the substrate 100 . ) may be substantially equal to the height SH21.

On the other hand, since the first wire pattern 110 is trimmed and the second wire pattern 210 is not trimmed, the gap between the first wire pattern 110 on which the first gate electrode 120 is formed and the substrate 100 is The space may be larger than the space between the second wire pattern 210 and the substrate 100 in which the second gate electrode 220 is formed.

Accordingly, the height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is the second gate electrode h21 between the second wire pattern 210 and the substrate 100 . ) can be greater than

20 is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of description, the points different from those described with reference to FIGS. 1 to 6C will be mainly described.

Referring to FIG. 20 , in the semiconductor device according to some embodiments of the present disclosure, the height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is the second wire pattern. The height SH21 of the second gate spacer 240 between the 210 and the substrate 100 may be different.

In other words, the height SH11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is the second inner spacer between the second wire pattern 210 and the substrate 100 . It may be different from the height SH21 of 242 .

For example, in FIG. 20 , the height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is between the second wire pattern 210 and the substrate 100 . It may be greater than the height SH21 of the second gate spacer 240 .

That is, the space in which the first gate electrode 120 is formed between the first wire pattern 110 and the substrate 100 is between the second wire pattern 210 and the substrate 100 , the second gate electrode 220 . The space to be formed may be different.

The height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is the height SH11 of the second gate spacer 240 between the second wire pattern 210 and the substrate 100 . Since it is different from the height SH21 , the height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is the second height h11 between the second wire pattern 210 and the substrate 100 . 2 It may be different from the height h21 of the gate electrode 220 .

When the height SH11 of the first inner spacer 142 is greater than the height SH21 of the second inner spacer 242 , the first gate electrode 120 between the first wire pattern 110 and the substrate 100 . The height h11 may be greater than the height h21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 .

The first gate electrode 120 includes a first lower metal layer 122 and a first upper metal layer 124 , and the second gate electrode 220 includes a second lower metal layer 222 and a second upper metal layer 224 . may include

The first gate electrode 120 between the substrate 100 and the first wire pattern 110 may include a first lower metal layer 122 and a first upper metal layer 124 .

In FIG. 20 , the space between the second wire pattern 210 and the substrate 100 may be smaller than the space between the first wire pattern 110 and the substrate 100 , but the substrate 100 and the second wire pattern ( The second gate electrode 220 between the 210 may include a second lower metal layer 222 and a second upper metal layer 224 .

In FIG. 20 , a distance by which the first inner spacers 142 are spaced apart between the first wire pattern 110 and the substrate 100 is a second inner spacer 242 between the second wire pattern 210 and the substrate 100 . Although shown to be substantially equal to the spaced apart distance, it is not limited thereto.

21 is a diagram for describing a semiconductor device according to some embodiments of the present invention. 22 is a diagram for describing a semiconductor device according to some embodiments of the present invention. 23 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. 24 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. For convenience of description, the points different from those described with reference to FIG. 20 will be mainly described.

Referring to FIG. 21 , in the semiconductor device according to some embodiments of the present disclosure, the number of metal layers included in the second gate electrode 220 may be different with respect to the second wire pattern 210 .

More specifically, the second gate electrode 220 may include a second lower metal layer 222 and a second upper metal layer 224 . However, the second gate electrode 220 between the second wire pattern 210 and the substrate 100 may include the second lower metal layer 222 but not the second upper metal layer 224 .

That is, the second upper metal layer 224 may not be formed between the second wire pattern 210 and the substrate 100 , but only the second lower metal layer 222 may be formed.

Referring to FIG. 3 , the second upper metal layer 224 is not formed between the second wire pattern 210 and the second fin-shaped protrusion 200P, but may be formed on the field insulating layer 105 .

Meanwhile, the first gate electrode 120 may include a first lower metal layer 122 and a first upper metal layer 124 . In addition, the first gate electrode 120 between the first wire pattern 110 and the substrate 100 may also include a first lower metal layer 122 and a first upper metal layer 124 .

Referring to FIG. 22 , in the semiconductor device according to some embodiments of the present disclosure, the first gate electrode 120 does not include an air gap, and the second gate electrode 220 includes the second gate electrode air gap 220g. may include

More specifically, the first gate electrode 120 between the first wire pattern 110 and the substrate 100 may not include an air gap. On the other hand, the second gate electrode air gap 220g may be formed between the second wire pattern 210 and the substrate 100 .

Since the second upper metal layer 224 is not formed between the second wire pattern 210 and the substrate 100 , the second gate electrode air gap 220g may be formed, but this is only exemplary and is limited thereto. it is not going to be

Referring to FIG. 3 , the second gate electrode air gap 220g may be formed between the second wire pattern 210 and the second fin-shaped protrusion 200P.

Referring to FIG. 23 , in the semiconductor device according to some embodiments of the present disclosure, a first source/drain air gap 150g may be formed between the first epitaxial pattern 150 and the first gate spacer 140 . have.

However, an air gap may not be formed between the second epitaxial pattern 250 and the second gate spacer 240 .

The first source/drain air gap 150g may be formed between the first inner spacer 142 and the first epitaxial pattern 150 .

Referring to FIG. 24 , in the semiconductor device according to some embodiments of the present disclosure, a first source/drain air gap 150g may be formed between the first epitaxial pattern 150 and the first gate spacer 140 . have.

Also, a second source/drain air gap 250g may be formed between the second epitaxial pattern 250 and the second gate spacer 240 .

The first source/drain air gap 150g is formed between the first inner spacer 142 and the first epitaxial pattern 150 , and the second source/drain air gap 250g is formed with the second inner spacer 242 . and the second epitaxial pattern 250 may be formed.

The size of the first source/drain air gap 150g is affected by the height of the first inner spacer 142 , and the size of the second source/drain air gap 250g is affected by the height of the second inner spacer 242 . may be affected

In addition, the size of the first source/drain air gap 150g is affected by which material the first epitaxial pattern 150 includes, and the size of the second source/drain air gap 250g is determined by the second epitaxial pattern 150 . What material the tactile pattern 250 includes may be affected.

25 is a schematic plan view for explaining a semiconductor device according to some embodiments of the present invention. 26 is a cross-sectional view taken along lines A - A and D - D of FIG. 25 . 27A and 27B are cross-sectional views taken along lines B - B and E - E of FIG. 25 . Points different from those described with reference to FIGS. 1 to 6C will be mainly described.

25 to 27B , in the semiconductor device according to some embodiments of the present invention, a third wire pattern 310 formed in the first region I and a fourth wire pattern 310 formed in the second region II 410) may be further included.

The third wire pattern 310 may be formed on the first wire pattern 110 . The third wire pattern 310 may be formed to be spaced apart from the first wire pattern 110 . The third wire pattern 310 may be formed to extend in the first direction X1. The third wire pattern 310 may vertically overlap the first wire pattern 110 .

The fourth wire pattern 410 may be formed on the second wire pattern 210 . The fourth wire pattern 410 may be formed to be spaced apart from the second wire pattern 210 . The fourth wire pattern 410 may be formed to extend in the second direction X2 . The fourth wire pattern 410 may vertically overlap the second wire pattern 210 .

Unlike FIG. 27A , in FIG. 27B , the width of the first wire pattern 110 in the third direction Y1 may be different from the width of the third wire pattern 310 in the third direction Y1 .

Similarly, a width of the second wire pattern 210 in the fourth direction Y2 may be different from a width of the fourth wire pattern 410 in the fourth direction Y2 .

In the semiconductor device according to some embodiments of the present invention, when the wire pattern includes an upper surface and a lower surface parallel to the upper surface of the substrate 100 , the width of the wire pattern will be described as meaning the width of the lower surface of the wire pattern.

For example, a width of the first wire pattern 110 in the third direction Y1 may be greater than a width of the third wire pattern 310 in the third direction Y1 . Also, a width of the second wire pattern 210 in the fourth direction Y2 may be greater than a width of the fourth wire pattern 410 in the fourth direction Y2 .

In other words, as the distance from the upper surface of the substrate 100 increases, the width of the wire pattern may decrease.

26 to 27B, two wire patterns are sequentially formed on the substrate 100 in the thickness direction of the substrate 100 in the first region I, and two wire patterns are formed in the second region II Although illustrated as being sequentially formed on the substrate 100 in the thickness direction of the substrate 100, it is only for convenience of description, and is not limited thereto.

On the substrate 100 of the first region (I), three or more wire patterns may be sequentially formed in the thickness direction of the substrate 100, and on the substrate 100 of the second region (II), 3 Of course, two or more wire patterns may be sequentially formed in the thickness direction of the substrate 100 .

The first gate spacers 140 defining the first trenches 140t may be formed at both ends of the first wire pattern 110 and the third wire pattern 310 . The first wire pattern 110 and the third wire pattern 310 may pass through the first gate spacer 140 . The first gate spacer 140 may be in full contact with the periphery of the end of the first wire pattern 110 and the end of the third wire pattern 310 .

The first inner spacer 142 may be disposed between the first pin-shaped protrusion 100P and the first wire pattern 110 and between the first wire pattern 110 and the third wire pattern 310 .

A second gate spacer 240 defining the second trench 240t may be formed at both ends of the second wire pattern 210 and the fourth wire pattern 410 . The second wire pattern 210 and the fourth wire pattern 410 may pass through the second gate spacer 240 . The second gate spacer 240 may entirely contact the end of the second wire pattern 210 and the circumference of the end of the fourth wire pattern 410 .

The second inner spacer 242 may be disposed between the second pin-shaped protrusion 200P and the second wire pattern 210 and between the second wire pattern 210 and the fourth wire pattern 410 .

The first gate insulating layer 130 may be formed along the circumference of the first wire pattern 110 and the circumference of the third wire pattern 310 . The first gate insulating layer 130 may surround the first wire pattern 110 and the third wire pattern 310 , respectively.

That is, the portion of the first gate insulating film 130 formed along the periphery of the first wire pattern 110 and the portion of the first gate insulating film 130 formed along the periphery of the third wire pattern 310 may be vertically spaced apart from each other. have.

The first gate insulating layer 130 may extend along sidewalls and bottom surfaces of the first trench 140t , the circumference of the first wire pattern 110 , and the circumference of the third wire pattern 310 .

The second gate insulating layer 230 may be formed along the circumference of the second wire pattern 210 and the circumference of the fourth wire pattern 410 . The second gate insulating layer 230 may surround the second wire pattern 210 and the fourth wire pattern 410 , respectively.

That is, the portion of the second gate insulating film 230 formed along the periphery of the second wire pattern 210 and the portion of the second gate insulating film 230 formed along the periphery of the fourth wire pattern 410 may be vertically spaced apart from each other. have.

The second gate insulating layer 230 may extend along sidewalls and bottom surfaces of the second trench 240t , the perimeter of the second wire pattern 210 , and the perimeter of the fourth wire pattern 410 .

The first gate electrode 120 may be formed on the first gate insulating layer 130 . The first gate electrode 120 may surround the first wire pattern 110 and the third wire pattern 310 . The first gate electrode 120 may cross the first wire pattern 110 and the third wire pattern 310 .

The first lower metal layer 122 may be formed on the first gate insulating layer 130 . The first lower metal layer 122 may be formed along a profile of the first gate insulating layer 130 .

The first lower metal layer 122 may be formed along the circumference of the first wire pattern 110 and the circumference of the third wire pattern 310 . The first lower metal layer 122 may cover the first gate insulating layer 130 formed along the outer peripheral surfaces of the first wire pattern 110 and the third wire pattern 310 .

26 to 27B , the first lower metal layer 122 surrounding the first wire pattern 110 and the first lower metal layer 122 surrounding the third wire pattern 310 may be spaced apart from each other.

The first upper metal layer 124 may be formed on the first lower metal layer 122 . The first upper metal layer 124 may fill the first trench 140t in which the first lower metal layer 122 is formed.

The first upper metal layer 124 may be interposed between the first wire pattern 110 and the third wire pattern 310 . The first upper metal layer 124 may be interposed between the first wire pattern 110 and the first fin-shaped protrusion 100P, that is, between the first wire pattern 110 and the substrate 100 .

That is, the first gate insulating layer 130 and the first lower metal layer 122 may be sequentially disposed around the first wire pattern 110 and the third wire pattern 310 , respectively. In addition, the first upper metal layer 124 surrounds each of the first wire patterns 110 and the third wire patterns 310 in which the first gate insulating layer 130 and the first lower metal layer 122 are sequentially disposed. can

The second gate electrode 220 may be formed on the second gate insulating layer 230 . The second gate electrode 220 may surround the second wire pattern 210 and the fourth wire pattern 410 . The second gate electrode 220 may cross the second wire pattern 210 and the fourth wire pattern 410 .

The second lower metal layer 222 may be formed on the second gate insulating layer 230 . The second lower metal layer 222 may be formed along a profile of the second gate insulating layer 230 .

The second lower metal layer 222 may be formed along the circumference of the second wire pattern 210 and the circumference of the fourth wire pattern 410 . The second lower metal layer 222 may surround the second gate insulating layer 230 formed along the outer peripheral surfaces of the second wire pattern 210 and the fourth wire pattern 410 .

26 to 27B , the second lower metal layer 222 surrounding the second wire pattern 210 and the second lower metal layer 222 surrounding the fourth wire pattern 410 may be spaced apart from each other.

The second upper metal layer 224 may be formed on the second lower metal layer 222 . The second upper metal layer 224 may fill the second trench 240t in which the second lower metal layer 222 is formed.

The second upper metal layer 224 may be interposed between the second wire pattern 210 and the fourth wire pattern 410 . The second upper metal layer 224 may be interposed between the second wire pattern 210 and the second fin-shaped protrusion 200P, that is, between the second wire pattern 210 and the substrate 100 .

That is, the second gate insulating layer 230 and the second lower metal layer 222 may be sequentially disposed around the second wire pattern 210 and the fourth wire pattern 410 , respectively. In addition, the second upper metal layer 224 surrounds each of the second wire patterns 210 and the fourth wire patterns 410 in which the second gate insulating film 230 and the second lower metal layer 222 are sequentially disposed. can

The first epitaxial pattern 150 may be disposed on both sides of the first wire pattern 110 and the third wire pattern 310 , and may be connected to the first wire pattern 110 and the third wire pattern 310 , respectively. .

The second epitaxial pattern 250 may be disposed on both sides of the second wire pattern 210 and the fourth wire pattern 410 , and may be connected to the second wire pattern 210 and the fourth wire pattern 410 , respectively. .

A width SW11 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the substrate 100 is a second It may be smaller than the width SW21 of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the wire pattern 210 and the substrate 100 .

In other words, the distance G11 by which the first gate spacer 140 is spaced apart between the first wire pattern 110 and the substrate 100 is the second gate space between the second wire pattern 210 and the substrate 100 . The spacer 240 may be greater than the spaced distance G21.

Since the spaced distance G11 of the first inner spacer 142 is greater than the spaced distance G21 of the second inner spacer 242 , the first gate between the first wire pattern 110 and the substrate 100 . The width W11 of the electrode 120 may be greater than the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 .

On the other hand, the height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is the second gate spacer 240 between the second wire pattern 210 and the substrate 100 . ) may be substantially equal to the height SH21.

Accordingly, the height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is the second gate electrode 220 between the second wire pattern 210 and the substrate 100 . ) may be substantially equal to the height h21.

In addition, the width SW11 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the substrate 100 is, a width SW12 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the third wire pattern 310; may be substantially the same.

A distance G11 by which the first gate spacer 140 is spaced apart between the first wire pattern 110 and the substrate 100 is a first gate spacer between the first wire pattern 110 and the third wire pattern 310 . 140 may be substantially equal to the spaced apart distance G12.

A height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is a height SH11 between the first wire pattern 110 and the third wire pattern 310 . 140 may be substantially equal to the height SH12.

Accordingly, the width W11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is the first between the first wire pattern 110 and the third wire pattern 310 . It may be substantially equal to the width W12 of the gate electrode 120 .

That is, the width W11 at which the first gate electrode 120 and the first wire pattern 110 overlap between the first wire pattern 110 and the substrate 100 is the width W11 between the first wire pattern 110 and the third The width W12 at which the first gate electrode 120 and the first wire pattern 110 overlap between the wire patterns 310 may be substantially the same.

The height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is the first gate electrode ( 120) may be substantially equal to the height h12.

In addition, the width SW21 of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the second wire pattern 210 and the substrate 100 is, a width SW22 of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the second wire pattern 210 and the fourth wire pattern 410; may be substantially the same.

A distance G21 by which the second gate spacer 240 is spaced apart between the second wire pattern 210 and the substrate 100 is a second gate spacer between the second wire pattern 210 and the fourth wire pattern 410 . 240 may be substantially equal to the spaced apart distance G22.

A height SH21 of the second gate spacer 240 between the second wire pattern 210 and the substrate 100 is a height SH21 between the second wire pattern 210 and the fourth wire pattern 410 . 240 may be substantially equal to the height SH22.

Accordingly, the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 is the second between the second wire pattern 210 and the fourth wire pattern 410 . It may be substantially equal to the width W22 of the gate electrode 220 .

That is, the width W21 at which the second gate electrode 220 and the second wire pattern 210 overlap between the second wire pattern 210 and the substrate 100 is the width W21 between the second wire pattern 210 and the fourth wire pattern 210 . The width W22 at which the second gate electrode 220 and the second wire pattern 210 overlap between the wire patterns 410 may be substantially the same.

The height h21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 is the second gate electrode ( ) between the second wire pattern 210 and the fourth wire pattern 410 . 220 ) may be substantially equal to the height h22 .

A distance G11 by which the first gate spacer 140 is spaced apart between the first wire pattern 110 and the substrate 100 is a first gate spacer between the first wire pattern 110 and the third wire pattern 310 . A distance G21 at which the second gate spacer 240 is spaced apart between the second wire pattern 210 and the substrate 100 is substantially the same as the distance G12 separated by 140 is the second wire pattern ( A distance G22 at which the second gate spacer 240 is spaced between the 210 and the fourth wire pattern 410 may be substantially the same.

Accordingly, the distance G12 by which the first gate spacer 140 is spaced apart between the first wire pattern 110 and the third wire pattern 310 is the second wire pattern 210 and the fourth wire pattern 410 . The second gate spacer 240 may be greater than the distance G22 separated therebetween.

In addition, the width SW12 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the third wire pattern 310 . ) is the width ( SW22).

Accordingly, the width W12 of the first gate electrode 120 between the first wire pattern 110 and the third wire pattern 310 is between the second wire pattern 210 and the fourth wire pattern 410 . may be greater than the width W22 of the second gate electrode 220 .

28 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. 29 is a view for explaining a semiconductor device according to some embodiments of the present invention. 30 is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of explanation, points different from those described with reference to FIGS. 25 to 27B will be mainly described.

Referring to FIG. 28 , in the semiconductor device according to some embodiments of the present disclosure, the thickness t1 of the first wire pattern 110 is different from the thickness t3 of the third wire pattern 310 and the second wire pattern The thickness t2 of the 210 may be different from the thickness t4 of the fourth wire pattern 410 .

The thicknesses of the first wire pattern 110 and the third wire pattern 310 stacked on the substrate 100 in the first region (I) are different from each other, and are stacked on the substrate 100 in the second region (II). The thicknesses of the second wire pattern 210 and the fourth wire pattern 410 may be different from each other.

For example, the thickness t1 of the first wire pattern 110 is thicker than the thickness t3 of the third wire pattern 310, and the thickness t2 of the second wire pattern 210 is the fourth wire pattern ( It may be thicker than the thickness t4 of the 410 .

In other words, as the distance from the upper surface of the substrate 100 increases, the thickness of each of the stacked wire patterns may decrease.

Referring to FIG. 29 , in the semiconductor device according to some embodiments of the present disclosure, the distance G11 by which the first gate spacer 140 is spaced apart between the first wire pattern 110 and the substrate 100 is the first wire The distance G12 separated by the first gate spacer 140 between the pattern 110 and the third wire pattern 310 may be greater than that of the first gate spacer 140 .

The width SW11 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the substrate 100 is a first It may be smaller than the width SW12 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the wire pattern 110 and the third wire pattern 310 . have.

In addition, a distance G21 by which the second gate spacer 240 is spaced apart between the second wire pattern 210 and the substrate 100 is a second distance G21 between the second wire pattern 210 and the fourth wire pattern 410 . The gate spacer 240 may be greater than the spaced distance G22.

A width SW21 of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the second wire pattern 210 and the substrate 100 is a second It may be smaller than the width SW22 of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the wire pattern 210 and the fourth wire pattern 410 . have.

Accordingly, the width W11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is the first between the first wire pattern 110 and the third wire pattern 310 . It may be larger than the width W12 of the gate electrode 120 .

That is, the width W11 at which the first gate electrode 120 and the first wire pattern 110 overlap between the first wire pattern 110 and the substrate 100 is the width W11 between the first wire pattern 110 and the third The overlapping width W12 between the first gate electrode 120 and the first wire pattern 110 between the wire patterns 310 may be greater.

The width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 is the second gate electrode (W21) between the second wire pattern 210 and the fourth wire pattern 410 . 220 may be greater than the width W22.

That is, the width W21 at which the second gate electrode 220 and the second wire pattern 210 overlap between the second wire pattern 210 and the substrate 100 is the width W21 between the second wire pattern 210 and the fourth wire pattern 210 . The overlapping width W22 between the second gate electrode 220 and the second wire pattern 210 between the wire patterns 410 may be greater.

In other words, as the distance from the top surface of the substrate 100 increases, the width of the first inner spacer 142 and the width of the second inner spacer 242 may increase, respectively.

On the other hand, as the distance from the top surface of the substrate 100 increases, the distance between the first inner spacers 142 and the distance between the second inner spacers 242 may decrease, respectively.

Referring to FIG. 30 , the height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is between the first wire pattern 110 and the third wire pattern 310 . It may be greater than the height SH12 of the first gate spacer.

In addition, the height SH21 of the second gate spacer 240 between the second wire pattern 210 and the substrate 100 is between the second wire pattern 210 and the fourth wire pattern 410 . It may be greater than the height SH22.

In other words, as the distance from the upper surface of the substrate 100 increases, the height of the first inner spacer 142 and the height of the second inner spacer 242 may increase, respectively.

Accordingly, the height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is the first between the first wire pattern 110 and the third wire pattern 310 . It may be greater than the height h12 of the gate electrode 120 .

The height h21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 is the second gate electrode ( ) between the second wire pattern 210 and the fourth wire pattern 410 . 220) may be greater than the height h22.

In addition, the height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is the first gate between the first wire pattern 110 and the third wire pattern 310 . Although greater than the height h12 of the electrode 120 , the first gate electrode 120 and the first wire pattern 110 and the third wire pattern 310 are disposed between the first wire pattern 110 and the substrate 100 . The interposed first gate electrode 120 may include a first lower metal layer 122 and a first upper metal layer 124 sequentially stacked on the first wire pattern 110 , respectively.

Similarly, the second gate electrode 220 between the second wire pattern 210 and the substrate 100 and the second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 are respectively It may include a second lower metal layer 222 and a second upper metal layer 224 sequentially stacked on the second wire pattern 210 .

31 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. 32 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, the points different from those described with reference to FIG. 30 will be mainly described.

Referring to FIG. 31 , in the semiconductor device according to some embodiments of the present disclosure, the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is sequentially formed on the first wire pattern 110 . It may include a first lower metal layer 122 and a first upper metal layer 124 that are stacked with each other.

However, the first gate electrode 120 between the first wire pattern 110 and the third wire pattern 310 may include the first lower metal layer 122 but not the first upper metal layer 124 . have.

Similarly, the second gate electrode 220 between the second wire pattern 210 and the substrate 100 has a second lower metal layer 222 and a second upper metal layer ( 224) may be included.

However, the second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 may include the second lower metal layer 222 but not the second upper metal layer 224 . have.

That is, the first upper metal layer 124 may not be formed between the first wire pattern 110 and the third wire pattern 310 , but only the first lower metal layer 122 may be formed. Also, the second upper metal layer 224 may not be formed between the second wire pattern 210 and the fourth wire pattern 410 , and only the second lower metal layer 222 may be formed.

27A , the first upper metal layer 124 is not formed between the first wire pattern 110 and the third wire pattern 310 , but may be formed on the field insulating layer 105 . The second upper metal layer 224 is not formed between the second wire pattern 210 and the fourth wire pattern 410 , but may be formed on the field insulating layer 105 .

The height SH12 of the first gate spacer between the first wire pattern 110 and the third wire pattern 310 is the height of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 . Since it is smaller than SH11 , a space in which the first upper metal layer 124 is formed may be insufficient between the first wire pattern 110 and the third wire pattern 310 .

The second upper metal layer 224 may not be formed between the second wire pattern 210 and the fourth wire pattern 410 for the same reason as described above.

Referring to FIG. 32 , in the semiconductor device according to some embodiments of the present disclosure, the first gate electrode 120 between the first wire pattern 110 and the substrate 100 does not include an air gap, but the first wire The first gate electrode 120 between the pattern 110 and the third wire pattern 310 may include a first gate electrode air gap 120g.

In addition, although the second gate electrode 220 between the second wire pattern 210 and the substrate 100 does not include an air gap, the second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 does not include an air gap. The gate electrode 220 may include a second gate electrode air gap 220g.

33 is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of explanation, the points different from those described with reference to FIGS. 25 to 27B will be mainly described.

Referring to FIG. 33 , in the semiconductor device according to some embodiments of the present disclosure, the height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is the second wire pattern. The height SH21 of the second gate spacer 240 between the 210 and the substrate 100 may be greater.

In addition, the height SH12 of the first gate spacer 140 between the first wire pattern 110 and the third wire pattern 310 is between the second wire pattern 210 and the fourth wire pattern 410 . It may be greater than the height SH22 of the second gate spacer 240 .

Accordingly, the height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is the second gate electrode 220 between the second wire pattern 210 and the substrate 100 . ) is greater than the height h21. In addition, the height h12 of the first gate electrode 120 between the first wire pattern 110 and the third wire pattern 310 is the second between the second wire pattern 210 and the fourth wire pattern 410 . 2 It is greater than the height h22 of the gate electrode 220 .

34 is a diagram for describing a semiconductor device according to some embodiments of the present invention. 35 is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of explanation, the points different from those described with reference to FIG. 33 will be mainly described.

Referring to FIG. 34 , in the semiconductor device according to some embodiments of the present disclosure, the second gate electrode 220 includes a second lower metal layer 222 sequentially stacked on the second gate insulating layer 230 , and a second An upper metal layer 224 may be included.

However, the second gate electrode 220 between the second wire pattern 210 and the substrate 100 and the second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 are The second lower metal layer 222 may be included, but the second upper metal layer 224 may not be included.

Meanwhile, the first gate electrode 120 may include a first lower metal layer 122 and a first upper metal layer 124 sequentially stacked on the first gate insulating layer 130 .

The first gate electrode 120 between the first wire pattern 110 and the substrate 100 and the first gate electrode 120 between the first wire pattern 110 and the third wire pattern 310 are also It may include a lower metal layer 122 and a first upper metal layer 124 .

Referring to FIG. 35 , in the semiconductor device according to some embodiments of the present disclosure, the first gate electrode 120 does not include an air gap, and the second gate electrode 220 includes a second gate electrode air gap 220g. may include

The second gate electrode air gap 220g may be formed between the second wire pattern 210 and the substrate 100 and between the second wire pattern 210 and the fourth wire pattern 410 .

Since the second upper metal layer 224 is not formed between the second wire pattern 210 and the substrate 100 and between the second wire pattern 210 and the fourth wire pattern 410 , the second gate electrode air The gap 220g may be formed, but is not limited thereto.

36 to 46 are intermediate steps for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.

For reference, FIGS. 37A and 38A are cross-sectional views taken along lines G - G and I - I of FIG. 36 . 37B and 38B are cross-sectional views taken along lines H - H and J - J of FIG. 36 .

36 to 37B , a substrate 100 including a first region I and a second region II may be provided.

Subsequently, a sacrificial layer 2001 and an active layer 2002 may be sequentially formed on the substrate 100 . The sacrificial layer 2001 and the active layer 2002 may be formed using, for example, an epitaxial growth method.

The active layer 2002 may include a material having an etch selectivity with respect to the sacrificial layer 2001 .

In FIG. 36 , the active film 2002 and the sacrificial film 2001 are illustrated as having two layers, respectively, but for convenience of description, the present invention is not limited thereto. In addition, although the active film 2002 is shown as being positioned on the top, the present invention is not limited thereto.

Subsequently, first mask patterns 2101 may be respectively formed on the sacrificial layer 2001 in the first region I and the second region II.

In the first region I, the first mask pattern 2101 may extend in the first direction X1. In the second region II, the first mask pattern 2101 may extend in the second direction X2.

38A and 38B , an etching process may be performed using the first mask pattern 2101 as a mask to form a first fin-type structure F1 and a second fin-type structure F2 .

The first fin-shaped structure F1 may be formed in the first region I. The first fin-shaped structure F1 includes a first fin-shaped protrusion 100P sequentially stacked on the substrate 100 , a first sacrificial pattern 111 , a first active pattern 112 , and a first sacrificial pattern ( 111 ) and a first active pattern 112 .

The second fin-shaped structure F2 may be formed in the second region II. The second fin-shaped structure F2 includes a second fin-shaped protrusion 200P sequentially stacked on the substrate 100 , a second sacrificial pattern 211 , a second active pattern 212 , and a second sacrificial pattern ( 211 , and a second active pattern 212 .

In FIG. 38B , except for the sacrificial film 2001 used to form the first fin-shaped structure F1 and the second fin-shaped structure F2 , all of the sacrificial films on the substrate 100 are illustrated as being removed, but for convenience of explanation for, but not limited to.

Subsequently, a field insulating layer 105 covering at least a portion of the sidewall of the first fin-shaped structure F1 and the sidewall of the second fin-shaped structure F2 may be formed on the substrate 100 .

During the process of forming the field insulating layer 105 , the first mask pattern 2101 may be removed.

Subsequently, a first dummy gate electrode 120P crossing the first fin-type structure F1 and extending in the third direction Y1 may be formed in the first region I.

In addition, a second dummy gate electrode 220P that crosses the second fin-type structure F2 and extends in the fourth direction Y2 may be formed in the second region II.

The first dummy gate electrode 120P and the second dummy gate electrode 220P may be formed using the second mask pattern 2102 .

Between the first dummy gate electrode 120P and the first fin structure F1 and between the second dummy gate electrode 220P and the second fin structure F2, the first dummy gate insulating layer 130P and the second dummy A gate insulating layer 230P may be formed.

A first free gate spacer 140P may be formed on a sidewall of the first dummy gate electrode 120P. A second free gate spacer 240P may be formed on a sidewall of the second dummy gate electrode 220P.

The following description will be given with reference to FIG. 38A.

Referring to FIG. 39 , a third mask pattern 2103 is formed on the second region II. The first region I not covered by the third mask pattern 2103 is exposed.

It goes without saying that the third mask pattern 2103 may be formed along the profiles of the second fin-type structure F2 and the second dummy gate electrode 120P, unlike the illustrated ones.

Subsequently, a portion of the first fin-type structure F1 may be removed by using the first dummy gate electrode 120P and the first free gate spacer 140P as a mask.

Accordingly, first recesses 150r may be formed on both sides of the first dummy gate electrode 120P and the first free gate spacer 140P.

Referring to FIG. 40 , a first inner spacer 142 is formed between the first active pattern 112 and the first fin-shaped protrusion 100P. A first inner spacer 142 is also formed between the first active patterns 112 on the first fin-shaped protrusion 100P.

Specifically, a portion of the first sacrificial pattern 111 may be removed using an etch selectivity between the first active pattern 112 and the first sacrificial pattern 111 .

Next, a first inner spacer 142 may be formed in a portion from which a portion of the first sacrificial pattern 111 is removed.

Referring to FIG. 41 , a first epitaxial pattern 150 may be formed in the first recess 150r.

The first epitaxial pattern 150 may be included in the raised source/drain.

Subsequently, the third mask pattern 2103 formed in the second region II may be removed.

Referring to FIG. 42 , a fourth mask pattern 2104 is formed on the first region (I). The second region II not covered by the fourth mask pattern 2104 is exposed.

Unlike the drawings, the fourth mask pattern 2104 may be formed along the profiles of the first epitaxial pattern 150 and the second dummy gate electrode 120P.

Subsequently, a portion of the second fin-type structure F2 may be removed by using the second dummy gate electrode 220P and the second free gate spacer 240P as a mask.

Accordingly, second recesses 250r may be formed on both sides of the second dummy gate electrode 220P and the second free gate spacer 240P.

Referring to FIG. 43 , a second inner spacer 242 is formed between the second active pattern 212 and the second fin-shaped protrusion 200P. A second inner spacer 242 is also formed between the second active patterns 212 on the second fin-shaped protrusion 200P.

Specifically, a portion of the second sacrificial pattern 211 may be removed using an etch selectivity between the second active pattern 212 and the second sacrificial pattern 211 .

Next, a second inner spacer 242 may be formed in a portion from which a portion of the second sacrificial pattern 211 is removed.

In this case, the width of the second inner spacer 242 may be greater than the width of the first inner spacer 142 .

Referring to FIG. 44 , a second epitaxial pattern 150 may be formed in the second recess 250r.

Subsequently, the fourth mask pattern 2104 formed in the first region I may be removed.

Referring to FIG. 45 , an interlayer insulating layer 190 covering the first epitaxial pattern 150 and the second epitaxial pattern 250 may be formed on the substrate 100 .

The first dummy gate electrode 120P and the second dummy gate electrode 220P may be exposed by the interlayer insulating layer 190 .

While forming the interlayer insulating layer 190 , the second mask pattern 2102 may be removed. Also, while the insulating interlayer 190 is being formed, the first outer spacers 141 and the second outer spacers 241 may be respectively formed.

Referring to FIG. 46 , the first dummy gate electrode 120P, the first dummy gate insulating layer 130P, and the first sacrificial pattern 111 are removed on the substrate 100 in the first region I. A first wire pattern 110 and a third wire pattern 310 may be formed.

In addition, by removing the second dummy gate electrode 220P, the second dummy gate insulating layer 230P, and the second sacrificial pattern 211 , the second wire pattern is formed on the substrate 100 in the second region II. 210 and a fourth wire pattern 410 may be formed.

The first wire pattern 110 is formed to be spaced apart from the first fin-shaped protrusion 100P, and the third wire pattern 310 is formed to be spaced apart from the first wire pattern 110 .

In addition, the second wire pattern 210 is formed to be spaced apart from the second pin-shaped protrusion 200P, and the fourth wire pattern 410 is formed to be spaced apart from the second wire pattern 210 .

In addition, by removing the first dummy gate electrode 120P, the first dummy gate insulating layer 130P, and the first sacrificial pattern 111 , the first trench 140t defined by the first gate spacer 140 is is formed

In addition, by removing the second dummy gate electrode 220P, the second dummy gate insulating layer 230P, and the second sacrificial pattern 211 , the second trench 240t defined by the second gate spacer 240 is is formed

Subsequently, a first gate insulating layer 130 and a first gate electrode 120 are formed in the first trench 140t. In addition, a second gate insulating layer 230 and a second gate electrode 220 are formed in the second trench 240t.

47 is a block diagram of an SoC system including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 47 , the SoC system 1000 includes an application processor 1001 and a DRAM 1060 .

The application processor 1001 may include a central processing unit 1010 , a multimedia system 1020 , a bus 1030 , a memory system 1040 , and a peripheral circuit 1050 .

The central processing unit 1010 may perform an operation necessary for driving the SoC system 1000 . In some embodiments of the present invention, the central processing unit 1010 may be configured as a multi-core environment including a plurality of cores.

The multimedia system 1020 may be used to perform various multimedia functions in the SoC system 1000 . The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like. .

The bus 1030 may be used for data communication between the central processing unit 1010 , the multimedia system 1020 , the memory system 1040 , and the peripheral circuit 1050 . In some embodiments of the present invention, such bus 1030 may have a multi-layer structure. Specifically, as an example of the bus 1030 , a multi-layer advanced high-performance bus (AHB) or a multi-layer advanced eXtensible interface (AXI) may be used, but the present invention is not limited thereto.

The memory system 1040 may provide an environment necessary for the application processor 1001 to be connected to an external memory (eg, the DRAM 1060) to operate at a high speed. In some embodiments of the present invention, the memory system 1040 may include a separate controller (eg, a DRAM controller) for controlling an external memory (eg, the DRAM 1060).

The peripheral circuit 1050 may provide an environment necessary for the SoC system 1000 to be smoothly connected to an external device (eg, a main board). Accordingly, the peripheral circuit 1050 may include various interfaces that allow an external device connected to the SoC system 1000 to be compatible.

The DRAM 1060 may function as a working memory required for the application processor 1001 to operate. In some embodiments of the present invention, the DRAM 1060 may be disposed outside the application processor 1001 as shown. Specifically, the DRAM 1060 may be packaged with the application processor 1001 in a package on package (PoP) format.

At least one of the components of the SoC system 1000 may include at least one of the semiconductor devices according to the embodiments of the present invention described above.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains can realize that the present invention can be embodied in other specific forms without changing its technical spirit or essential features. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate 105: field insulating film
110, 210, 310, 410: wire pattern 120, 220: gate electrode
122, 222: lower metal layer 124, 224: upper metal layer
130, 230: gate insulating film 140, 240: gate spacer
141, 241: outer spacer 142, 242: inner spacer
150, 250: epitaxial pattern

Claims (20)

a substrate comprising a first region and a second region;
a first wire pattern on the substrate in the first region and spaced apart from the substrate;
a second wire pattern on the substrate in the second region, the second wire pattern being spaced apart from the substrate and the first wire pattern;
a first gate electrode crossing the first wire pattern and overlapping the first wire pattern by a first width;
a second gate electrode crossing the second wire pattern and overlapping the second wire pattern by a second width different from a first width;
first gate spacers positioned at both ends of the first wire pattern;
a second gate spacer positioned at both ends of the second wire pattern;
a first epitaxial pattern disposed on both sides of the first wire pattern; and
and a second epitaxial pattern disposed on both sides of the second wire pattern,
the first gate electrode is disposed between the first gate spacers;
the second gate electrode is disposed between the second gate spacers;
A width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the substrate and the first wire pattern is the width of the second epitaxial pattern between the substrate and the second wire pattern. A semiconductor device having a width different from a width of the second gate spacer interposed between the pattern and the second gate electrode. According to claim 1,
The first width is a width at which the first gate electrode and the first wire pattern overlap between the first wire pattern and the substrate;
The second width is a width at which the second gate electrode and the second wire pattern overlap between the second wire pattern and the substrate. delete delete According to claim 1,
the first gate spacer defines a first trench, and the second gate spacer defines a second trench;
A first gate insulating layer extending along a sidewall of the first trench and a circumference of the first wire pattern, and a second gate insulating layer extending along a sidewall of the second trench and a circumference of the second wire pattern semiconductor device. According to claim 1,
a third wire pattern intersecting the first gate electrode on the first wire pattern in the first region;
The semiconductor device further comprising a fourth wire pattern intersecting the second gate electrode on the second wire pattern in the second region. 7. The method of claim 6,
The overlapping width of the first gate electrode and the first wire pattern between the first wire pattern and the substrate is between the first gate electrode and the first wire between the first wire pattern and the third wire pattern. substantially equal to the overlapping width of the pattern,
The overlapping width of the second gate electrode and the second wire pattern between the second wire pattern and the substrate is between the second gate electrode and the second wire between the second wire pattern and the fourth wire pattern. A semiconductor device substantially equal to the width over which the patterns overlap. 7. The method of claim 6,
The overlapping width of the first gate electrode and the first wire pattern between the first wire pattern and the substrate is between the first gate electrode and the first wire between the first wire pattern and the third wire pattern. larger than the overlapping width of the pattern,
The overlapping width of the second gate electrode and the second wire pattern between the second wire pattern and the substrate is between the second gate electrode and the second wire between the second wire pattern and the fourth wire pattern. A semiconductor device that is greater than the width over which the patterns overlap. a substrate comprising a first region and a second region;
a first wire pattern on the substrate in the first region and spaced apart from the substrate;
a second wire pattern on the first wire pattern, the second wire pattern being spaced apart from the first wire pattern;
a third wire pattern on the substrate in the second region and spaced apart from the substrate;
a fourth wire pattern on the third wire pattern, the fourth wire pattern being spaced apart from the third wire pattern;
a first gate spacer positioned at both ends of the first wire pattern and the second wire pattern;
With second gate spacers positioned at both ends of the third wire pattern and the fourth wire pattern, a distance by which the second gate spacer is spaced apart between the third wire pattern and the fourth wire pattern is the first wire pattern and a second gate spacer that is smaller than a distance between the second wire patterns by which the first gate spacer is spaced apart;
a first gate electrode intersecting the first wire pattern and the second wire pattern between the first gate spacers;
a second gate electrode intersecting the third wire pattern and the fourth wire pattern between the second gate spacers;
a first epitaxial pattern disposed on both sides of the first gate electrode; and
a second epitaxial pattern disposed on both sides of the second gate electrode;
A width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the second wire pattern is between the third wire pattern and the fourth wire pattern. in a semiconductor device that is smaller than a width of the second gate spacer interposed between the second epitaxial pattern and the second gate electrode. delete 10. The method of claim 9,
A width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the substrate is a width of the second epitaxial pattern between the third wire pattern and the substrate. A semiconductor device having a width smaller than a width of the second gate spacer interposed between the pattern and the second gate electrode. 10. The method of claim 9,
A width of the first gate electrode between the first wire pattern and the second wire pattern is greater than a width of the second gate electrode between the third wire pattern and the fourth wire pattern. 10. The method of claim 9,
A width of the first gate electrode between the first wire pattern and the second wire pattern is substantially the same as a width of the first gate electrode between the first wire pattern and the substrate;
A width of the second gate electrode between the third wire pattern and the fourth wire pattern is substantially the same as a width of the second gate electrode between the third wire pattern and the substrate. 10. The method of claim 9,
A width of the first gate electrode between the first wire pattern and the second wire pattern is smaller than a width of the first gate electrode between the first wire pattern and the substrate;
A width of the second gate electrode between the third wire pattern and the fourth wire pattern is smaller than a width of the second gate electrode between the third wire pattern and the substrate. 10. The method of claim 9,
A height of the first gate electrode between the first wire pattern and the substrate is substantially the same as a height of the first gate electrode between the first wire pattern and the second wire pattern,
A height of the second gate electrode between the third wire pattern and the substrate is substantially the same as a height of the second gate electrode between the third wire pattern and the fourth wire pattern. 10. The method of claim 9,
A height of the first gate electrode between the first wire pattern and the substrate is greater than a height of the first gate electrode between the first wire pattern and the second wire pattern;
A height of the second gate electrode between the third wire pattern and the substrate is greater than a height of the second gate electrode between the third wire pattern and the fourth wire pattern. a substrate comprising a first region and a second region;
a first wire pattern on the substrate in the first region and spaced apart from the substrate;
a second wire pattern on the substrate in the second region and spaced apart from the substrate;
first gate spacers positioned at both ends of the first wire pattern;
a second gate spacer positioned at both ends of the second wire pattern;
a first gate electrode intersecting the first wire pattern between the first gate spacers;
a second gate electrode intersecting the second wire pattern between the second gate spacers;
a first epitaxial pattern disposed on both sides of the first gate electrode and connected to the first wire pattern; and
a second epitaxial pattern disposed on both sides of the second gate electrode and connected to the second wire pattern;
A width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the substrate is a width of the second epitaxial space between the second wire pattern and the substrate. A semiconductor device having a width different from a width of the second gate spacer interposed between the pattern and the second gate electrode. a substrate comprising a first region and a second region;
a first wire pattern on the substrate in the first region and spaced apart from the substrate;
a second wire pattern on the substrate in the second region and spaced apart from the substrate;
first gate spacers positioned at both ends of the first wire pattern;
a second gate spacer positioned at both ends of the second wire pattern;
a first gate electrode intersecting the first wire pattern between the first gate spacers;
a second gate electrode intersecting the second wire pattern between the second gate spacers;
a first epitaxial pattern disposed on both sides of the first gate electrode and connected to the first wire pattern; and
a second epitaxial pattern disposed on both sides of the second gate electrode and connected to the second wire pattern;
A height of the first gate spacer between the first wire pattern and the substrate is greater than a height of the second gate spacer between the second wire pattern and the substrate;
A width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the substrate is a width of the second epitaxial space between the second wire pattern and the substrate. A semiconductor device having a width different from a width of the second gate spacer interposed between the pattern and the second gate electrode. a substrate comprising a first region and a second region;
a first wire pattern on the substrate in the first region and spaced apart from the substrate;
a second wire pattern on the substrate in the second region and spaced apart from the substrate;
first gate spacers positioned at both ends of the first wire pattern;
a second gate spacer positioned at both ends of the second wire pattern;
a first gate electrode intersecting the first wire pattern between the first gate spacers;
a second gate electrode intersecting the second wire pattern between the second gate spacers;
a first epitaxial pattern disposed on both sides of the first gate electrode and connected to the first wire pattern; and
a second epitaxial pattern disposed on both sides of the second gate electrode and connected to the second wire pattern;
The thickness of the first wire pattern is constant as it moves away from the first gate spacer in the longitudinal cross-section of the first wire pattern,
In a longitudinal cross-section of the second wire pattern, the first wire pattern includes a first portion having a first thickness and a second portion having a second thickness smaller than the first thickness, 1 part is disposed on both sides around the second part of the first wire pattern,
A width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the substrate is a width of the second epitaxial space between the second wire pattern and the substrate. A semiconductor device having a width different from a width of the second gate spacer interposed between the pattern and the second gate electrode. a substrate comprising a first region and a second region;
a first wire pattern spaced apart from the substrate on the substrate in the first region and extending in a first direction;
a second wire pattern spaced apart from the substrate and the first wire pattern on the substrate in the second region and extending in a second direction;
first gate spacers positioned at both ends of the first wire pattern;
a second gate spacer positioned at both ends of the second wire pattern;
a first gate insulating layer extending along sidewalls of the first gate spacer and a circumference of the first wire pattern;
a second gate insulating layer extending along a sidewall of the second gate spacer and a circumference of the second wire pattern, the second gate insulating layer having a thickness different from that of the first gate insulating layer;
A first gate on the first gate insulating layer that crosses the first wire pattern and extends in a third direction intersecting the first direction, and overlaps the first wire pattern with the first wire pattern by a first width in the first direction electrode; and
A second gate on the second gate insulating layer that intersects the second wire pattern and extends in a fourth direction intersecting the first direction and overlaps the second wire pattern by a second width in the second direction A semiconductor device comprising an electrode.

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