KR102364098B1 - Organic Light Emitting Diode Display Device - Google Patents

Abstract

An organic light emitting diode display according to the present invention includes pixels and a shift register for driving transistors disposed in the pixels. Each pixel includes a driving transistor, a scan transistor, a sense transistor, and a storage capacitor. The driving transistor controls the driving current supplied to the organic light emitting diode. The scan transistor is connected between the gate electrode of the driving transistor and the data line, and is switched by the scan signal. The sense transistor is connected between the source electrode of the driving transistor and the initialization line, and is switched by the sense signal. The storage capacitor is connected between the gate electrode and the source electrode of the driving transistor. The shift register sequentially applies a scan signal to a sense signal stage that simultaneously applies a sense signal to pixels arranged in k (k being a natural number) adjacent to each other and to pixels arranged in k adjacent to each other in horizontal lines. and a scan signal stage that

Description

Organic Light Emitting Diode Display Device

The present invention relates to an organic light emitting diode display.

Flat panel displays (FPDs) are widely used in portable computers such as notebook computers and PDAs, mobile phone terminals, etc. as well as monitors of desktop computers due to their advantages in miniaturization and weight reduction. Such a flat panel display device is a liquid crystal display device; LCD), Plasma Display Panel (PDP), Field Emission Display; FED) and organic light emitting diode display (OLED).

Among them, the organic light emitting diode display has the advantages of fast response speed, high luminance efficiency, high luminance, and a large viewing angle. In general, an organic light emitting diode display uses a transistor turned on by a scan signal to apply a data voltage to a gate electrode of a driving transistor, and charges the data voltage supplied to the driving transistor to a storage capacitor. Then, the organic light emitting diode emits light by outputting the data voltage charged in the storage capacitor using the light emission control signal.

Although the organic light emitting diode display displays a gray level corresponding to a data voltage, a desired gray level may not be displayed due to variations in threshold voltage or mobility of the driving transistor. To improve this, the organic light emitting diode display may use a method of sensing a threshold voltage or mobility of a driving transistor and compensating for a data voltage based thereon. A sense transistor for switching a path for sensing a threshold voltage or mobility operates in response to a sense signal.

The scan signal for applying the data voltage and the sense signal for switching the sense transistor are sometimes implemented in the form of a gate-in-panel (GIP) in the bezel area of the display panel.

Recently, methods for reducing the bezel area have been sought according to the user's request, but it is not easy to reduce the bezel size due to the GIP circuit part.

An object of the present invention is to provide an organic light emitting diode display capable of reducing a bezel area.

In order to achieve the above object, an organic light emitting diode display device according to the present invention includes pixels and a shift register for driving transistors disposed in the pixels. Each pixel includes a driving transistor, a scan transistor, a sense transistor, and a storage capacitor. The driving transistor controls the driving current supplied to the organic light emitting diode. The scan transistor is connected between the gate electrode of the driving transistor and the data line, and is switched by the scan signal. The sense transistor is connected between the source electrode of the driving transistor and the initialization line, and is switched by the sense signal. The storage capacitor is connected between the gate electrode and the source electrode of the driving transistor. The shift register sequentially applies a scan signal to a sense signal stage that simultaneously applies a sense signal to pixels arranged in k (k being a natural number) adjacent to each other and to pixels arranged in k adjacent to each other in horizontal lines. and a scan signal stage that

Since the organic light emitting diode display device according to the present invention simultaneously supplies a sense signal to pixels arranged in a plurality of horizontal lines using a sense signal stage implemented as a single stage, a sense signal stage for driving the entire display panel The number of stages can be reduced. As a result, the bezel area in which the sense signal stage is disposed can be reduced.

1 is a view showing the configuration of an organic light emitting diode display device according to the present invention.
2 is a diagram showing the configuration of a shift register according to the present invention.
FIG. 3 is a view showing the pixel structure shown in FIG. 1;
FIG. 4 is a view showing an embodiment of the shift register shown in FIG. 2;
5 is a diagram illustrating a driving signal applied to a pixel during an image display driving period;
6A and 6B are diagrams illustrating pixel operations in an image display driving period;
7 is a diagram illustrating a driving signal applied to a pixel in a sensing period;
8A and 8C are diagrams illustrating pixel operations in an external compensation driving period;

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of writing the specification, and may be different from the component names of the actual product.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a diagram showing the configuration of a display device according to the present invention. And Fig. 2 is a view showing a shift register according to the present invention, and Fig. 3 is a view showing a pixel structure according to the present invention.

1 to 3 , the organic light emitting diode display device according to the present invention includes a display panel 100 in which pixels P are arranged in a matrix form, a data driver 120 , a gate driver 130 and 140 , and a timing controller. (110) is provided.

The display panel 100 includes a display unit 100A in which pixels P are arranged to display an image, and a non-display unit 100B in which a shift register 140 is arranged and does not display an image.

The display unit 100A includes a plurality of pixels P, and displays an image based on a gray level displayed by each pixel P. The pixels P are arranged along first to n-th horizontal lines HL1 to HL[n].

Each pixel P is connected to a data line DL arranged along a column line and connected to a gate line GL arranged along a horizontal line HL. As shown in FIG. 3 , the gate line GL includes a scan line SCL and a sensing line SEL. In addition, each of the pixels P includes an organic light emitting diode OLED, a driving transistor DT, a scan transistor ST1, a sense transistor ST2, and a storage capacitor Cst. Each of the transistors DT, ST1, and ST2 may be implemented as a polycrystalline thin film transistor (hereinafter, referred to as a transistor) including a polycrystalline semiconductor layer. However, the present invention is not limited thereto, and the semiconductor layer of the transistor may be formed of amorphous silicon or polysilicon.

The timing controller 110 controls driving timings of the data driver 120 and the gate drivers 130 and 140 . To this end, the timing controller 110 rearranges digital video data RGB input from the outside to match the resolution of the display panel 100 and supplies it to the data driver 120 . In addition, the timing controller 110 controls the data driver 120 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The data control signal DDC for controlling the operation timing and the gate control signal GDC for controlling the operation timing of the gate drivers 130 and 140 are generated.

The data driving unit 120 is for driving the data line unit DL. To this end, the data driver 120 converts the digital video data RGB input from the timing controller 110 into an analog data voltage based on the data control signal DDC and supplies it to the data lines DL.

The scan drivers 130 and 140 include a level shifter 130 and a shift register 140 . The level shifter 130 is formed on a printed circuit board (not shown) connected to the display panel 100 in the form of an IC, and the shift register 140 is formed in a non-display area ( 100B) is formed in a gate-in-panel (GIP) method.

The level shifter 130 level-shifts the clock signals CLK and the start signal VST under the control of the timing controller 110 and supplies them to the shift register 140 . The shift register 140 is formed by a combination of a plurality of thin film transistors (hereinafter referred to as transistors) in the non-display area 100B of the display panel 100 by the GIP method.

Referring to FIG. 2 , the stage of the shift register 140 for driving the pixels Pj arranged on the j-th horizontal line and the pixels P[j+k] arranged on the (j+k)-th horizontal line Take a look at: The pixel Pj arranged on the j-th horizontal line includes a j-th scan line SCL[j] and a j-th sensing line SEL[j].

The shift register 140 for driving pixels arranged in k horizontal lines includes the j-th scan signal stage SCAN_STG[j] to the (j+k-1)th scan signal stage SCAN_STG[j+k-1]. ), and a j-th sense signal stage (SENSE_STG[j]).

The j-th scan signal stage SCAN_STG[j] generates the j-th scan signal SCAN[j] and applies it to the scan lines SCL[j] of the pixels Pj arranged on the j-th horizontal line. The (j+k-1)th scan signal stage (SCAN_STG[j+k-1]) generates a (j+k-1)th scan signal (SCAN[j+k-1]), which It is applied to the scan line SCL[j+k-1] of the pixels P[j+k-1] disposed on the -1)th horizontal line. And, the j-th scan signal stage SCAN_STG[j] to the (j+k-1)-th scan signal stage SCAN_STG[j+k-1] are the j-th scan lines SCL[j] to (j+). A scan signal is sequentially applied to the k-1)th scan line (SCL[j+k-1]).

The j-th sense signal stage SENSE_STG[j] generates the j-th sense signal SENSE[j], which is used for the sense lines SEL[j] of the pixels P[j] arranged on the j-th horizontal line. It is simultaneously supplied to the sense lines SEL[j+k-1] of the pixels (j+k-1) arranged on the (j+k-1)-th horizontal line.

As described above, the pixels Pj, Pj+k-1 arranged in k horizontal lines use the same sense signal. If, in order to apply sense signals having different timings to each horizontal line, the number of sense signal stages must correspond to the number of horizontal lines. In contrast, in the present invention, since one sense signal stage is required to apply the sense signal to k horizontal lines, the number of sense signal stages can be reduced to 1/k. As a result, according to the present invention, the total area of the shift register 140 can be reduced, and the bezel area of the non-display unit 100B can be reduced by that much.

FIG. 3 is a diagram illustrating the pixel structure shown in FIG. 1 and the connection between the pixel and the data driver.

Referring to FIG. 3 , each pixel P includes an organic light emitting diode OLED, a driving transistor DT, a scan transistor ST1 , a sense transistor ST2 , and a storage capacitor Cst.

The organic light emitting diode OLED emits light by a driving current supplied from the driving transistor DT. A multi-layered organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). The anode electrode of the organic light emitting diode OLED is connected to the source electrode of the driving transistor DT, and the cathode electrode is connected to the ground terminal VSS.

The driving transistor DT controls the driving current Ioled flowing through the organic light emitting diode OLED according to the gate-source voltage Vgs. The driving transistor DT has a gate electrode connected to a first node N1 , a drain electrode connected to a high potential voltage VDD input terminal, and a source electrode connected to a second node N2 .

The storage capacitor Cst is connected between the first node N1 and the second node N2 to maintain the data voltage received from the data line DL for one frame.

The scan transistor ST1 is switched according to the scan signal SCAN to control the potential of the first node N1 . The scan transistor ST1 includes a gate electrode connected to the scan line SCL, a drain electrode connected to the data line DL, and a source electrode connected to the first node N1 .

The sense transistor ST2 is switched according to the sense signal SENSE to control the potential of the second node N2. The gate electrode of the sense transistor ST2 is connected to the sensing line SEL, the drain electrode of the sense transistor ST2 is connected to the second node N2, and the source electrode of the sense transistor ST2 is connected to the initialization voltage Vinit. ) is connected to the input terminal.

Each of the pixels P is connected to the data driver 120 through the data line DL and the initialization line INL. The data driver 120 includes a digital-to-analog converter (hereinafter 'DAC'), an analog-to-digital converter (hereinafter 'ADC'), and first and second switches SW1 and SW2. ), etc.

The DAC converts digital data input from the timing controller 110 into an analog data voltage Vdata and outputs the converted digital data to the data line DL. The first switch SW1 switches the current flow between the initialization voltage Vini input terminal and the initialization line INL. The second switch SW2 switches the current flow between the initialization line INL and the ADC. The ADC converts the analog sensing voltage Vsen into a digital value and supplies it to the timing controller 110 .

Hereinafter, a pixel operation according to the present invention will be described.

FIG. 4 shows an embodiment of a shift register that applies a sense signal in common to pixels arranged in two horizontal lines adjacent to a sensing stage when k is 1 in FIG. 2 . 5 is a diagram illustrating timing of a driving signal for driving an image display, and FIGS. 6A and 6B are diagrams illustrating an operation state of a pixel according to a driving signal.

Referring to FIG. 4 , a stage of the shift register 140 for driving the pixels Pj arranged on the j-th horizontal line and the pixels P[j+1] arranged on the (j+1)-th horizontal line Take a look at:

As shown in FIG. 4 , the shift register 140 for driving pixels arranged in two adjacent horizontal lines includes a jth scan signal stage SCAN_STG[j] and a (j+1)th scan signal stage SCAN_STG[ j+1]) and a j-th sense signal stage SENSE_STG[j].

The j-th scan signal stage SCAN_STG[j] generates the j-th scan signal SCAN[j] and applies it to the scan lines SCL[j] of the pixels Pj disposed on the j-th horizontal line. The (j+1)-th scan signal stage SCAN_STG[j+1] generates the (j+1)-th scan signal SCAN[j+1], which is a pixel arranged on the (j+1)-th horizontal line It is applied to the scan lines SCL[j+1] of (P[j+1]). In addition, the j-th scan signal stage SCAN_STG[j] and the (j+1)-th scan signal stage SCAN_STG[j+1] are the j-th scan lines SCL[j] and the (j+1)-th scan line. A scan signal is sequentially applied to the line SCL[j+1].

The j-th sense signal stage SENSE_STG[j] generates a j-th sense signal SENSE[j], which is used for the sense lines SEL[j]) and (j) of the pixels Pj disposed on the j-th horizontal line. It is simultaneously supplied to the sense lines SEL[j+1] of the pixels j+1 disposed on the +1)-th horizontal line.

Referring to FIG. 5 , the image display driving period includes a data writing period Tw and a light emission period Te. The data writing period Tw and the light emission period Te shown in FIG. 5 are indicated with the pixels Pj arranged on the j-th horizontal line as the center. During the image display driving period, the first switch SW1 of the data driver 120 illustrated in FIG. 3 is continuously maintained in an on state, whereas the second switch SW2 is continuously maintained in an off state.

5 and 6A , during the data writing period Tw of the j-th horizontal line HLj, the j-th scan signal SCAN[j] and the j-th sense signal SENSE[j] are turned on. voltage level is applied. As a result, the scan transistor ST1 of the pixels Pj disposed on the j-th horizontal line is turned on, and the data voltage Vdata supplied from the data line DL is applied to the gate of the driving transistor DT[j]. applied to the electrode. Then, the sense transistor ST2[j] is turned on to apply the initialization voltage supplied from the initialization line INL to the source electrode of the driving transistor DT[j]. That is, during the data writing period Tw, the voltage Vgs between the gate and the source of the driving transistor DT[j] is a voltage corresponding to the “difference between the data voltage ( ) and the initialization voltage Vpre”. .

During the data writing period Tw of the j-th horizontal line HLj, the pixels P[j+1] disposed on the (j+1)-th horizontal line are the source electrodes of the driving transistor DT[j+1]. Although the initialization voltage Vini is provided to the , the data write operation is not performed because the data voltage Vdata is not applied to the first node N1.

5 and 6B, during the light emission period Te of the j-th horizontal line HL[j], the j-th scan signal SCAN[j] is inverted to a turn-off voltage level, and the j-th sense signal (SENSE[j]) maintains the turn-on voltage level. The scan transistor SCAN[j] of the pixels Pj arranged on the j-th horizontal line is turned off, and the driving transistor DT[j] is turned off according to the level of the gate-source voltage Vgs set during the data writing period. A driving current Ioled is generated and applied to the organic light emitting diode (OLED). As a result, the organic light emitting diode OLED emits light with a brightness corresponding to the driving current Ioled to display grayscale.

During the light emission period of the j-th horizontal line HL[j], the pixels P[j+1] disposed on the (j+1)-th horizontal line are generated by the (j+1)-th scan signal SCAN[j+1]. ]) and the j-th sense signal SENSE[j] to perform a data write operation. That is, since the timing of the sense signal for writing data to the pixels arranged in two horizontal lines is the same, the number of stages of the shift register for outputting the sense signal can be reduced.

7 is a diagram illustrating timing of a driving signal for external compensation, and FIGS. 8A to 8C are diagrams illustrating an operation of a pixel during an external compensation driving period. In particular, FIG. 7 shows driving signals according to an embodiment in which a sense signal is simultaneously applied to two horizontal lines using the shift register shown in FIG. 4 .

7 and 8A , during the first initialization period Ti, the j-th scan signal SCAN[j] and the j-th sense signal SENSE[j] are applied at a turn-on voltage level. The first switch SW1 is turned on, the second switch SW2 is turned off, and the sense transistor ST2[j] is connected to the input terminal of the initialization voltage Vini. As a result, the scan transistor ST1[j] of the pixels P[j] arranged on the j-th horizontal line is turned on, and the driving transistor DT[ j]) is applied to the gate electrode. Then, the sense transistor ST2[j] is turned on to apply the initialization voltage supplied from the initialization line INL to the source electrode of the driving transistor DT.

7 and 8B , during the second initialization period Ti, the (j+1)th scan signal SCAN[j+1] is applied as a turn-on voltage, and the jth sense signal SENSE[j] ]) maintains the turn-on voltage level. The first switch SW1 is turned on, the second switch SW2 is turned off, and the sense transistor SENSE[j+1] is connected to the input terminal of the initialization voltage Vini. As a result, the scan transistor ST1[j+1] of the pixels P[j+1] disposed on the (j+1)-th horizontal line is turned on, and is used for sensing supplied from the data line DL. A data voltage is applied to the gate electrode of the driving transistor DT[j]. Since the sense transistor ST2[j+1] maintains the turned-on state during the second initialization period Ti2, the source electrode of the driving transistor DT[j+1] maintains the initialization voltage Vini.

7 and 8C , during the sensing period Ts, both the j-th scan signal SCAN[j] and the (j+1)-th scan signal SCNA[j+1] are maintained at turn-off voltages. and the j-th sense signal SENSE[j] maintains a turn-on voltage. The first switch SW1 is turned off and the second switch SW2 is turned on, so that each of the sense transistors SENSE[j] and SENSE[j+1] is connected to the ADC. Also, during the sensing period Ts, a high potential voltage VDD is applied to the cathode electrode of the organic light emitting diode OLED.

Since both the j-th scan signal SCAN[j] and the (j+1)-th scan signal SCAN[j] are turned off, the pixels P[j] and ( The first node N1 of the pixels ([j+1]) arranged on the j+1)-th horizontal line is floated. During the first and second initialization periods Ti1 and Ti2, the gate-source voltage Vgs of each of the driving transistors DT[j] and DT[j+1] becomes greater than the threshold voltage, and the driving transistor ( The driving current passing through the drain-source of DT[j], DT[j+1]) flows. During the sensing period Ts, since the cathode electrode of the organic light emitting diode OLED receives the high potential voltage VDD, the organic light emitting diode OLED does not emit light, and the second node N2[j] ,N2[j+1]) gradually increases. The voltage of the second node N2[j], N2[j+1] is the gate-source voltage Vgs of the driving transistors DT[j] and DT[j+1] as the threshold voltage Vth. increase until saturation.

Since the second switch SW2 is turned on during the sensing period Ts so that each of the second nodes N2[j] and N2[j+1] is connected to the ADC, each second node N2[j ], N2[j+1]) is detected by the ADC.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: data driving circuit 130, 140: gate driving circuit

Claims (9)

a shift register for driving pixels and transistors disposed in the pixels;
Each of the pixels is
a driving transistor for controlling a driving current supplied to the organic light emitting diode;
a scan transistor connected between a gate electrode of the driving transistor and a data line and switched by a scan signal;
a sense transistor connected between a source electrode of the driving transistor and an initialization line and switched by a sense signal; and
a storage capacitor connected between the gate electrode and the source electrode of the driving transistor;
The shift register is
a sense signal stage for simultaneously applying the same sense signal to pixels arranged in k (where k is a natural number) horizontal lines adjacent to each other during an image display driving period and an external compensation driving period; and
and a scan signal stage for sequentially applying the scan signal to pixels arranged in k horizontal lines adjacent to each other. The method of claim 1,
During the data writing period of the image display driving period,
The scan transistor applies a data voltage to the gate electrode of the driving transistor in response to the scan signal,
The sense transistor applies an initialization voltage to the source electrode of the driving transistor in response to the sense signal. 3. The method of claim 2,
During the data writing period of pixels arranged in the j (j is a natural number)-th horizontal line to the (j+k-1)-th horizontal line,
The scan signal stage is
An organic light emitting diode display comprising: a j-th scan signal stage to (j+k-1)-th scan signal stage for sequentially outputting a j-th scan signal to a (j+k-1)-th scan signal. 4. The method of claim 3,
During the data writing period of pixels arranged in the j-th horizontal line to the (j+k-1)-th horizontal line,
The j-th sense signal stage simultaneously applies the j-th sense signal to pixels arranged in the j-th horizontal line to the (j+k-1)-th horizontal line. The method of claim 1,
During the initialization period of the external compensation driving period
The scan transistor applies a sensing data voltage to the gate electrode of the driving transistor in response to the scan signal,
The sense transistor applies an initialization voltage to the source electrode of the driving transistor in response to the sense signal. 6. The method of claim 5,
During the initialization period of the external compensation driving period of pixels arranged in the j (j is a natural number)-th horizontal line to the (j+k-1)-th horizontal line,
An organic light emitting diode display comprising: a j-th scan signal stage to (j+k-1)-th scan signal stage for sequentially outputting a j-th scan signal to a (j+k-1)-th scan signal. 7. The method of claim 6,
During the initialization period of the external compensation driving period of the pixels arranged in the j-th horizontal line to the (j+k-1)-th horizontal line,
The j-th sense signal stage simultaneously applies the j-th sense signal to pixels arranged in the j-th horizontal line to the (j+k-1)-th horizontal line. 6. The method of claim 5,
During the sensing period of the external compensation driving period
the scan transistor is turned off,
The sense transistor connects the source electrode of the driving transistor to the analog-to-digital converter in response to the sense signal. 9. The method of claim 8,
During the sensing period of the external compensation driving period
An organic light emitting diode display device to which a high potential voltage is applied to the cathode electrode of the organic light emitting diode.

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