KR102270613B1 - Organic Light Emitting Diode Display - Google Patents

Abstract

The present invention has the effect of reducing the mounting area of the gate driver by integrating the scan signal generator and the emission signal generator to form the gate driver. In addition, it has the effect of realizing a narrow bezel by reducing signal lines applied to the gate driver.

Description

Organic Light Emitting Diode Display

The present invention relates to an organic light emitting diode display.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting device Various flat display devices such as an organic light emitting diode device (OLED) are being used.

Among them, the organic light emitting diode display has advantages of fast response speed, high luminous efficiency, luminance, and viewing angle by using self-luminous devices that emit light. In such an organic light emitting diode display, a current driving method of controlling the amount of current and controlling the luminance of the organic light emitting diode is generally used.

1 is an exemplary diagram illustrating a circuit configuration for controlling light emission of a conventional organic light emitting diode display device.

As shown, the conventional organic light emitting diode display device includes an external system 12 , a timing controller 14 , a data driver 16 , a gate driver 18 , and a panel 12 .

The external system 10 supplies vertical/horizontal synchronization signals Vsync and Hsync and a clock signal CLK, and the timing controller 14 receives each signal from the external system 12 and controls the gate driver 18 . A gate control signal GCS for controlling the data and a data control signal DCS for controlling the data driver 16 are output. In addition, the timing controller 14 rearranges the image signal RGB input from the external system according to the resolution of the panel 12 and supplies it to the data driver 16 .

The data driver 16 converts the image signal RGB into an analog pixel signal (data signal or data voltage) corresponding to the grayscale value in response to the data control signal DCS inputted from the timing controller 14 . The converted pixel signal is supplied to the data lines DL1 to DLm on the panel 12 .

The gate driver 18 sequentially supplies scan signals to the gate lines GL1 to GLn in response to the gate control signal GCS input from the timing controller 14 , and thereby The thin film transistors (TFTs) are turned on. The gate driver 18 includes a scan signal generator 18a that supplies a scan signal for determining the addressing time of the data voltage Vdata to each of the gate lines GL1 to GLn, and the emission time of the pixels P. and an emission signal generator 18b for supplying the emission signal EM for determination to each of the emission lines EL1 to ELn. At this time, the scan signal generating unit 18a and the emission signal generating unit 18b may be configured in the panel 12 as a gate in panel (GIP).

In the panel 12 , a plurality of pixels P are formed at intersections of each of the gate lines GL1 to GLn and each of the data lines DL1 to DLn. A line for supplying a high potential voltage Vdd and a low potential voltage Vss to each pixel P, a switching transistor, a driving transistor turned on by an image signal applied through the switching transistor, and each emission line EL1 to ELn), an emission transistor and an organic light-emitting diode are formed.

As described above, in the related art, the gate driver 18 for controlling light emission includes a scan signal generating unit 18a and an emission signal generating unit 18a to control light emission. The reason why these two signals are needed is to have different timings of the scan signal and the emission signal to compensate for a threshold voltage change (Vth shift) due to deterioration of the driving transistor.

That is, in the period in which the data voltage is addressed, the scan signal is generated at the turn-on level and the emission signal EM is generated at the turn-off level, and in the period when the pixels P are emitted, the scan signal is generated at the turn-off level, and The emission signal EM is generated at a turn-on level.

In particular, as shown in the drawings, in order to sequentially output signals, the emission signal generator 18b receives the signals output from the shift register SR and the shift register SR and inverts the signals. and an inverter INV for generating a light emission control pulse.

Similarly, the scan signal generating unit 18a also includes a shift resist SRG for sequentially outputting signals that are connected in a cascading fashion.

However, by forming the scan signal generating unit 18a and the emission signal generating unit 18b to generate two signals, respectively, the control signal for controlling each of the generating units 18a and 18b increases, and the control There is a problem in that the number of wires for transmitting signals increases.

2 is a diagram illustrating an area in which a gate driver for controlling light emission is mounted on a panel in a conventional organic light emitting diode display device.

As shown in FIG. 2 , the area W constituting the gate driving unit 18 is the mounting area W1 of the scan signal generating unit 18a and the mounting area W2 of the emission signal generating unit 18b. There are increasing problems. In particular, the area W constituting the gate driver 18 is further increased with the shift resist SR mounting area W2a and the inverter INV mounting area W2b of the emission signal generating unit 18b. Accordingly, there is a problem in that the bezel area of the display device is widened.

An object of the present invention is to solve the above problems, and to reduce an area for mounting a gate driver and to implement a narrow bezel.

In order to achieve the object as described above, the present invention provides a display panel including a plurality of pixels, a data driver supplying data signals to the plurality of pixels, and a plurality of stages to the plurality of pixels. A gate driver supplying a scan signal and a plurality of emission signals, wherein at least one of the plurality of stages includes a first circuit unit generating the scan signal and a second circuit unit generating the emission signal using the scan signal Provided is an organic light emitting diode display including a gate driver comprising: a timing controller for supplying control signals to the data driver and the gate driver.

And, the first circuit unit of the n-th stage generates an n-th scan signal using the (n-1)-th scan signal, a plurality of gate clocks, a high potential voltage and a low potential voltage, and the The second circuit unit may generate an n-th emission signal using the n-th scan signal, a plurality of emission clocks, an emission reset voltage, the high potential voltage, and the low potential voltage.

In addition, the first circuit unit of the first stage generates a first scan signal using a start voltage, the plurality of gate clocks, the high potential voltage and the low potential voltage, and the second circuit unit of the first stage may generate a first emission signal using the start voltage, the first scan signal, the plurality of emission clocks, the emission reset voltage, the high potential voltage, and the low potential voltage.

The plurality of gate clocks may include first to fifth gate clocks, and the plurality of emission clocks may include first to fifth emission clocks.

In addition, the first circuit unit may include N-type first to eleventh transistors and a first capacitor, and the second circuit unit may include N-type twelfth to 22nd transistors and a second capacitor.

And, the gate electrode of the first transistor is connected to the supply terminal of the start voltage and one of the first circuit part of the previous stage, the drain electrode of the first transistor is connected to the supply terminal of the high potential voltage, The source electrode of the first transistor is connected to the drain electrode of the second transistor, the gate electrode of the second transistor is connected to one of the supply terminals of the plurality of gate clocks, and the drain electrode of the second transistor is connected to the first connected to the source electrode of the transistor, the source electrode of the second transistor is connected to the drain electrode of the third transistor, the gate electrode of the third transistor is connected to the supply terminal of the high potential voltage, and the third transistor the drain electrode of the second transistor is connected to the source electrode of the second transistor, the source electrode of the third transistor is connected to the Q1 node, the gate electrode of the fourth transistor is connected to the supply terminal of the high potential voltage, The drain electrode of the fourth transistor is connected to the Q1 node, the source electrode of the fourth transistor is connected to the drain electrode of the sixth transistor, the gate electrode of the fifth transistor is connected to the supply terminal of the high potential voltage, and , the drain electrode of the fifth transistor is connected to the Q1 node, the source electrode of the fifth transistor is connected to the gate electrode of the eleventh transistor, the gate electrode of the sixth transistor is connected to the QB1 node, The drain electrode of the sixth transistor is connected to the source electrode of the fourth transistor, the source electrode of the sixth transistor is connected to the supply terminal of the low potential voltage, and the gate electrode of the seventh transistor is connected to the plurality of gates connected to one of the supply terminals of the clock, the drain electrode of the seventh transistor is connected to the supply terminal of the high potential voltage, the source electrode of the seventh transistor is connected to the QB1 node, and the gate of the eighth transistor The electrode is connected to the supply terminal of the start voltage and one of the first circuit part of the previous stage, the drain electrode of the eighth transistor is connected to the QB1 node, and the source electrode of the eighth transistor is the connected to a supply terminal of a low potential voltage, a gate electrode of the ninth transistor is connected to a source electrode of the fifth transistor, a drain electrode of the ninth transistor is connected to the QB1 node, and a source of the ninth transistor an electrode is connected to the supply terminal of the low potential voltage, the gate electrode of the tenth transistor is connected to the QB1 node, the drain electrode of the tenth transistor is connected to one of the supply terminals of the plurality of gate clocks, The source electrode of the tenth transistor is connected to the drain electrode of the eleventh transistor, the gate electrode of the eleventh transistor is connected to the QB1 node, and the drain electrode of the eleventh transistor is connected to the source electrode of the tenth transistor. connected, the source electrode of the eleventh transistor is connected to the supply terminal of the low potential voltage, the first capacitor is connected between the gate electrode and the source electrode of the tenth transistor, and the source electrode of the tenth transistor and the A first output node between the drain electrode of the eleventh transistor may be connected to a gate line of the display panel, the second circuit unit, and a next stage.

In addition, the gate electrode of the twelfth transistor is connected to one of the supply terminals of the plurality of emission clocks, the drain electrode of the twelfth transistor is connected to the supply terminal of the high potential voltage, and the source electrode of the twelfth transistor is connected to the Q2 node, the gate electrode of the thirteenth transistor is connected to one of the supply terminals of the plurality of emission clocks, the source electrode of the thirteenth transistor is connected to the QB2 node, and the gate of the 14th transistor An electrode is connected to the QB2 node, a drain electrode of the 14th transistor is connected to the Q2 node, a source electrode of the 14th transistor is connected to the supply terminal of the low potential voltage, and a gate electrode of the 15th transistor is connected to the supply terminal of the emission reset voltage, the drain electrode of the fifteenth transistor is connected to the supply terminal of the high potential voltage, the source electrode of the fifteenth transistor is connected to the drain electrode of the sixteenth transistor, and , a gate electrode of the sixteenth transistor is connected to a first output node of the first circuit part, a drain electrode of the sixteenth transistor is connected to the supply terminal of the high potential voltage, and a source electrode of the sixteenth transistor is connected to the connected to the QB2 node, the gate electrode of the 17th transistor is connected to one of the supply terminals of the plurality of emission clocks, the drain electrode of the 17th transistor is connected to the QB2 node, and the source of the 17th transistor The electrode is connected to the QB2 node, the gate electrode of the 18th transistor is connected to the second output node of the second circuit part, the drain electrode of the 18th transistor is connected to the supply terminal of the high potential voltage, The source electrode of the 18th transistor is connected to the source electrode of the 21st transistor, the gate electrode of the 19th transistor is connected to one of the supply terminals of the plurality of emission clocks, and the drain electrode of the 19th transistor is the QB2 node, the source electrode of the 19th transistor is connected to the supply terminal of the low potential voltage, the gate electrode of the twentieth transistor is connected to the Q2 node, The drain electrode is connected to the supply terminal of the high potential voltage, the source electrode of the twentieth transistor is connected to the drain electrode of the twenty-first transistor, the gate electrode of the twenty-first transistor is connected to the QB2 node, and the The drain electrode of the 21st transistor is connected to the source electrode of the twentieth transistor, the source electrode of the 21st transistor is connected to the drain electrode of the 22nd transistor, the gate electrode of the 22nd transistor is connected to the QB2 node, , the drain electrode of the 22nd transistor is connected to the source electrode of the 21st transistor, the source electrode of the 22nd transistor is connected to the supply terminal of the low potential voltage, and the second capacitor is the gate of the twentieth transistor The second output node may be connected between the electrode and the source electrode, and the second output node between the source electrode of the twentieth transistor and the drain electrode of the twenty-first transistor may be connected to the emission line of the display panel.

The first circuit unit of the first stage generates a first scan signal using a start voltage, the plurality of gate clocks, a Q node reset voltage, the high potential voltage, and the low potential voltage, and the first stage The second circuit unit may generate a first emission signal using the first scan signal, the plurality of emission clocks, the emission reset voltage, the high potential voltage, and the low potential voltage.

Also, the plurality of gate clocks may include first to fourth gate clocks, and the plurality of emission clocks may include first to fourth emission clocks.

The first circuit unit may include P-type first to thirteenth transistors and a first capacitor, and the second circuit unit may include P-type 14th to 22nd transistors and a second capacitor.

In addition, the gate electrode of the first transistor is connected to the supply terminal of the start voltage and one of the first circuit part of the previous stage, the source electrode of the first transistor is connected to the supply terminal of the high potential voltage, The drain electrode of the first transistor is connected to the source electrode of the second transistor, the gate electrode of the second transistor is connected to one of the supply terminals of the plurality of gate clocks, and the source electrode of the second transistor is connected to the second transistor. connected to the drain electrode of the first transistor, the drain electrode of the second transistor is connected to the source electrode of the third transistor, the gate electrode of the third transistor is connected to the supply terminal of the high potential voltage, and the third The source electrode of the transistor is connected to the drain electrode of the second transistor, the drain electrode of the third transistor is connected to the Q1 node, the gate electrode of the fourth transistor is connected to the supply terminal of the high potential voltage, and the The source electrode of the fourth transistor is connected to the Q1 node, the drain electrode of the fourth transistor is connected to the source electrode of the seventh transistor, and the gate electrode of the fifth transistor is connected to the supply terminal of the high potential voltage. The source electrode of the fifth transistor is connected to the Q1 node, the drain electrode of the fifth transistor is connected to the source electrode of the eighth transistor, and the gate electrode of the sixth transistor is supplied with the high potential voltage. terminal, the source electrode of the sixth transistor is connected to the Q1 node, the drain electrode of the sixth transistor is connected to the gate electrode of the tenth transistor, and the gate electrode of the seventh transistor is connected to the Q node connected to the supply terminal of the reset voltage, the source electrode of the seventh transistor is connected to the drain electrode of the fourth transistor, the drain electrode of the seventh transistor is connected to the supply terminal of the low potential voltage, and the eighth The gate electrode of the transistor is connected to the QB1 node, the source electrode of the eighth transistor is connected to the drain electrode of the fifth transistor, and the drain electrode of the eighth transistor is connected to the supply terminal of the low potential voltage. a gate electrode of the ninth transistor is connected to one of the supply terminals of the plurality of gate clocks, a source electrode of the ninth transistor is connected to a supply terminal of the high potential voltage, and a drain electrode of the ninth transistor is connected to the QB1 node, the gate electrode of the tenth transistor is connected to the supply terminal of the start voltage and one of the first circuit parts of the previous stage, the source electrode of the tenth transistor is connected to the QB1 node, , the drain electrode of the tenth transistor is connected to the supply terminal of the low potential voltage, the gate electrode of the eleventh transistor is connected to the drain electrode of the sixth transistor, and the source electrode of the eleventh transistor is the QB1 node is connected to, the drain electrode of the eleventh transistor is connected to the supply terminal of the low potential voltage, the gate electrode of the twelfth transistor is connected to the Q1 node, and the source electrode of the twelfth transistor is connected to the plurality of gates connected to one of the clock supply terminals, a drain electrode of the twelfth transistor is connected to a source electrode of the thirteenth transistor, a gate electrode of the thirteenth transistor is connected to the QB1 node, and a source of the thirteenth transistor The electrode is connected to the drain electrode of the twelfth transistor, the drain electrode of the thirteenth transistor is connected to the supply terminal of the low potential voltage, and the first capacitor is connected between the gate electrode and the source electrode of the tenth transistor. and a first output node between the drain electrode of the twelfth transistor and the source electrode of the thirteenth transistor may be connected to the gate line of the display panel, the second circuit unit, and the next stage.

And, the gate electrode of the 14th transistor is connected to one of the supply terminals of the plurality of emission clocks, the source electrode of the 14th transistor is connected to the supply terminal of the high potential voltage, and the drain electrode of the 14th transistor is connected to the Q2 node, a gate electrode of the fifteenth transistor is connected to a first output node of the first circuit unit, a source electrode of the fifteenth transistor is connected to a supply terminal of the emission reset voltage, and the first The drain electrode of the 15th transistor is connected to the QB2 node, the gate electrode of the 16th transistor is connected to the QB2 node, the source electrode of the 16th transistor is connected to the Q2 node, and the drain electrode of the 16th transistor is connected to the supply terminal of the low potential voltage, the gate electrode of the 17th transistor is connected to one of the supply terminals of the plurality of emission clocks, the source electrode of the 17th transistor is connected to the QB2 node, The drain electrode of the seventeenth transistor is connected to the supply terminal of the low potential voltage, the gate electrode of the eighteenth transistor is connected to the second output node of the second circuit part, and the source electrode of the eighteenth transistor is connected to the high voltage connected to the above voltage supply terminal, the drain electrode of the 18th transistor is connected to the QB2 node, the gate electrode of the 19th transistor is connected to the second output node, and the source electrode of the 19th transistor is the connected to a high potential voltage supply terminal, a drain electrode of the 19th transistor is connected to a drain electrode of the 21st transistor, a gate electrode of the twentieth transistor is connected to the Q2 node, and a source of the twentieth transistor The electrode is connected to the supply terminal of the high potential voltage, the drain electrode of the twentieth transistor is connected to the second output node, the gate electrode of the twenty-first transistor is connected to the QB2 node, and the A source electrode is connected to the second output node, a drain electrode of the 21st transistor is connected to a source electrode of the 22nd transistor, and a gate electrode of the 22nd transistor is connected to the Q2 node. and a source electrode of the 22nd transistor is connected to a drain electrode of the 21st transistor, a source electrode of the twentieth transistor is connected to a supply terminal of the high potential voltage, and the second capacitor is connected to a supply terminal of the twentieth transistor. The second output node may be connected between the gate electrode and the drain electrode, and the second output node between the drain electrode of the twentieth transistor and the source electrode of the twenty-first transistor may be connected to the emission line of the display panel.

As described above, the present invention has the effect of reducing the mounting area of the gate driver by integrating the scan signal generator and the emission signal generator to form the gate driver.

In addition, it has the effect of realizing a narrow bezel by reducing signal lines applied to the gate driver.

1 is an exemplary diagram illustrating a configuration for controlling light emission of a conventional organic light emitting diode display device.
2 is a diagram illustrating an area in which a gate driver for controlling light emission is mounted on a panel in a conventional organic light emitting diode display device.
3 is a block diagram schematically illustrating an organic light emitting diode display device according to a first embodiment of the present invention.
4 is an equivalent circuit diagram illustrating an example of a pixel disposed on an nth horizontal pixel line of the organic light emitting diode display according to the first embodiment of the present invention.
5 is a schematic block diagram of a gate driver of an organic light emitting diode display according to a first embodiment of the present invention.
6A is a diagram illustrating a configuration of a first stage of an organic light emitting diode display device according to a first embodiment of the present invention.
6B is a view showing the configuration of a second stage of the organic light emitting diode display device according to the first embodiment of the present invention.
7 is a timing diagram according to the operation characteristics of the gate driver of the organic light emitting diode display according to the first embodiment of the present invention.
8 is a view showing an area in which a gate driver for controlling light emission is mounted on a panel in the organic light emitting diode display according to the first embodiment of the present invention.
9 is a diagram illustrating an example of pixels disposed on an nth horizontal pixel line (n is a positive integer) of an organic light emitting diode display according to a second exemplary embodiment of the present invention.
10 is a waveform diagram of a signal used in a pixel of an organic light emitting diode display device according to a second embodiment of the present invention.
11 is a diagram illustrating a configuration of a first stage of a gate driver of an organic light emitting diode display according to a second exemplary embodiment of the present invention.
12 is a timing diagram according to operation characteristics of a gate driver of an organic light emitting diode display according to a second exemplary embodiment of the present invention.

Hereinafter, an organic light emitting diode display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram schematically illustrating an organic light emitting diode display device according to a first embodiment of the present invention.

As shown, the organic light emitting diode display device according to the first embodiment of the present invention includes a display panel 102 in which pixels P are arranged in a matrix form, a plurality of data lines DL1 to DLq, and a plurality of A data driver 106 for driving the data lines DL1 to DLq, a plurality of gate lines GL1 to GLp and a plurality of emission lines EL1 to ELp, a plurality of gate lines GL1 to GLp, and It includes a gate driver 108 for driving the plurality of emission lines EL1 to ELp, a timing controller 104 for controlling operations of each of the drivers 106 and 108 , and an external system 100 .

The display panel 102 includes a plurality of data lines DL1 to DLq, a plurality of gate lines GL1 to GLp crossing the plurality of data lines DL1 to DLq, and a plurality of emission lines EL1 to ELp, , pixels P are disposed at intersections of the lines DL1 to DLq, GL1 to GLp, and EL1 to ELp.

Each pixel P is supplied with a high potential voltage Vdd, a low potential voltage Vss, and an initialization voltage Vinit. Here, each pixel P has one data line DLm, two adjacent gate lines GL1 and GL(n-1), and one emission line ELn, as shown in FIG. 4 . can be connected to

The timing controller 104 aligns the digital video data RGB input from the external system 100 to the resolution of the display panel 100 and supplies it to the data driver 106 . In addition, the timing controller 104 performs the operation timing of the data driver 106 based on timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the clock signal CLK, and the data enable signal DE. A data control signal DCS for controlling , and a gate control signal GCS for controlling an operation timing of the gate driver 108 are generated.

The data driver 106 converts the digital video data RGB into an analog data voltage according to the data control signal DCS and supplies it to the plurality of data lines DL1 to DLq.

The gate driver 108 generates the scan signals Scan1 to Scan(p) and the emission signals EM(1) to EM(p) according to the gate control signal GCS, and generates a plurality of gate lines GL1 to GL1 to GLp) and a plurality of emission lines EL1 to ELp, respectively.

Here, the gate driver 108 shifts the scan signals Scan1 to Scan(p) and includes a plurality of stages STG1 to STGp for generating the emission signals EM(1) to EM(p). .

The gate driver 108 may be directly formed on the display panel 100 according to a gate in panel (GIP) method.

4 is a diagram illustrating an example of a pixel disposed on an n-th horizontal pixel line (n is a positive integer) of an organic light emitting diode display device according to the first embodiment of the present invention, wherein one pixel includes four transistors; A 4T2C structure including two capacitors is shown.

As shown, the pixel P includes an organic light emitting diode E, an emission transistor ETr, a switching transistor STr, a driving transistor DTr, an initialization transistor Tinit, and first and second pixel capacitors. (Cp1, Cp2). Each of the transistors ETr, STr, DTr, and Tinit may be implemented as an N-type MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) or a P-type. Hereinafter, it will be described based on the N-type MOSFET.

The organic light emitting diode E emits light by a driving current flowing between the input terminal of the high potential voltage Vdd and the input terminal of the low potential voltage Vss. The cathode electrode of the organic light emitting diode E is connected to the input terminal of the low potential voltage Vss.

The emission transistor ETr is connected between the input terminal of the high potential voltage Vdd and the driving transistor DTr, according to the n-th emission signal EM(n) input to the n-th emission line ELn. The high potential voltage (Vdd) is switched. The gate electrode of the emission transistor ETr is connected to the n-th emission line ELn, the drain electrode is connected to the input terminal of the high potential voltage Vdd, and the source electrode is connected to the drain electrode of the driving transistor DTr. do. In this case, a point where the source electrode of the emission transistor ETr and the drain electrode of the driving transistor DTr are connected is referred to as a first node N1 .

The switching transistor STr switches a current path between the data line DLm and the driving transistor DTr according to the n-th scan signal Scan(n). The gate electrode of the switching transistor STr is connected to the n-th gate line GLn, the drain electrode is connected to the data line DLm, and the source electrode is connected to the gate electrode of the driving transistor DTr. In this case, a point where the source electrode of the switching transistor STr and the gate electrode of the driving transistor DTr are connected is referred to as a second node N2 .

The driving transistor DTr is connected between the first node N1 and the organic light emitting diode E, and controls the amount of driving current applied to the anode electrode of the organic light emitting diode E according to the potential of the second node N2. do. The gate electrode of the driving transistor DTr is connected to the second node N2 , the drain electrode is connected to the first node N1 , and the source electrode is connected to the anode electrode of the organic light emitting diode E . In this case, a point where the source electrode of the driving transistor DTr and the anode electrode of the organic light emitting diode E are connected is referred to as a third node N3 .

The initialization transistor Tinit is connected between the input terminal of the initialization voltage Vinit and the third node N3, and an initialization voltage is applied to the third node N3 according to the n-1 th scan signal Scan(n-1). (Vinit) is applied to set the source voltage of the driving transistor DTr as the initialization voltage Vinit. The gate electrode of the initialization transistor Tinit is connected to the n-1 th gate line GL(n-1), the drain electrode is connected to the input terminal of the initialization voltage Vinit, and the source electrode is connected to the third node N3. is connected to

The first capacitor C1 is connected between the second node N2 and the third node N3, and the second capacitor C1 is connected between the input terminal of the high potential driving voltage Vdd and the third node N3. connected The first capacitor C1 stores the threshold voltage Vth of the driving transistor DTr according to the n-th emission signal EM(n), and the driving transistor C1 according to the n-th scan signal Scan(n). The gate voltage of DTr) is maintained for a set frame time. The second capacitor C2 functions to stabilize the gate voltage of the driving transistor DTr and increase the efficiency of the data voltage Vdata.

Hereinafter, a gate driver for driving the pixels of the above-described organic light emitting diode display will be described.

5 is a schematic block diagram of a gate driver of an organic light emitting diode display according to a first exemplary embodiment of the present invention.

As shown, the gate driver 108 has a high potential voltage Vdd, a low potential voltage Vss, a start voltage VST, first to fifth gate clocks GCLK1 to GCLK5, and first to fifth emitters. Scan signals (Scan(1) to Scan(p)) and emission signals (EM(1) to EM(p)) are sequentially driven based on the signal clock (ECLK1 ~ ECLK5) and the emission reset voltage (ERST). It includes a plurality of stages (STG1 to STGp) that output as

For example, the first stage STG1 includes a high potential voltage Vdd, a low potential voltage Vss, a start voltage VST, the first, third, and fifth gate clocks GCLK1, GCLK3, GCLK5, and the second stage. 1st, 2nd, 3rd, 5th emission clocks (ECLK1, ECLK2, ECLK3, ECLK5) and the emission reset voltage (ERST) are driven based on the first scan signal (Scan(1)) and the first emission A signal EM(1) is output.

At this time, the output first scan signal Scan(1) and the first emission signal EM(1) are respectively the first gate line GL1 and the first emission line of the first horizontal pixel column HPL1. (EL1) is applied.

The second stage STG2 includes a high potential voltage Vdd, a low potential voltage Vss, a first scan signal Scan(1), first, second, and fourth gate clocks GCLK1, GCLK2, GCLK4, The first, second, third, and fourth emission clocks ECLK1, ECLK2, ECLK3, and ECLK4 are driven based on the emission reset voltage ERST, and the second scan signal Scan(2) and the second emitter output signal EM(2).

At this time, the output second scan signal Scan(2) and the second emission signal EM(2) are respectively the second gate line GL(2) and the second emission signal of the second horizontal pixel column HPL2. It is applied to the emission line EL(2).

In the case of the second stage STG2, the first scan signal Scan(1) of the first stage STG1 is supplied as a voltage corresponding to the start voltage VST. That is, the stage located in the subordinate stage is supplied with the output signals of the stage located in the front stage as a start voltage.

Similarly, an arbitrary n-th stage STGn includes a high potential voltage Vdd, a low potential voltage Vss, an (n-1)th scan signal Scan(n-1), a first gate clock GCLK1, One of the pair of the third and fifth gate clocks GCLK3 and GCLK5 and the pair of the second and fourth gate clocks GCLK2 and GCLK4, the first, second, and third emission clocks ECLK1, ECLK2, ECLK3 ), one of the fourth and fifth emission clocks ECLK4 and ECLK5, driven based on the emission reset voltage ERST, and the nth scan signal Scan(n) and the nth emission signal EM(n) )) is printed.

At this time, the output n-th scan signal Scan(n) and n-th emission signal EM(n) are respectively the n-th gate line GLn and the n-th emission line of the n-th horizontal pixel column HPLn. (ELn) is applied.

Accordingly, the second to pth stages STG2 to STGp are connected in a dependent connection relationship in which the output signals of the previous stage are supplied as start voltages.

6A and 6B are diagrams illustrating the configuration of the first and second stages of the gate driver of the organic light emitting diode display according to the first embodiment of the present invention.

As shown in FIG. 6A , the first stage STG1 includes a first circuit unit BL1 and a second circuit unit BL2 .

The first circuit unit BL1 includes a start voltage VST, a first gate clock GCLK1, a third gate clock GCLK3, a fifth gate clock GCLK5, a high potential voltage Vdd, and a low potential voltage Vss. It serves to generate the first scan signal Scan(1) using .

The second circuit unit BL2 includes the first scan signal Scan(1) generated by the first circuit unit BL1 and the first, second, third, and fifth emission clocks ECLK1, ECLK2, ECLK3, and ECLK5. , serves to generate the first emission signal EM( 1 ) using the emission reset voltage ERST, the high potential voltage Vdd, and the low potential voltage Vss.

That is, in the related art, a shift register and an emission driving circuit for generating a scan signal and an emission signal are provided, respectively, but the present invention is characterized in that the shift register and the emission driving circuit are integrated into one to form a gate driver.

In more detail, the first circuit unit BL1 includes first to eleventh transistors T1 to T11 and a first driving capacitor Cd1. A connection relationship between transistors included in the first circuit unit BL1 will be described as follows.

The first transistor T1 has a gate electrode connected to a terminal to which a start voltage VST is supplied, a drain electrode connected to a terminal to which a high potential voltage Vdd is supplied, and a drain electrode of the second transistor T2. The source electrode is connected.

The second transistor T2 has a gate electrode connected to a terminal to which the fifth gate clock GCLK5 is supplied, a drain electrode connected to a source electrode of the first transistor T1, and a drain electrode of the third transistor T3. The source electrode is connected to

The third transistor T3 has a gate electrode connected to a terminal to which the high potential voltage Vdd is supplied, a drain electrode connected to a source electrode of the second transistor T2, and a source electrode connected to the Q1 node Q1. do.

The fourth transistor T4 has a gate electrode connected to a terminal to which the high potential voltage Vdd is supplied, a drain electrode connected to a source electrode of the third transistor T3, and a drain electrode connected to the sixth transistor T6. The source electrode is connected.

The fifth transistor T5 has a gate electrode connected to a terminal to which the high potential voltage Vdd is supplied, a drain electrode connected to the Q1 node Q1, and a source electrode connected to the gate electrode of the ninth transistor T9. do.

As illustrated, the sixth transistor T6 may be configured as a dual gate to improve off-current characteristics. Hereinafter, for convenience of description, a transistor configured as a dual gate will be described as a configuration of a single gate.

The sixth transistor T6 has a gate electrode connected to the QB1 node QB1, a source electrode connected to a terminal to which the low potential voltage Vss is supplied, and a drain electrode connected to the source electrode of the fourth transistor T4. do.

The seventh transistor T7 has a gate electrode connected to a terminal to which the third gate clock GCLK3 is supplied, a drain electrode connected to a terminal to which the high potential voltage Vdd is applied, and a source electrode connected to the QB1 node QB1. is connected

The eighth transistor T8 has a gate electrode connected to a terminal to which a start voltage VST is supplied, a drain electrode connected to a source electrode of the seventh transistor T7, and a terminal to which a low potential voltage Vss is supplied. The source electrode is connected.

The ninth transistor T9 has a gate electrode connected to the source electrode of the fifth transistor T5, a drain electrode connected to the QB1 node QB1, and a source electrode connected to a terminal to which the low potential voltage Vss is supplied. do.

The tenth transistor T10 has a gate electrode connected to the Q1 node Q1, a drain electrode connected to a terminal to which the first gate clock GCLK1 is supplied, and a source electrode connected to the first gate line GL1. Configures the first output node OUT1. At this time, the first driving capacitor Cd1 is positioned between the gate electrode and the source electrode.

The eleventh transistor T11 has a gate electrode connected to the QB1 node QB1, a drain electrode connected to a source electrode of the tenth transistor T10, and a source electrode connected to a terminal to which the low potential voltage Vss is supplied. do.

The second circuit unit BL2 includes twelfth to twenty-second transistors T12 to T22 and a second driving capacitor Cd2. A connection relationship between the transistors included in the second circuit unit BL2 will be described as follows.

The twelfth transistor T12 has a gate electrode connected to a terminal to which the first emission clock ECLK1 is supplied, a drain electrode connected to a terminal to which the high potential voltage Vdd is supplied, and a source to the Q2 node Q2. The electrode is connected.

The thirteenth transistor T13 has a gate electrode connected to a terminal to which the third emission clock ECLK3 is supplied, a drain electrode connected to a terminal to which a start voltage VST is supplied, and a source electrode to the QB2 node QB2. is connected

The 14th transistor T14 has a gate electrode connected to the QB2 node QB2, a drain electrode connected to the Q2 node Q2, and a source electrode connected to a terminal to which the low potential voltage Vss is supplied.

The fifteenth transistor T15 has a gate electrode connected to a terminal to which the emission reset voltage ERST is supplied, a drain electrode connected to a terminal to which the high potential voltage Vdd is supplied, and the drain of the sixteenth transistor T16. A source electrode is connected to the electrode.

The sixteenth transistor T16 has a gate electrode connected to the first gate line GL1 , a drain electrode connected to a source electrode of the fifteenth transistor T15 , and a source electrode connected to the QB2 node QB2 .

The 17th transistor T17 has a gate electrode connected to a terminal to which the fifth emission clock ECLK5 is supplied, a drain electrode connected to the QB2 node QB2, and a source to a terminal to which the low potential voltage Vss is supplied. The electrode is connected.

The eighteenth transistor T18 has a gate electrode connected to the first emission line EL( 1 ), a drain electrode connected to a terminal to which a high potential voltage Vdd is supplied, and a source of the twenty-first transistor T21 . A source electrode is connected to the electrode and the drain electrode of the 22nd transistor T22.

The nineteenth transistor T19 has a gate electrode connected to a terminal to which the second emission clock ECLK2 is supplied, a drain electrode connected to the QB2 node QB2, and a source to a terminal supplied with the low potential voltage Vss. The electrode is connected.

The twentieth transistor T20 has a gate electrode connected to the Q2 node Q2, a drain electrode connected to a terminal to which a high potential voltage Vdd is supplied, and a source electrode connected to the first emission line EL(1). These are connected to configure the second output node OUT2. At this time, the second driving capacitor Cd2 is positioned between the gate electrode and the source electrode.

The 21st transistor T21 has a gate electrode connected to the QB2 node QB2, a drain electrode connected to the first emission line EL(1), and a source electrode connected to the source electrode of the 18th transistor T18. connected

The 22nd transistor T22 has a gate electrode connected to the QB2 node QB2, a drain electrode connected to a source electrode of the 21st transistor T21, and a source electrode connected to a terminal to which the low potential voltage Vss is supplied. do.

As shown in FIG. 6B , the second stage STG2 includes first and second circuit units BL1 and BL2 that use the n-th scan signal Scan(n) instead of the start voltage VST. In addition, the first and second circuit units BL1 and BL2 of the second stage STG2 are similar in configuration to the first and second circuit units BL1 and BL2 of the first stage STG1. is omitted.

In the first circuit unit BL1 of the second stage STG2, the first transistor T1 is a first output node of the first circuit unit BL1 of the first stage STG1 instead of the terminal to which the start voltage VST is supplied. The gate is connected to (OUT1). The gate of the second transistor T2 is connected to a terminal to which the first gate clock GCLK1 is supplied instead of the terminal to which the fifth gate clock GCLK5 is supplied. The gate of the seventh transistor T7 is connected to a terminal to which the fourth gate clock GCLK4 is supplied instead of the terminal to which the third gate clock GCLK3 is supplied. The drain of the tenth transistor T10 is connected to a terminal to which the second gate clock GCLK2 is supplied instead of the terminal to which the first gate clock GCLK1 is supplied.

In addition, the first output node OUT1 of the second stage STG2 includes the second gate line GL2, the second circuit unit BL2 of the second stage STG2, and the first circuit unit of the third stage STG3 (STG3). The second scan signal Scan(2) connected to BL1 and output from the first output node OUT1 of the second stage STG2 is the second gate line GL2 and the second stage STG2. It is supplied to the second circuit unit BL2 and the first circuit unit BL1 of the third stage STG3.

In the second circuit unit BL2 of the second stage STG2, the twentieth transistor T20 has a gate at the terminal to which the second emission clock ECLK2 is supplied instead of the terminal to which the first emission clock ECLK1 is supplied. Connected. The thirteenth transistor T13 has a gate connected to a terminal to which the fourth emission clock ECLK4 is supplied instead of a terminal to which the third emission clock ECLK3 is supplied, and the first transistor T13 instead of a terminal to which the start voltage VST is supplied. The drain is connected to the output node OUT1. The gate of the seventeenth transistor T17 is connected to a terminal to which the first emission clock ECLK1 is supplied instead of the terminal to which the fifth emission clock ECLK5 is supplied. The gate of the nineteenth transistor T19 is connected to a terminal to which the third emission clock ECLK3 is supplied instead of the terminal to which the second emission clock ECLK2 is supplied.

And, the second output node OUT2 of the second stage STG2 is connected to the second emission line EL2, and the second emission output from the second output node OUT2 of the second stage STG2 is The signal EM( 2 ) is supplied to the second emission line EL2 .

Although not shown, the remaining stages STG3 to STGp also have a connection structure similar to that of the second stage STG2, and the first to pth stages STG1 to STGp form a dependent connection relationship with each other and are connected through respective output nodes. A scan signal and a light emission control signal are sequentially output.

For example, the arbitrary n-th stage STGn includes the high potential voltage Vdd, the low potential voltage Vss, the (n-1)th scan signal Scan(n-1), the first and third And the fifth gate clock (GCLK1, GCLK3, GCLK5), the first, second, third and fifth emission clocks (ECLK1, ECLK2, ECLK3, ECLK5), the n-th scan using the emission reset voltage (ERST) The signal Scan(n) and the nth emission signal EM(n) are output, and the nth scan signal Scan(n) and the nth emission signal EM(n) are respectively nth horizontal It may be supplied to the n-th gate line GLn and the n-th emission line ELn corresponding to the pixel column HPLn.

And, an arbitrary (n+1)th stage STG(n+1) is a high potential voltage Vdd, a low potential voltage Vss, an nth scan signal Scan(n), the first, The second and fourth gate clocks GCLK1, GCLK2, GCLK4, the first, second, third, and fourth emission clocks ECLK1, ECLK2, ECLK3, ECLK4, and the ( The (n+1)th scan signal Scan(n+1) and the (n+1)th emission signal EM(n+1) are output, and the (n+1)th scan signal Scan(n+1) is output. )) and the (n+1)th emission signal EM(n+1) are the (n+1)th gate line corresponding to the (n+1)th horizontal pixel column HPL(n+1), respectively. (GL(n+1)) and the (n+1)th emission line EL(n+1) may be supplied.

Also, in the above description, the transistor is an N-type transistor as an example, but one or more of them may be configured as a P-type transistor.

Hereinafter, operation characteristics of the gate driver will be described with reference to FIG. 7 .

7 is a timing diagram according to the operation characteristics of the gate driver of the organic light emitting diode display according to the first embodiment of the present invention.

First, as shown in FIGS. 6A, 6B and 7 , when the start voltage VST and the fifth gate clock GCLK5 are synchronized and input to the first circuit unit BL1 of the first stage STG1, the first and second The transistors T1 and T2 are turned on so that the Q1 node Q1 is in a logic high state corresponding to the high potential voltage Vdd. The tenth transistor T10 connected thereto is also in a logic high state. That is, it is in a ready state. Subsequently, when the first gate clock GCLK1 is input, the tenth transistor T10 in the ready state is turned on and outputs the first scan signal Scan(1). At this time, the output first scan signal Scan(1) is the 16th transistor T16 of the first gate line GL1 and the second circuit unit BL2 and the first circuit unit BL1 of the second stage STG2. is entered as

Then, when the first scan signal Scan(1) and the first gate clock GCLK1 are input to the first circuit unit BL1 of the second stage STG2, the first and second transistors T1 and T2 are turned on. -on, the Q1 node Q1 becomes a logic high state corresponding to the high potential voltage Vdd. The tenth transistor T10 connected thereto is in a ready state. Subsequently, when the second gate clock GCLK2 is input, the tenth transistor T10 in the ready state is turned on and the second scan signal Scan(2) is output. At this time, the output second scan signal Scan(2) is the second gate line GL2) and the 16th transistor T16 and the third stage STG3 of the second circuit unit BL2 of the second stage STG2. ) is input to the first circuit unit BL1.

That is, the first circuit unit BL1 of the second stage STG2 corresponds to the first scan signal Scan(1) output from the first circuit unit BL1 of the first stage STG1 to the start voltage VST. The voltage is supplied to the output voltage, and a second scan signal Scan(2) is output. In other words, the first circuit unit BL1 of the second stage STG2 operates based on the first scan signal Scan( 1 ) of the first circuit unit BL1 of the first stage STG1 . Accordingly, the first circuit units BL1 of the third to pth stages STG3 to STGp located in the dependent stages have a dependent connection relationship with each other, and operate based on the scan signal output from the previous stage.

On the other hand, as shown in FIGS. 6A, 6B and 7 , when the start voltage VST and the third emission clock ECLK3 are synchronized and input to the second circuit unit BL2 of the first stage STG1, The 21st and 22nd transistors T21 and T22 are turned on to output the low potential voltage Vss as the first emission signal EM( 1 ). That is, the first emission signal EM( 1 ) in a logic low state is output. Subsequently, the fifth emission clock ECLK5 is input to turn off the 21st and 22nd transistors T21 and T22 so that the first emission signal EM(1) is maintained in a logic low state ( holding).

Next, the first emission clock ECLK1 is applied to the second circuit unit BL2 of the first stage STG1 to turn on the twelfth and twentieth transistors T12 and T20, and the high potential voltage Vdd ) is output as the first emission signal EM( 1 ). That is, the first emission signal EM( 1 ), which was held in a logic low state, is changed to a logic high state.

Next, the first scan signal Scan(1) and the emission reset voltage ERST are applied to the second circuit unit BL2 of the first stage STG1 to turn on the 15th and 16th transistors T15 and T16. -on and the QB2 node QB2 is set to a logic high state. Accordingly, the 21st and 22nd transistors T21 and T22 are turned on, and the low potential voltage Vss is output as the first emission signal EM( 1 ). Accordingly, the first emission signal EM( 1 ) maintaining a logic high state is set to a logic low state.

Next, the first emission clock ECLK1 is applied to the second circuit unit BL of the first stage STG1 to output the first emission signal EM( 1 ) having a logic high state.

Then, when the second scan signal Scan2 and the fourth emission clock ECLK4 are synchronized and input to the second circuit unit BL2 of the second stage STG2, the 21st and 22nd transistors T21 and T22 are It is turned on and the low potential voltage Vss is output as the second emission signal EM2. That is, the second emission signal EM2 in a logic low state is output. Subsequently, the first emission clock ECLK1 is input to turn off the 21st and 22nd transistors T21 and T22 so that the second emission signal EM2 is held in a logic low state. .

Next, the second emission clock ECLK2 is applied to the second circuit unit BL2 of the second stage STG2 to turn on the twelfth and twentieth transistors T12 and T20, and the high potential voltage Vdd is applied. This second emission signal EM2 is output. That is, the second emission signal EM2, which was held in a logic low state, is changed to a logic high state.

Next, the second scan signal Scan2 and the emission reset voltage ERST are applied to the second circuit unit BL2 of the second stage STG2 to turn on the 15th and 16th transistors T15 and T16 and The QB2 node QB2 is set to a logic high state. Accordingly, the 21st and 22nd transistors T21 and T22 are turned on, and the low potential voltage Vss is output as the second emission signal EM2. Accordingly, the second emission signal EM2 maintaining a logic high is set to a logic low state.

Next, the second emission clock ECLK2 is applied to the second circuit unit BL2 of the second stage STG2 to output the second emission signal EM2 having a logic high state.

As described above, the subsequent circuit units are connected in a dependent connection relationship to sequentially output the emission control signal.

Here, during the initialization period TPinit in which the n-th scan signal Scan(n) has a logic high state and the n-th emission signal EM(n) has a logic low state, The third node (N3 in FIG. 4) is initialized. Then, during the sampling period TPsamp in which the n-th scan signal Scan(n) has a logic high state and the n-th emission signal EM(n) has a logic high state, the driving transistor (DTr of FIG. 4 ) The threshold voltage Vth is stored in the first pixel capacitor (Cp1 in FIG. 4 ).

Meanwhile, in the conventional case, the scan signal generated by the scan signal generating unit is applied to the gate line, and the emission signal generating unit is turned on to the QB node of the inverter circuit using the signal generated from the shift register of the emission signal generating unit. In contrast to controlling turn-off, in the first embodiment, the n-th scan signal Scan(n) generated in the first circuit unit BL1 of each stage is applied to the 16th transistor T16 of the second circuit unit BL2. is supplied to to control the second circuit unit BL2, and when the n-th scan signal Scan(n) is a voltage in a logic low state, the voltage of the QB2 node QB2 is floated, As a result, the operation characteristics of the twenty-first and twenty-second transistors T21 and T22 are unstable, and thus the n-th emission signal EM(n) may operate unstable.

In order to solve this problem, the QB2 node QB2 is controlled to maintain a constant voltage using the emission reset voltage ERST, the second emission clock ECLK2, and the fifth emission clock ECLK5. (The order in which the second and fifth emission clocks ECLK2 and ECLK5 are input can be changed as needed.)

That is, when the n-th emission signal EM(n) is logic high, the twelfth transistor T12 and the twentieth transistor T20 are turned on through the first emission clock ECLK1, and the It is boosted using the second driving capacitor Cd2, and when the n-th emission signal EM(n) is logic low, the emission reset voltage ERST and the n-th scan signal Scan(n)) is used to set the QB2 node QB2 to logic high to turn on the 21st and 22nd transistors T21 and T22 to operate.

8 is a diagram illustrating an area in which a gate driver of the organic light emitting diode display device according to the first embodiment of the present invention is mounted on a panel.

As shown in FIG. 8 , the gate driver of the present invention includes a first circuit unit BL1 and a second circuit unit BL2 and is mounted on a panel.

When the mounting area W3 of the first circuit unit BL1 and the mounting area W4 of the second circuit unit BL2 are compared with the conventional gate driver of FIG. 2 , the conventional gate driver includes a scan signal generator and an emission signal The generator unit has an area of a width of 1100 μm, and the gate driving unit of the present invention has an area of 865 μm when the first circuit unit BL1 and the second circuit unit BL2 are combined.

That is, the gate driver according to the first embodiment of the present invention has the effect of reducing the mounting area by about 21.4% compared to the conventional gate driver. In addition, as the number of circuits constituting the gate driver is reduced, a control signal line applied to each circuit is reduced, so that a narrow bezel can be implemented.

Meanwhile, the present invention can be applied to other pixel structures, which will be described with reference to the drawings.

9 is a diagram illustrating an example of a pixel disposed on an nth horizontal pixel line (n is a positive integer) of an organic light emitting diode display device according to a second embodiment of the present invention, and FIG. 10 is a first embodiment of the present invention. A waveform diagram of a signal used in a pixel of an organic light emitting diode display according to the second embodiment, showing a 6T1C structure in which one pixel includes six transistors and one capacitor.

Since the schematic configuration of the gate driver and the organic light emitting diode display of the second embodiment is the same as that of the first embodiment, a description thereof will be omitted.

As shown in FIG. 9 , the pixel P includes an organic light emitting diode E, a driving transistor DTr, first to fifth pixel transistors PTr1 to PTr5, and a pixel capacitor Cp. The driving transistor DTr and the first to fifth pixel transistors PTr1 to PTr5 may be implemented as N-type or P-type MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors). Hereinafter, P-type MOSFETs are used. explained on the basis of

The driving transistor DTr and the first to fifth pixel transistors PTr1 to PTr5 include a gate electrode, a source electrode, and a drain electrode, respectively. For convenience, an electrode to which a signal for switching is applied is a gate electrode and a high potential voltage Vdd. ) will be described as the source electrode and the electrode close to the low potential voltage (Vss) as the drain electrode.

The first pixel transistor PTr1 transfers the m-th data voltage Vdata(m) of the m-th data line DLm according to the n-th scan signal Scan(n) of the n-th gate line GLn to the pixel capacitor ( Cp), and for this, the gate electrode, the source electrode, and the drain electrode of the first pixel transistor PTr1 are respectively connected to the n-th gate line GLn, one end of the pixel capacitor Cp, and the m-th data line DLm. Connected.

The second pixel transistor PTr2 applies the initialization voltage Vinit to the gate electrode of the driving transistor DTr according to the n-th scan signal Scan(n) of the n-th gate line GLn. The gate electrode, the source electrode, and the drain electrode of the pixel transistor PTr2 are the nth gate line GLn, the drain electrode of the driving transistor DTr, the source electrode of the fourth pixel transistor PTr4, and the drain electrode of the driving transistor DTr, respectively. It is connected to the other end of the gate electrode and the pixel capacitor Cp.

Here, the second pixel transistor PTr2 is configured as a dual gate, but may be configured as a single gate in another embodiment.

The third pixel transistor PTr2 applies the initialization voltage Vinit to one end of the pixel capacitor Cp according to the n-th emission signal EM(n) of the n-th emission line ELn. The gate electrode, the source electrode, and the drain electrode of the three-pixel transistor PTr3 have the n-th emission line ELn, the source electrode of the first pixel transistor PTr1, and one end of the pixel capacitor Cp, the initialization voltage Vinit, respectively. It is connected to the input terminal and the drain electrode of the fifth pixel transistor PTr5.

The fourth pixel transistor PTr4 applies the initialization voltage Vinit to the other end of the pixel capacitor Cp according to the n-th emission signal EM(n) of the n-th emission line ELn, and applies a high potential voltage ( Vdd) is applied to the anode of the organic light emitting diode E, and for this purpose, the gate electrode, the source electrode, and the drain electrode of the fourth pixel transistor PTr4 are connected to the nth emission line ELn and the second pixel transistor PTr2, respectively. ) and the drain electrode of the driving transistor DTr, the drain electrode of the fifth pixel transistor PTr5, and the anode of the organic light emitting diode E.

The fifth pixel transistor PTr5 applies the initialization voltage Vinit to the gate of the driving transistor DTr according to the n-th scan signal Scan(n) of the n-th gate line GLn. The gate electrode, the source electrode, and the drain electrode of the transistor PTr5 are the nth gate line GLn, the drain electrode of the fourth pixel transistor PTr4 and the anode of the organic light emitting diode E, the initialization voltage Vinit input terminal and It is connected to the drain electrode of the third pixel transistor PTr3.

The driving transistor DTr applies a high potential voltage Vdd to the anode of the organic light emitting diode E according to the voltage of the other end of the pixel capacitor Cp, and for this purpose, the gate electrode, the source electrode, The drain electrode is the other end of the pixel capacitor Cp, the drain of the second pixel transistor PTr2, and the input terminal of the high potential voltage Vdd, respectively. It is connected to the source electrode of the second pixel transistor PTr2 and the source electrode of the fourth pixel transistor PTr4.

The pixel capacitor Cp stores the m-th data voltage Vdata(m) and the threshold voltage Vth of the driving transistor DTr, and for this purpose, one end and the other end of the pixel capacitor Cp are respectively connected to the first pixel transistor ( It is connected to the source electrode of PTr1, the source electrode of the third pixel transistor PTr3, the gate electrode of the driving transistor DTr, and the drain electrode of the second pixel transistor PTr.

The organic light emitting diode (E) emits light by the driving current flowing between the high potential voltage (Vdd) input terminal and the low potential voltage (Vss) input terminal, and for this, the anode and the cathode of the organic light emitting diode (E) are respectively connected to the driving transistor DTr ), the source electrode of the second pixel transistor PTr, and the low potential voltage Vss input terminal.

As shown in FIG. 10 , during the first period TP1, which is the initialization period, the first, second, and fifth pixel transistors PTr1, PTr2, and PTr5 according to the low-level n-th scan signal Scan(n). ) is turned on, and the third and fourth pixel transistors PTr3 and PTr4 are turned on by the low-level n-th emission signal EM(n) to drive both ends of the pixel capacitor Cp. The gate electrode of the transistor DTr is charged with the initialization voltage Vinit.

During the second period TP2, which is the sampling and writing period, the first, second, and fifth pixel transistors PTr1, PTr2, and PTr5 are turned on by the low-level n-th scan signal Scan(n). , the third and fourth pixel transistors PTr3 and PTr4 are turned off by the high-level n-th emission signal EM(n), so that the m-th data voltage Vdata(m) and the threshold voltage Vth are turned off. ) is stored in the pixel capacitor Cp.

During the third period TP3, which is the holding period, the first, second, and fifth pixel transistors PTr1, PTr2, and PTr5 are turned off by the high-level n-th scan signal Scan(n), and the high level The third and fourth pixel transistors PTr3 and PTr4 are turned off by the n-th emission signal EM(n) of the level, so that the voltage of the gate electrode of the driving transistor DTr is changed to the n-th data voltage Vdata. (n)) and the threshold voltage Vth.

During the fourth period TP4, which is the emission period, the first, second, and fifth pixel transistors PTr1, PTr2, and PTr5 are turned off by the high-level n-th scan signal Scan(n), The third and fourth pixel transistors PTr3 and PTr4 are turned on by the low-level n-th emission signal EM(n), and the n-th data voltage Vdata(n) and the threshold voltage Vth are turned on. A current corresponding to ? flows through the driving transistor DTr, and the organic light emitting diode E emits light.

A gate driver for driving such a pixel will be described with reference to the drawings.

11 is a view showing the configuration of the first stage of the gate driving unit of the organic light emitting diode display device according to the second embodiment of the present invention. The cascading configuration of the first stage and the second to p-th stages is the first embodiment. Since it is the same as , a description thereof will be omitted.

11 , the first stage STG1 includes a first circuit unit BL1 and a second circuit unit BL2.

The first circuit unit BL1 includes a start voltage VST, a first gate clock GCLK1, a third gate clock GCLK3, a fourth gate clock GCLK4, a high potential voltage Vdd, and a low potential voltage Vss. and a first scan signal Scan(1) using the Q node reset voltage QRST.

The second circuit unit BL2 includes the first scan signal Scan(1) generated by the first circuit unit BL1, the second emission clock ECLK2, the emission reset voltage ERST, and the high potential voltage Vdd. and the low potential voltage Vss to generate the first emission signal EM( 1 ).

That is, in the related art, the gate driver is configured by separately forming a shift register and an emission driving circuit for generating a scan signal and an emission signal, whereas in the second embodiment, the shift register and the emission driving circuit are integrated into one to form a gate driver. It is characterized by composition.

Specifically, the first circuit unit BL1 includes first to thirteenth transistors T1 to T13 and a first driving capacitor Cd1.

The first transistor T1 has a gate electrode connected to a terminal to which the start voltage VST is supplied, a source electrode connected to a terminal to which a high potential voltage Vdd is supplied, and a source electrode connected to the second transistor T2. A drain electrode is connected.

The second transistor T2 has a gate electrode connected to a terminal to which the fourth gate clock GCLK4 is supplied, a source electrode connected to the drain electrode of the first transistor T1 , and a source electrode of the third transistor T3 . A drain electrode is connected to

The third transistor T3 has a gate electrode connected to a terminal to which the high potential voltage Vdd is supplied, a source electrode connected to the drain electrode of the second transistor T2, and a drain electrode connected to the Q1 node Q1. do.

The fourth transistor T4 has a gate electrode connected to a terminal to which the high potential voltage Vdd is supplied, a source electrode connected to the Q1 node Q1, and a drain electrode connected to the source electrode of the seventh transistor T7. do.

The fifth transistor T5 has a gate electrode connected to a terminal to which the high potential voltage Vdd is supplied, a source electrode connected to the Q1 node Q1, and a drain electrode connected to the source electrode of the eighth transistor T8. do.

The sixth transistor T6 has a gate electrode connected to a terminal to which the high potential voltage Vdd is supplied, a source electrode connected to the Q1 node Q1, and a drain electrode connected to the gate electrode of the tenth transistor T10. do.

The seventh transistor T7 has a gate electrode connected to a terminal to which a Q node reset voltage QRST is supplied, a source electrode connected to a drain electrode of the fourth transistor T4, and a low potential voltage Vss supplied. A drain electrode is connected to the terminal.

The eighth transistor T8 has a gate electrode connected to the QB1 node QB1, a source electrode connected to the drain electrode of the fifth transistor T5, and a drain electrode connected to a terminal to which the low potential voltage Vss is supplied. do.

The ninth transistor T9 has a gate electrode connected to a terminal to which the third gate clock GCLK3 is supplied, a source electrode connected to a terminal supplied with the high potential voltage Vdd, and a drain electrode connected to the QB1 node QB1. is connected

The tenth transistor T10 has a gate electrode connected to a terminal to which the start voltage VST is supplied, a source electrode connected to the QB1 node QB1, and a drain electrode connected to a terminal to which the low potential voltage Vss is supplied. do.

The eleventh transistor T11 has a gate electrode connected to the drain electrode of the sixth transistor T6, a source electrode connected to the QB1 node QB1, and a drain electrode connected to a terminal to which the low potential voltage Vss is supplied. do.

Here, the seventh to eleventh transistors T7 to T11 are configured as dual gates, but in other embodiments, they may be configured as single gates.

The twelfth transistor T11 has a gate electrode connected to the Q1 node Q1, a source electrode connected to a terminal to which the first gate clock GCLK1 is supplied, and a drain electrode connected to the first gate line GL1. Configures the first output node OUT1. At this time, the first driving capacitor Cd1 is positioned between the gate electrode and the drain electrode.

The thirteenth transistor T13 has a gate electrode connected to the QB1 node QB1, a source electrode connected to the drain electrode of the twelfth transistor T12, and a drain electrode connected to a terminal to which the low potential voltage Vss is supplied. do.

In addition, the second circuit unit BL2 includes 14th to 22nd transistors T13 to T21 and a second driving capacitor Cd2.

The 14th transistor T14 has a gate electrode connected to a terminal to which the second emission clock ECLK2 is supplied, a source electrode connected to a terminal to which the high potential voltage Vdd is supplied, and a drain to the Q2 node Q2. The electrode is connected.

The fifteenth transistor T15 has a gate electrode connected to the first gate line GL1 , a source electrode connected to a terminal to which the emission reset voltage QRST is supplied, and a drain electrode connected to the QB2 node QB2 . .

The sixteenth transistor T16 has a gate electrode connected to the QB2 node QB2, a source electrode connected to the Q2 node Q2, and a drain electrode connected to a terminal to which the low potential voltage Vss is supplied.

The seventeenth transistor T17 has a gate electrode connected to a terminal to which the second emission clock ECLK2 is supplied, a source electrode connected to the QB2 node QB2, and a drain to a terminal supplied with the low potential voltage Vss. The electrode is connected.

The eighteenth transistor T18 has a gate electrode connected to the first emission line EL( 1 ), a source electrode connected to a terminal to which a high potential voltage Vdd is supplied, and a drain electrode connected to the Q2 node Q2 . is connected

The 19th transistor T19 has a gate electrode connected to the first emission line EL( 1 ), a source electrode connected to a terminal to which a high potential voltage Vss is supplied, and a drain of the 21st transistor T21 . A drain electrode is connected to the electrode and the source electrode of the 22nd transistor T22.

The twentieth transistor T20 has a gate electrode connected to the Q2 node Q2, a source electrode connected to a terminal to which a high potential voltage Vdd is supplied, and a drain electrode connected to the first emission line EL(1). These are connected to configure the second output node OUT2. At this time, the second driving capacitor Cd2 is positioned between the gate electrode and the drain electrode.

The 21st transistor T21 has a gate electrode connected to the QB2 node QB2, a source electrode connected to the first emission line EL(1), and a drain electrode and a 22nd transistor of the 19th transistor T19. A drain electrode is connected to the source electrode of (T22).

The 22nd transistor T22 has a gate electrode connected to the QB2 node QB2, a source electrode connected to a drain electrode of the 19th transistor T19 and a drain electrode of the 21st transistor T21, and a low potential voltage Vss ) is supplied to the drain electrode is connected to the terminal.

Although not shown, the second stage STG2 includes first and second circuit units BL1 and BL2 using the n-th scan signal Scan(n) instead of the start voltage VST. In addition, the first and second circuit units BL1 and BL2 of the second stage STG2 have a configuration similar to that of the first and second circuit units BL1 and BL2 of the first stage STG1.

In the first circuit unit BL1 of the second stage STG2, the first transistor T1 is a first output node of the first circuit unit BL1 of the first stage STG1 instead of the terminal to which the start voltage VST is supplied. The gate is connected to (OUT1). The gate of the second transistor T2 is connected to a terminal to which the first gate clock GCLK1 is supplied instead of the terminal to which the fourth gate clock GCLK4 is supplied. The gate of the fourth transistor T9 is connected to a terminal to which the fourth gate clock GCLK4 is supplied instead of the terminal to which the third gate clock GCLK3 is supplied.

In addition, the first output node OUT1 of the second stage STG2 includes the second gate line GL2, the second circuit unit BL2 of the second stage STG2, and the first circuit unit of the third stage STG3 (STG3). The second scan signal Scan(2) connected to BL1 and output from the first output node OUT1 of the second stage STG2 is the second gate line GL2 and the second stage STG2. It is supplied to the second circuit unit BL2 and the first circuit unit BL1 of the third stage STG3.

In the second circuit unit BL2 of the second stage STG2, the 14th and 17th transistors T14 and T17 each have a third emission clock ECLK3 instead of a terminal to which the second emission clock ECLK2 is supplied. A gate is connected to the supplied terminal.

And, the second output node OUT2 of the second stage STG2 is connected to the second emission line EL2, and the second emission output from the second output node OUT2 of the second stage STG2 is The signal EM( 2 ) is supplied to the second emission line EL2 .

Although not shown, the remaining stages STG3 to STGp also have a connection structure similar to that of the second stage STG2, and the first to pth stages STG1 to STGp form a dependent connection relationship with each other and are connected through respective output nodes. A scan signal and a light emission control signal are sequentially output.

For example, the arbitrary n-th stage STGn includes the high potential voltage Vdd, the low potential voltage Vss, the (n-1)th scan signal Scan(n-1), the first and third and an nth scan signal Scan(n) using the fourth gate clocks GCLK1, GCLK3, GCLK4, the Q node reset voltage QRST, the second emission clock ECLK2, and the emission reset voltage ERST. and the nth emission signal EM(n) are output, and the nth scan signal Scan(n) and the nth emission signal EM(n) correspond to the nth horizontal pixel column HPLn, respectively. may be supplied to the n-th gate line GLn and the n-th emission line ELn.

And, an arbitrary (n+1)th stage STG(n+1) is a high potential voltage Vdd, a low potential voltage Vss, an nth scan signal Scan(n), the first, The (n+1)th scan signal (n+1) using the second and fourth gate clocks GCLK1, GCLK2, GCLK4, Q node reset voltage QRST, third emission clock ECLK3, and emission reset voltage ERST Scan(n+1)) and (n+1)th emission signal EM(n+1)) are output, and (n+1)th scan signal Scan(n+1)) and (n+)th emission signal EM(n+1) are output. 1) The emission signal EM(n+1) is the (n+1)th gate line GL(n+1) corresponding to the (n+1)th horizontal pixel column HPL(n+1), respectively. ) and the (n+1)th emission line EL(n+1).

Also, in the above description, the transistor is a P-type transistor as an example, but one or more of them may be configured as an N-type transistor.

The operating characteristics of such a gate driver will be described with reference to the drawings.

12 is a timing diagram according to operation characteristics of a gate driver of an organic light emitting diode display according to a second embodiment of the present invention, which will be described with reference to FIG. 11 .

12, when the start voltage VST and the fourth gate clock GCLK4 are synchronized and input to the first circuit unit BL1 of the first stage STG1, the first and second transistors T1 and T2 ) is turned on, so that the Q1 node Q1 is in a logic high state corresponding to the high potential voltage Vdd. The twelfth transistor T12 connected thereto also becomes a logic high state. That is, it is ready. Subsequently, when the first gate clock GCLK1 is input, the twelfth transistor T12 in the ready state is turned on and outputs the first scan signal Scan( 1 ). At this time, the output first scan signal Scan(1) is applied to the 15th transistor T15 of the first gate line GL1 and the second circuit unit BL2 and the first circuit unit BL1 of the second stage STG2. is entered as

Although not shown, when the first scan signal Scan(1) and the first gate clock GCLK1 are input to the first circuit unit BL1 of the second stage STG2, the first and second transistors T1 and T2 is turned on, so that the Q1 node Q1 is in a logic high state corresponding to the high potential voltage Vdd, and the twelfth transistor T12 connected to the Q1 node Q1 is in a ready state. Subsequently, when the second gate clock GCLK2 is input, the twelfth transistor T12 in the ready state is turned on and a (2) second scan signal Scan(2) is output. At this time, the output second scan signal Scan(2) is the second gate line GL2 and the fifteenth transistor T15 of the second circuit unit BL2 of the second stage STG2 and the third stage STG3. is input to the first circuit unit BL1 of

That is, the first circuit unit BL1 of the second stage STG2 corresponds to the first scan signal Scan(1) output from the first circuit unit BL1 of the first stage STG1 to the start voltage VST. The voltage is supplied to the output voltage, and a second scan signal Scan(2) is output. In other words, the first circuit unit BL1 of the second stage STG2 operates based on the first scan signal Scan( 1 ) of the first circuit unit BL1 of the first stage STG1 . Accordingly, the first circuit units BL1 of the third to pth stages STG3 to STGp located in the dependent stages have a dependent connection relationship with each other, and operate based on the scan signal output from the previous stage.

On the other hand, when the first scan signal Scan(1) in the logic low state and the emission reset voltage ERST in the logic high state are input to the second circuit unit BL2 of the first stage STG1, the 21st, 22 The transistors T21 and T22 are turned off, and the first emission signal EM( 1 ) maintains the previous logic low state.

Next, when the first scan signal Scan(1) in the logic low state and the emission reset voltage ERST in the logic low state are input to the second circuit unit BL2 of the first stage STG1, the twentieth transistor ( T20) is turned on, and the high potential voltage Vdd is output as the first emission signal EM(1). That is, the first emission signal EM( 1 ) maintaining the logic low state is changed to the logic high state.

Next, when the first scan signal Scan(1) in a logic high state is input to the second circuit unit BL2 of the first stage STG1, the fifteenth transistor T15 is turned off, and the first emission Signal EM( 1 ) maintains its previous logic high state.

Next, when the second emission clock ECLK2 is input to the second circuit unit BL of the first stage STG1, the 21st and 22nd transistors T21 and T22 are turned on and maintain a logic high state. The previously used first emission signal EM( 1 ) is changed to a logic low state.

Although not shown, when the second scan signal Scan(2) in the logic low state and the emission reset voltage ERST in the logic high state are input to the second circuit unit BL2 of the second stage STG2, the 21st , 22 , the transistors T21 and T22 are turned off, and the second emission signal EM2 maintains the previous logic low state.

Next, when the second scan signal Scan(2) in the logic low state and the emission reset voltage ERST in the logic low state are input to the second circuit unit BL2 of the second stage STG2, the twentieth transistor ( T20) is turned on, and the high potential voltage Vdd is output as the second emission signal EM2. That is, the second emission signal EM2 maintaining the logic low state is changed to the logic high state.

Next, when the second scan signal Scan(2) in a logic high state is input to the second circuit unit BL2 of the second stage STG2, the fifteenth transistor T15 is turned off, and the second emission Signal EM2 maintains its previous logic high state.

Next, when the third emission clock ECLK3 is input to the second circuit unit BL of the second stage STG2, the 21st and 22nd transistors T21 and T22 are turned on and maintain a logic high state. The previously used second emission signal EM2 is changed to a logic low state.

As described above, the subsequent circuit units are connected in a dependent connection relationship to sequentially output the emission control signal.

Here, during the first period TP1 in which the nth scan signal Scan(n) has a logic low state and the nth emission signal EM(n) has a logic low state, each pixel (P in FIG. 9 ) The gate electrode of the driving transistor (DTr in FIG. 9) is initialized. Then, during the second period TP2 in which the n-th scan signal Scan(n) has a logic low state and the n-th emission signal EM(n) has a logic high state, the m-th data voltage Vdata(m) )) and the threshold voltage Vth of the driving transistor (DTr in FIG. 9 ) are stored in the pixel capacitor (Cp in FIG. 9 ). Then, during the third period TP3 in which the n-th scan signal Scan(n) has a logic high state and the n-th emission signal EM(n) has a logic high state, the driving transistor (DTr in FIG. 9 ) The m-th data voltage Vdata(m) and the threshold voltage Vth of the driving transistor (DTr in FIG. 9) are maintained at the gate electrode of . Then, during the fourth period TP4 in which the n-th scan signal Scan(n) has a logic high state and the n-th emission signal EM(n) has a logic low state, the organic light emitting diode (E of FIG. 9) ) emits light.

Meanwhile, in the conventional case, the scan signal generated by the scan signal generating unit is applied to the gate line, and the emission signal generating unit is turned on to the QB node of the inverter circuit using the signal generated from the shift register of the emission signal generating unit. In contrast to controlling turn-off, in the second embodiment, the n-th scan signal Scan(n) generated in the first circuit unit BL1 of each stage is applied to the 14th transistor T14 of the second circuit unit BL2. is supplied to to control the second circuit unit BL2, and when the n-th scan signal Scan(n) is in a logic high state, the voltage of the QB2 node QB2 is floated, and this causes the 21st, The operation characteristics of the 22nd transistors T21 and T22 may become unstable, so that the nth emission signal EM(n) may operate unstable.

In order to solve this problem, the first to fourth emission clocks ECLK1 to ECLK4 and the 17th transistor T17 are used to control the QB2 node QB2 to maintain a constant voltage. (The order in which the second emission clock ECLK2 is input can be changed as needed.)

That is, when the n-th emission signal EM(n) is in a logic low state, the second emission clock ECLK2 is used to set the QB2 node QB2 to a logic low state and the 21st and 22nd transistors T21 , T22) is turned on to operate, and when the n-th emission signal EM(n) is in a logic high state, the twentieth transistor T20 is turned on by the emission reset voltage ERST and the 2 Boosting by using the driving capacitor (Cd2).

The gate driver according to the second embodiment of the present invention is disposed in a mounting region having a width of about 841 μm by combining the first circuit part BL1 and the second circuit part BL2, whereas the conventional gate driver has a width of about 1150 μm. placed in a mounting area with Accordingly, the gate driver according to the second embodiment of the present invention has the effect of reducing the mounting area by about 26.9% compared to the conventional gate driver. In addition, as the number of circuits constituting the gate driver is reduced, a control signal line applied to each circuit is reduced, so that a narrow bezel can be implemented.

VST : start voltage VDD : high potential voltage
VSS : Low potential voltage GCLK : Gate clock
ECLK : Emission clock ERST : Emission reset voltage
Scan(n) : Scan signal EM(n) : Emission signal
BL1: first circuit unit BL2: second circuit unit

Claims (14)

a display panel including a plurality of pixels;
a data driver supplying a data signal to the plurality of pixels;
A gate driver for supplying a plurality of scan signals and a plurality of emission signals to the plurality of pixels including a plurality of stages,
at least one of the plurality of stages includes: a gate driver including a first circuit unit generating the scan signal and a second circuit unit generating the emission signal using the scan signal;
a timing controller that supplies a control signal to the data driver and the gate driver
including,
The first circuit unit of the nth stage generates an nth scan signal using the (n-1)th scan signal, a plurality of gate clocks, a high potential voltage and a low potential voltage,
The second circuit unit of the nth stage is configured to generate an nth emission signal using the nth scan signal, a plurality of emission clocks, an emission reset voltage, the high potential voltage, and the low potential voltage. diode display.
delete The method of claim 1,
The first circuit unit of the first stage generates a first scan signal using a start voltage, the plurality of gate clocks, the high potential voltage, and the low potential voltage,
The second circuit unit of the first stage uses the start voltage, the first scan signal, the plurality of emission clocks, the emission reset voltage, the high potential voltage, and the low potential voltage to generate a first emission An organic light emitting diode display that generates a signal.
The method of claim 1,
The plurality of gate clocks include first to fifth gate clocks, and the plurality of emission clocks include first to fifth emission clocks.
The method of claim 1,
The first circuit unit includes N-type first to eleventh transistors and a first capacitor,
The second circuit unit includes an N-type twelfth to twenty-second transistors and a second capacitor.
6. The method of claim 5,
A gate electrode of the first transistor is connected to a supply terminal of a start voltage and one of the first circuit parts of a previous stage, a drain electrode of the first transistor is connected to a supply terminal of the high potential voltage, and the first transistor A source electrode of the second transistor is connected to the drain electrode,
The gate electrode of the second transistor is connected to one of the supply terminals of the plurality of gate clocks, the drain electrode of the second transistor is connected to the source electrode of the first transistor, and the source electrode of the second transistor is the connected to the drain electrode of the third transistor,
The gate electrode of the third transistor is connected to the supply terminal of the high potential voltage, the drain electrode of the third transistor is connected to the source electrode of the second transistor, and the source electrode of the third transistor is connected to the Q1 node. become,
The gate electrode of the fourth transistor is connected to the supply terminal of the high potential voltage, the drain electrode of the fourth transistor is connected to the Q1 node, and the source electrode of the fourth transistor is connected to the drain electrode of the sixth transistor. connected,
The gate electrode of the fifth transistor is connected to the supply terminal of the high potential voltage, the drain electrode of the fifth transistor is connected to the Q1 node, and the source electrode of the fifth transistor is connected to the gate electrode of the ninth transistor. connected,
The gate electrode of the sixth transistor is connected to the QB1 node, the drain electrode of the sixth transistor is connected to the source electrode of the fourth transistor, and the source electrode of the sixth transistor is connected to the supply terminal of the low potential voltage. become,
The gate electrode of the seventh transistor is connected to one of the supply terminals of the plurality of gate clocks, the drain electrode of the seventh transistor is connected to the supply terminal of the high potential voltage, and the source electrode of the seventh transistor is the connected to the QB1 node,
The gate electrode of the eighth transistor is connected to the supply terminal of the start voltage and one of the first circuit portion of the previous stage, the drain electrode of the eighth transistor is connected to the QB1 node, the source electrode of the eighth transistor is connected to the supply terminal of the low potential voltage,
The gate electrode of the ninth transistor is connected to the source electrode of the fifth transistor, the drain electrode of the ninth transistor is connected to the QB1 node, and the source electrode of the ninth transistor is connected to the supply terminal of the low potential voltage. connected,
The gate electrode of the tenth transistor is connected to the Q1 node, the drain electrode of the tenth transistor is connected to one of the supply terminals of the plurality of gate clocks, and the source electrode of the tenth transistor is connected to the eleventh transistor. connected to the drain electrode,
The gate electrode of the eleventh transistor is connected to the QB1 node, the drain electrode of the eleventh transistor is connected to the source electrode of the tenth transistor, and the source electrode of the eleventh transistor is connected to the supply terminal of the low potential voltage. connected,
the first capacitor is connected between the gate electrode and the source electrode of the tenth transistor;
A first output node between the source electrode of the tenth transistor and the drain electrode of the eleventh transistor is connected to a gate line of the display panel, the second circuit unit, and a next stage.
6. The method of claim 5,
The gate electrode of the twelfth transistor is connected to one of the supply terminals of the plurality of emission clocks, the drain electrode of the twelfth transistor is connected to the supply terminal of the high potential voltage, and the source electrode of the twelfth transistor is Q2 connected to the node,
The gate electrode of the thirteenth transistor is connected to one of the supply terminals of the plurality of emission clocks, and the drain electrode of the thirteenth transistor is connected to the supply terminal of the start voltage and one of the first circuit units of the previous stage, The source electrode of the thirteenth transistor is connected to the QB2 node,
The gate electrode of the 14th transistor is connected to the QB2 node, the drain electrode of the 14th transistor is connected to the Q2 node, the source electrode of the 14th transistor is connected to the supply terminal of the low potential voltage,
A gate electrode of the fifteenth transistor is connected to a supply terminal of the emission reset voltage, a drain electrode of the fifteenth transistor is connected to a supply terminal of the high potential voltage, and a source electrode of the fifteenth transistor is connected to the sixteenth transistor. connected to the drain electrode of the transistor,
The gate electrode of the 16th transistor is connected to the first output node of the first circuit part, the drain electrode of the 16th transistor is connected to the source electrode of the 15th transistor, and the source electrode of the 16th transistor is the QB2 connected to the node,
The gate electrode of the seventeenth transistor is connected to one of the supply terminals of the plurality of emission clocks, the drain electrode of the seventeenth transistor is connected to the QB2 node, and the source electrode of the seventeenth transistor is connected to the low potential voltage connected to the supply terminal of
The gate electrode of the 18th transistor is connected to a second output node of the second circuit part, the drain electrode of the 18th transistor is connected to the supply terminal of the high potential voltage, and the source electrode of the 18th transistor is the 21st connected to the source electrode of the transistor,
The gate electrode of the 19th transistor is connected to one of the supply terminals of the plurality of emission clocks, the drain electrode of the 19th transistor is connected to the QB2 node, and the source electrode of the 19th transistor is connected to the low potential voltage. connected to the supply terminal of
The gate electrode of the twentieth transistor is connected to the Q2 node, the drain electrode of the twentieth transistor is connected to the supply terminal of the high potential voltage, and the source electrode of the twentieth transistor is connected to the drain electrode of the twenty-first transistor. connected,
The gate electrode of the twenty-first transistor is connected to the QB2 node, the drain electrode of the twenty-first transistor is connected to the source electrode of the twentieth transistor, and the source electrode of the twenty-first transistor is connected to the drain electrode of the twenty-second transistor. connected,
The gate electrode of the 22nd transistor is connected to the QB2 node, the drain electrode of the 22nd transistor is connected to the source electrode of the 21st transistor, and the source electrode of the 22nd transistor is connected to the supply terminal of the low potential voltage. connected,
the second capacitor is connected between the gate electrode and the source electrode of the twentieth transistor;
The second output node between the source electrode of the twentieth transistor and the drain electrode of the twenty-first transistor is connected to an emission line of the display panel.
The method of claim 1,
The first circuit unit of the first stage generates a first scan signal using a start voltage, the plurality of gate clocks, a Q node reset voltage, the high potential voltage, and the low potential voltage,
The second circuit unit of the first stage generates a first emission signal using the first scan signal, the plurality of emission clocks, the emission reset voltage, the high potential voltage, and the low potential voltage. Organic light emitting diode display.
The method of claim 1,
The plurality of gate clocks include first to fourth gate clocks, and the plurality of emission clocks include first to fourth emission clocks.
The method of claim 1,
The first circuit unit includes P-type first to thirteenth transistors and a first capacitor,
The second circuit unit includes P-type 14th to 22nd transistors and a second capacitor.
11. The method of claim 10,
A gate electrode of the first transistor is connected to a supply terminal of a start voltage and one of the first circuit parts of a previous stage, a source electrode of the first transistor is connected to a supply terminal of the high potential voltage, and the first transistor The drain electrode of the is connected to the source electrode of the second transistor,
The gate electrode of the second transistor is connected to one of the supply terminals of the plurality of gate clocks, the source electrode of the second transistor is connected to the drain electrode of the first transistor, and the drain electrode of the second transistor is the connected to the source electrode of the third transistor,
The gate electrode of the third transistor is connected to the supply terminal of the high potential voltage, the source electrode of the third transistor is connected to the drain electrode of the second transistor, and the drain electrode of the third transistor is connected to the Q1 node. become,
The gate electrode of the fourth transistor is connected to the supply terminal of the high potential voltage, the source electrode of the fourth transistor is connected to the Q1 node, and the drain electrode of the fourth transistor is connected to the source electrode of the seventh transistor. connected,
The gate electrode of the fifth transistor is connected to the supply terminal of the high potential voltage, the source electrode of the fifth transistor is connected to the Q1 node, and the drain electrode of the fifth transistor is connected to the source electrode of the eighth transistor. connected,
The gate electrode of the sixth transistor is connected to the supply terminal of the high potential voltage, the source electrode of the sixth transistor is connected to the Q1 node, and the drain electrode of the sixth transistor is connected to the gate electrode of the eleventh transistor. connected,
A gate electrode of the seventh transistor is connected to a supply terminal of a Q node reset voltage, a source electrode of the seventh transistor is connected to a drain electrode of the fourth transistor, and a drain electrode of the seventh transistor is connected to the low potential voltage. connected to the supply terminal of
The gate electrode of the eighth transistor is connected to the QB1 node, the source electrode of the eighth transistor is connected to the drain electrode of the fifth transistor, and the drain electrode of the eighth transistor is connected to the supply terminal of the low potential voltage. become,
The gate electrode of the ninth transistor is connected to one of the supply terminals of the plurality of gate clocks, the source electrode of the ninth transistor is connected to the supply terminal of the high potential voltage, and the drain electrode of the ninth transistor is connected to the connected to the QB1 node,
The gate electrode of the tenth transistor is connected to the supply terminal of the start voltage and one of the first circuit parts of the previous stage, the source electrode of the tenth transistor is connected to the QB1 node, and the drain electrode of the tenth transistor is connected to the supply terminal of the low potential voltage,
The gate electrode of the eleventh transistor is connected to the drain electrode of the sixth transistor, the source electrode of the eleventh transistor is connected to the QB1 node, and the drain electrode of the eleventh transistor is connected to the supply terminal of the low potential voltage. connected,
The gate electrode of the twelfth transistor is connected to the Q1 node, the source electrode of the twelfth transistor is connected to one of the supply terminals of the plurality of gate clocks, and the drain electrode of the twelfth transistor is connected to the thirteenth transistor. connected to the source electrode,
The gate electrode of the thirteenth transistor is connected to the QB1 node, the source electrode of the thirteenth transistor is connected to the drain electrode of the twelfth transistor, and the drain electrode of the thirteenth transistor is connected to the supply terminal of the low potential voltage. connected,
the first capacitor is connected between the gate electrode and the source electrode of the tenth transistor;
A first output node between the drain electrode of the twelfth transistor and the source electrode of the thirteenth transistor is connected to a gate line of the display panel, the second circuit unit, and a next stage.
11. The method of claim 10,
The gate electrode of the 14th transistor is connected to one of the supply terminals of the plurality of emission clocks, the source electrode of the 14th transistor is connected to the supply terminal of the high potential voltage, and the drain electrode of the 14th transistor is Q2 connected to the node,
A gate electrode of the fifteenth transistor is connected to a first output node of the first circuit part, a source electrode of the fifteenth transistor is connected to a supply terminal of the emission reset voltage, and a drain electrode of the fifteenth transistor is connected to the connected to the QB2 node,
The gate electrode of the 16th transistor is connected to the QB2 node, the source electrode of the 16th transistor is connected to the Q2 node, the drain electrode of the 16th transistor is connected to the supply terminal of the low potential voltage,
The gate electrode of the seventeenth transistor is connected to one of the supply terminals of the plurality of emission clocks, the source electrode of the seventeenth transistor is connected to the QB2 node, and the drain electrode of the seventeenth transistor is connected to the low potential voltage connected to the supply terminal of
A gate electrode of the eighteenth transistor is connected to a second output node of the second circuit unit, a source electrode of the eighteenth transistor is connected to a supply terminal of the high potential voltage, and a drain electrode of the eighteenth transistor is connected to the Q2 connected to the node,
The gate electrode of the 19th transistor is connected to the second output node, the source electrode of the 19th transistor is connected to the supply terminal of the high potential voltage, and the drain electrode of the 19th transistor is the drain of the 21st transistor. connected to the electrode,
The gate electrode of the twentieth transistor is connected to the Q2 node, the source electrode of the twentieth transistor is connected to the supply terminal of the high potential voltage, the drain electrode of the twentieth transistor is connected to the second output node, and ,
The gate electrode of the twenty-first transistor is connected to the QB2 node, the source electrode of the twenty-first transistor is connected to the second output node, the drain electrode of the twenty-first transistor is connected to the source electrode of the twenty-second transistor, and ,
The gate electrode of the 22nd transistor is connected to the QB2 node, the source electrode of the 22nd transistor is connected to the drain electrode of the 21st transistor, and the source electrode of the 20th transistor is connected to the supply terminal of the high potential voltage. connected,
the second capacitor is connected between the gate electrode and the drain electrode of the twentieth transistor;
The second output node between the drain electrode of the twentieth transistor and the source electrode of the twenty-first transistor is connected to an emission line of the display panel.
The method of claim 1,
Each of the plurality of pixels includes an organic light emitting diode, an emission transistor, a switching transistor, a driving transistor, an initialization transistor, and first and second pixel capacitors,
The emission transistor, the switching transistor, the driving transistor, and the initialization transistor are each of an N-type organic light emitting diode display.
The method of claim 1,
Each of the plurality of pixels includes an organic light emitting diode, first to fifth pixel transistors, and a pixel capacitor,
Each of the first to fifth pixel transistors is a P-type organic light emitting diode display.

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