KR102291634B1 - Display apparatus possible selectively performing progressive scan and interlaced scan - Google Patents

Abstract

The present invention relates to a display device capable of selectively driving of progressive scan and interlaced scan. A display device capable of selectively driving progressive scan and interlaced scan, according to an aspect of the present invention, comprises: a display panel including a plurality of sub-pixels disposed along a plurality of rows and columns, a plurality of scan lines connected to sub-pixels along the row, a plurality of source lines connected to the subpixels along the column; a mode selection unit for selecting any one of a first mode and a second mode different from the first mode according to a user input; and a driving unit which sequentially outputs a scan signal to the plurality of scan lines when the first mode is selected by the mode selection unit, sequentially outputs a scan signal to one of the scan lines in odd rows or the scan lines in even rows from among the plurality of scan lines when the second mode is selected by the mode selection unit, and sequentially outputs a scan signal to the other one. According to the present invention, color loss due to image difference is prevented from occurring.

Description

Display device capable of selectively driving progressive scan and interlaced scan

The present invention relates to a display device capable of selectively driving progressive scan and interlaced scan, and more particularly, selective driving of progressive scan and interlaced scan capable of selectively driving progressive scan and interlaced scan according to user needs. It relates to possible display devices.

The demand for AMOLED screens is increasing according to the demands for high contrast and flexibility in mobile phones. In order to increase pixels per inch (PPI) in an AMOLED screen, a subpixel rendering (SPR) structure in which red and blue pixels are arranged in a zigzag in the vertical direction is used.

In the case of simply applying the conventional progressive scan driving method in which an active signal is sequentially applied to a plurality of scan lines in a display panel having an SPR structure, the output of the source line changes the luminance voltage of the red pixel once and the luminance voltage of the blue once again. Since it is necessary to output the luminance voltage of the pixel, there is a problem in that power consumption increases as the voltage is repeatedly changed.

In order to solve this problem, a display technology to which an interlaced driving method is applied has been disclosed, but in the case of the interlaced driving, there is a difficulty in that a color loss phenomenon occurs due to an image difference between two consecutive frames.

For this reason, a technology related to a scan driver capable of selectively performing a progressive scan operation and an interlaced scan operation has been proposed, but such a conventional technology requires a large number of gates and a large number of wirings to selectively perform the progressive scan operation and the interlace scan operation. Because it is complicated, it is difficult to apply to the bezel of the actual panel, and there is a problem in forming a narrow bezel especially in mobile.

Republic of Korea Patent No. 10-0601377 Republic of Korea Patent No. 10-1493276

An object of the present invention is to solve the above problems, and it is an object of the present invention to provide a display device capable of selectively driving progressive scan and interlaced scan, which can selectively drive progressive scan and interlaced scan according to user needs. .

Objects of the present invention are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood from the description below.

A display device capable of selectively driving progressive scan and interlaced scan according to an aspect of the present invention for achieving the above object includes a plurality of sub-pixels arranged along a plurality of rows and columns, and sub-pixels along the rows; A display panel including a plurality of scan lines connected to each other and a plurality of source lines connected to the sub-pixels along a column, any one of a first mode or a second mode different from the first mode according to a user input When the first mode is selected by the mode selection unit and the mode selection unit for selecting , scan signals are sequentially output to a plurality of scan lines. Alternatively, a driving unit that sequentially outputs a scan signal first to any one of the scan lines of even rows and sequentially outputs a scan signal to the other one is included.

According to the present invention, there is an effect of providing a display device capable of selectively driving progressive scan and interlaced scan according to a user's input.

In addition, according to the present invention, since the scan driving unit is configured with a relatively small number of gates, there is an advantage in that progressive scan and interlaced scan can be selectively driven in a display having a narrow bezel.

According to the present invention, in the sub-pixel rendering structure, a display panel is provided in which sub-pixels in each row are respectively connected to at least two scan lines, and at least one red sub-pixel, blue sub-pixel, and green sub-pixels are respectively connected to each scan line. By performing interlaced scanning according to the input of

The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a diagram illustrating a display device capable of selectively driving progressive scan and interlaced scan according to an embodiment of the present invention.
2 is a diagram illustrating a display panel of a display device capable of selectively driving progressive scan and interlaced scan according to an embodiment of the present invention.
3 is a block diagram illustrating a scan driving circuit unit according to an embodiment of the present invention.
4 is a block diagram illustrating a scan driving circuit unit according to another embodiment of the present invention.
FIG. 5A shows the configuration of the scan driving unit as a logic circuit when the display panel is a PMOS type according to embodiments of the present invention.
5B is a circuit diagram illustrating a configuration of a scan driving unit when a display panel is a PMOS type according to embodiments of the present invention.
6A is a timing diagram for explaining an operation of a scan driving unit when a first mode is selected when a display panel is a PMOS type according to embodiments of the present invention.
6B is a timing diagram for explaining the operation of the scan driving unit when the second mode is selected when the display panel is a PMOS type according to embodiments of the present invention.
7A is a timing diagram for explaining the operation of the scan driving circuit unit when the first mode is selected when the display panel is a PMOS type according to embodiments of the present invention.
7B is a timing diagram for explaining the operation of the scan driving circuit unit when the second mode is selected when the display panel is a PMOS type according to embodiments of the present invention.
8A is a diagram illustrating a configuration of a scan driving unit as a logic circuit when the display panel is an NMOS type according to embodiments of the present invention.
8B is a circuit diagram illustrating a configuration of a scan driving unit when a display panel is an NMOS type according to embodiments of the present invention.
9A is a timing diagram for explaining the operation of the scan driving unit when the first mode is selected when the display panel is an NMOS type according to embodiments of the present invention.
9B is a timing diagram for explaining the operation of the scan driving unit when the second mode is selected when the display panel is an NMOS type according to embodiments of the present invention.
10, 11, and 12 are block diagrams illustrating the arrangement of a scan driving unit in a display device capable of selectively driving progressive scan and interlaced scan according to embodiments of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains. It is provided to fully inform the person of the scope of the invention, and the present invention is only defined by the description of the claims. On the other hand, the terms used in the present specification are for describing the embodiments, and are not intended to limit the present invention. As used herein, the singular also includes the plural unless specifically stated otherwise in the phrase.

1 is a view showing a display device capable of selectively driving progressive scan and interlaced scan according to an embodiment of the present invention. Referring to FIG. 1 , selective operation of progressive scan and interlaced scan according to an embodiment of the present invention The display device 10 capable of being driven may include a display panel 100 , a mode selection unit 200 , and a driving unit 300 .

2 is a diagram illustrating a display panel of a display device capable of selectively driving progressive scan and interlaced scan according to an embodiment of the present invention.

Referring to FIG. 2 , a display panel 100 according to an embodiment of the present invention includes a plurality of subpixels disposed along a plurality of rows and columns, and a plurality of subpixels connected to the subpixels along the rows. It may include scan lines scan1, scan2, ..., scanM and a plurality of source lines source1, source2, ..., sourceN connected to subpixels along a column.

The sub-pixels may each correspond to any one of the first color, the second color, and the third color.

Here, the first color is any one of red, blue, and green, the second color is any one of red, blue, and green except for the first color, and the third color is a first color and a second color among red, blue, and green. It may be any one other than the color, but is not limited thereto.

The mode selector 200 may receive selection of either the first mode or a second mode different from the first mode according to a user's input.

When the first mode is selected by the mode selector 200 , the driving unit 300 sequentially outputs a scan signal to the plurality of scan lines scan1 , scan2 , ..., scanM, and the mode selector 200 selects the second mode. When the mode is selected, a scan signal is first sequentially output to any one of the scan lines in odd rows or scan lines in even rows among the plurality of scan lines scan1, scan2, ..., scanM, and the scan signal is sequentially applied to the other one. It may be output.

That is, the driving unit 300 performs progressive scan driving for sequentially outputting scan signals to a plurality of scan lines according to the mode selected by the mode selector 200 , or one of odd-numbered scan lines or even-numbered scan lines. Interlaced scan driving in which a scan signal is sequentially output to one of them first and then a scan signal is sequentially output to the other one may be performed.

The driving unit 300 may include a clock generating unit 310 , a start signal generating unit 320 , and a scan driving circuit unit 330 .

The clock generator 310 includes a first odd clock CLKO1 , a second odd clock CLKO2 , and a first even clock each having a falling edge time or a rising edge time corresponding to the mode selected by the mode selector 200 . (CLKE1) and the second even clock (CLKE2) may be generated, respectively.

When the first mode is selected by the mode selection unit 200 , the clock generator 310 has different falling edge timing or rising edge timing, but having the same duty ratio as the first odd clock CLKO1 and the second odd clock CLKO2 . ), the first even-numbered clock CLKE1 and the second even-numbered clock CLKE2 may be generated, respectively.

When the second mode is selected by the mode selection unit 200, the clock generator 310 has different falling edge timing or rising edge timing, but having the same duty ratio. A first odd clock CLKO1 and a second odd clock CLKO2 are generated, and a first even clock CLKE1 identical to the second odd clock CLKO2 and a second even clock identical to the first odd clock CLKO1 are generated. CLKE2).

The clock generator 310 generates a clock signal /CLKO1 whose phase is opposite to each of the first odd clock CLKO1, the second odd clock CLKO2, the first even clock CLKE1, and the second even clock CLKE2. , /CLKO2, /CLKE1, /CLKE2) may be further created.

The start signal generator 320 generates a first start signal STV_O and a second start signal STV_E that have a high level or a low level state for a preset time, but have different falling edge times or rising edge times. can

The start signal generator 320 causes the first start signal STV_O to have a high level or a low level state for a preset time when the first mode is selected by the mode selector 200, but the second start signal STV_E A point at which the high-level or low-level state of the first start signal STV_O ends is the start time to have the high-level or low-level state for a preset time.

The start signal generator 320 causes the first start signal STV_O to have a high level or a low level state for a preset time when the second mode is selected by the mode selector 200, but the first start signal STV_O The second start signal STV_E may have a high level or a low level state for a preset time after a preset time at the time when the high-level or low-level state of is ended.

Here, the preset time means a time required to sequentially drive any one of the scanlines in odd rows or scanlines in even rows among the plurality of scanlines.

The scan driving circuit unit 330 includes a plurality of clock input terminals for receiving a first odd clock, a second odd clock, a first even clock, and a second even clock, and a start for receiving a first start signal or a second start signal. High level or low level of the first start signal or the second start signal at the time of the falling edge or the rising edge of each of the first odd clock, the second odd clock, the first even clock, and the second even clock having the signal input terminal It may include a plurality of scan driving units each outputting a scan signal according to a state.

3 is a block diagram illustrating a scan driving circuit unit according to an embodiment of the present invention, and FIG. 4 is a block diagram showing a scan driving circuit unit according to another embodiment of the present invention.

3 to 4 , scan driving circuit units 330a and 330b according to embodiments of the present invention include a first scan driving unit SDU1, a second scan driving unit SDU2, and a plurality of odd scan driving units. (SDU3, ..., SDU(2n-1), n≥2), and a plurality of even scan driving units SDU4, ..., SDU(2n), n≥2.

The first scan driving unit SDU1 receives a first start signal STV_O as a start signal input terminal, receives a first odd clock CLKO1 as a first clock input terminal, and receives a second odd clock signal CLKO2 as a second input terminal. A scan signal for driving a first scan line Scan1 among a plurality of scan lines connected to sub-pixels of the display panel 100 by being input through a clock input terminal is transmitted to a first scan line Scan1 of the display panel 100 . It may be output.

The second scan driving unit SDU2 receives the second start signal STV_E as a start signal input terminal, receives the first even clock CLKE1 as a first clock input terminal, and receives the second even clock CLKE2 as a second input terminal. A second scan line (Scan2) of the display panel 100 receives a scan signal for driving to a second scan line (Scan2) among a plurality of scan lines connected to sub-pixels of the display panel (100) by being input through a clock input terminal It may be output as .

Each of the plurality of odd scan driving units SDU3, ..., SDU(2n-1), n≥2 is the scan line Scan1, ..., Scan(2n-3), n≥2 of the odd row of the display panel 100 . ), the scan signal output to the first odd scan line is inputted through the start signal input terminal, and any one of the first odd clock CLKO1 and the second odd clock CLKO2 is inputted to the first clock input terminal The next hole of the first odd scan line in row order among the scan lines (Scan1, ..., Scan(2n-1), n≥2) of the odd row of the display panel 100 by receiving the other one as input to the second clock input terminal The scan signal may be output to the second odd line corresponding to the execution.

Each of the plurality of even-numbered scan driving units SDU4, ..., SDU(2n), n≥2 is any one of the scanlines Scan2, ..., Scan(2n), n≥2 of the even-numbered row of the display panel 100 . A scan signal output from one first even scan line is input to a start signal input terminal, any one of the first even clock CLKE1 and the second even clock CLKE2 is input to the first clock input terminal, and the other The second clock input terminal may output the scan signal to the second even line corresponding to the next even number of the first even scan line in row order among the scan lines in the even row of the display panel 100 .

The plurality of odd scan driving units SDU3, ..., SDU(2n-1), n≥2 receives the second odd clock CLKO2 as the first clock input terminal and receives the first odd clock CLKO1 as the second clock input terminal. A plurality of first odd scan driving units SDU3, ..., SDU(4n-1), n≥2 and a first odd-numbered clock CLKO1 received through may include a plurality of second odd scan driving units SDU5, ..., SDU(4n-3), n≧2 that receive the .

A plurality of first odd scan driving units SDU3, ..., SDU(4n-1), n≥2 and a plurality of second odd scan driving units SDU5, ..., SDU(4n-3), n≥2 are They may be alternately arranged along rows.

The plurality of even-numbered scan driving units SDU4, ..., SDU(2n), n≥2 receives the second even-numbered clock CLKE2 as a first clock input terminal and inputs the first even-numbered clock CLKE1 as a second clock input terminal. It receives the plurality of first even-numbered scan driving units SDU4, ..., SDU(4n), n≥2 and the first even-numbered clock CLKE1 as input to the first clock input terminal, and receives the second even-numbered clock CLKE2 as the second clock It may include a plurality of second even-numbered scan driving units SDU6, ..., SDU(4n-2), n≧2 received through the input terminal.

A plurality of first even scan driving units (SDU4, ..., SDU(4n), n≥2) and a plurality of second even scan driving units (SDU6, ..., SDU(4n-2), n≥2) They may be alternately arranged according to each other.

A first scan driving unit SDU1, a second scan driving unit SDU2, a plurality of odd scan driving units SDU3, ..., SDU(2n-1), n≥2, a plurality of even scan driving units SDU4, . can

In an embodiment, the first scan driving unit SDU1 receives the first even clock CLKE1 as the third clock, and the second scan driving unit SDU2 inputs the second odd clock CLKO2 as the third clock. The first odd-numbered scan driving units SDU3, ..., SDU(4n-1), n≥2 receive the second even-numbered clock CLKE2 as the third clock, and the first even-numbered scan driving units SDU4, ... , SDU(4n), n≥2 receives the first odd clock CLKO1 as the third clock, and the second odd scan driving unit SDU5, ..., SDU(4n-3, n≥2) receives the first odd-numbered clock CLKO1 as the third clock. The first even-numbered clock CLKE1 is input as the third clock, and the second even-numbered scan driving units SDU6, ..., SDU(4n-2, n≥2) input the second odd-numbered clock CLKO2 as the third clock. may be receiving

In another embodiment, a first scan driving unit SDU1, a second scan driving unit SDU2, a plurality of odd scan driving units SDU3, ..., SDU(2n-1), n≥2, a plurality of even scan driving units At least one of the units SDU4, .

Specifically, the first scan driving unit SDU1 receives the clock signal /CLKO1 having a phase opposite to that of the first odd-numbered clock CLKO1 as the third clock, and the second scan driving unit SDU2 receives the first even-numbered clock signal /CLKO1. The clock signal /CLKE1 having a phase opposite to that of the clock CLKE1 may be input as the third clock. In addition, the first odd scan driving unit SDU3, ..., SDU(4n-1), n≥2 receives the clock signal /CLKO2 out of phase with the second odd clock CLKO2 as the third clock, The first even-numbered scan driving unit SDU4, ..., SDU(4n), n≥2 receives a clock signal /CLKE2 whose phase is opposite to that of the second even-numbered clock CLKE2 as a third clock, and a second odd number The scan driving units SDU5, ..., SDU(4n-3), n≥2 receive the clock signal /CLKO1 out of phase with the first odd clock CLKO1 as the third clock, and perform a second even scan The driving units SDU6, .

The plurality of scan driving units SDU1, ..., SDUM of the scan driving circuit unit 330, 330a, 330b according to embodiments of the present invention outputs scan signals according to the first clock, the second clock, and the third clock, respectively. By doing so, a plurality of scan lines scan1, scan2, ..., scanM of the display panel 100 is sequentially driven, or a scan line corresponding to any one of odd or even rows is first sequentially driven and the other The corresponding scan lines are sequentially driven.

The plurality of scan driving units SDU1 , ..., SDUM of the scan driving circuit unit 330 , 330a , 330b according to embodiments of the present invention is one of the plurality of clocks generated according to the mode selected by the mode selector 200 . Progressive scan or interlaced scan can be selectively performed with a relatively simple configuration by receiving any one of the first clock, the second clock and the third clock, respectively, and outputting a scan signal according to the first clock, the second clock and the third clock. have.

Accordingly, it is possible to selectively drive progressive scan or interlaced scan in a narrow bezel.

Hereinafter, the configuration and operation of the scan driving circuit units 330, 330a, 330b in the display device 10 capable of selectively driving progressive scan and interlaced scan according to embodiments of the present invention will be described in more detail with reference to the drawings. let it do

5A is a diagram illustrating a configuration of a scan driving unit as a logic circuit when the display panel is of the PMOS type according to the embodiments of the present invention, and FIG. 5B is the scan driving when the display panel is of the PMOS type according to the embodiments of the present invention. It is a circuit diagram showing the configuration of the unit, and FIG. 6A is a timing diagram for explaining the operation of the scan driving unit when the first mode is selected when the display panel is a PMOS type in embodiments of the present invention, and FIG. 6B is this In embodiments of the present invention, when the display panel is of the PMOS type, it is a timing diagram for explaining the operation of the scan driving unit when the second mode is selected, and FIG. 7A is the display panel of the PMOS type in the embodiments of the present invention A timing diagram for explaining the operation of the scan driving circuit unit when the first mode is selected in the case of It is a timing diagram for explaining the operation of , and FIG. 8A shows the configuration of the scan driving unit as a logic circuit when the display panel is an NMOS type in the embodiments of the present invention, and FIG. 8B shows the configuration of the scan driving unit in the embodiments of the present invention In the present invention, it is a circuit diagram showing the configuration of the scan driving unit when the display panel is an NMOS type, and FIG. 9A explains the operation of the scan driving unit when the first mode is selected when the display panel is an NMOS type in embodiments of the present invention. 9B is a timing diagram for explaining the operation of the scan driving unit when the second mode is selected when the display panel is an NMOS type according to embodiments of the present invention.

Referring to FIGS. 5A and 8A , the scan driving units SDU1, ..., SDUM delay the start signal input to the start signal input terminal for a predetermined time according to the second clock CLK2 input from the second clock input terminal and output the first output signal. The buffers 501 and 801 and the second buffer 503 outputting the signal out1 output from the first buffers 501 and 801 are delayed for a predetermined time according to the first clock CLK1 input from the first clock input terminal. , 803), and operation units 505 and 805 for outputting a scan signal by ORing or ORing the signal out2 output from the second buffers 503 and 803 and the first clock CLK1. have.

In addition, referring to FIGS. 5B and 8B , the scan driving units SDU1, ..., SDUM receive the third clock CLK3 as a gate and perform switching operation of the transistors 507 and 807 and one end of the transistors 507 and 807. It may further include capacitors 509 and 809 connected to the source and the other end connected to the drain of the transistors 507 and 807 .

Here, the scan driving units SDU1, ..., SDUM receive the signals out2 and the first clock output from the second buffers 503 and 803 according to the switching operation of the transistor 507.807 by the third clock CLK3. When (CLK1) is ORed or ORed, the scan signal may be switched to a high level or a low level state.

The capacitors 509 and 809 are charged and discharged according to the switching operation of the transistors 507 and 807 and the outputs of the operation units 505 and 805, and the scan driving units SDU1, ..., SDUM are drains of the transistors 507 and 807. It may be to output a scan signal from this connected node.

Each of the scan driving units SDU1 , ..., SDUM according to embodiments of the present invention is different from the first clock CLK1 and the second clock CLK2 and the timing of the falling edge (or the timing of the rising edge) of the first clock CLK1 ), by further receiving the third clock CLK3 having a rising edge time (or a falling edge time) from the clock generator 310 , progressive and interlaced driving is selectively possible even with a simple configuration.

When the display panel 100 is of the PMOS type, the scan driving units SDU1, ..., SDUM transmit the start signal S, the first clock CLK1, the second clock CLK2, and the third clock CLK3, respectively. outputs a scan signal according to the low-level state of CLK2) and the third clock CLK3 respectively output a scan signal according to the high level state.

Referring to FIG. 7A , when the display panel 100 is a PMOS type, when the first mode is selected by the mode selector 200, the start signal generator 320 generates the first start signal STV_O for a preset time (eg, For example _{, the low-level state is maintained during Δt 1} ), but the second start signal STV_E is made to have a low-level state for a preset time when the low-level state of the first start signal STV_O ends.

When the display panel 100 is an NMOS type, when the first mode is selected by the mode selector 200, the start signal generator 320 sets the first start signal STV_O to have a high level state for a preset time. When the high-level state of the first start signal STV_O ends, the second start signal STV_E has the high-level state for a preset time.

When the display panel 100 is a PMOS type (or NMOS type), when the first mode is selected by the mode selector 200, the clock generator 310 generates a preset number from each falling edge time (or rising edge time). first predetermined multiple of the time (Δt _1), the low level (or high level) with the state, the first time (Δt ₁₎ from the low level (or high level) state is terminated rising edge point (or the falling edge point) are for (example 3) a second time (Δt ₂₎ during the high level (or low level), the first odd-numbered clock (CLKO1) having a state, the second odd-numbered clock according to the (CLKO2), first even clock (CLKE1), Each of the second even clocks CLKE2 may be generated.

5 and 6A, when the display panel 100 is of the PMOS type, the signal out1 output from the first buffer 501 of the scan driving units SDU1, ..., SDUM is the start signal S and It has a low level state from the first time point t1 which is the time of the falling edge of the second clock CLK2 to the fifth time point t5 which is the time point of the next falling edge of the second clock CLK2, and in the second buffer 503 The output signal out2 is synchronized with the signal out1 output from the first buffer 501 at a third time point t3 when the first clock CLK1 is the falling edge point of the first clock CLK1 following the polling of the first clock CLK1 . The edge time point is maintained until the seventh time point t7 , and has a low level state from the third time point t3 to the seventh time point t7 , and the operation unit 505 outputs the signal out2 output from the second buffer 503 . ) and the first clock CLK1 , the scan signal Scan having a low level state is output from the third time point t3 to the fourth time point t4 .

Referring to FIG. 7A , the first scan driving unit SDU 1 receives the first start signal STV_O as the start signal S and delays the time according to the second odd clock CLKO2 that is the second clock CLK2 . and output as a scan signal in synchronization with the first odd clock CLKO1 which is the first clock CLK1.

The second scan driving unit SDU 2 receives the second start signal STV_E as the start signal S, and delays the time according to the second even clock CLKE2 that is the second clock CLK2, and the first clock By outputting a scan signal to the scan line Scan2 of the second row in synchronization with the first even clock CLKE1 which is (CLK1), the low level state of the scan signal output to the scan line Scan1 of the first row is terminated The scan signal output to the scan line Scan2 of the second row from the time point is set to a low level state for a preset time.

In addition, the scan driving unit SDU 3 , which receives the scan signal Scan 1 output to the scan line Scan1 of the first row as a start signal, is time delayed according to the first odd clock CLKO1 which is the second clock CLK2 . and output as a scan signal to the third scan line Scan3 in synchronization with the second odd clock CLKO2 that is the first clock CLK1, and the low level of the scan signal output to the scan line Scan2 in the second row The scan signal output to the scan line Scan3 in the third row from the time when the state ends is made to be in the low level state for a preset time.

The scan driving circuit units 330 , 330a , 330b according to embodiments of the present invention sequentially output scan signals to the plurality of scan lines scan1 , scan2 , ..., scanM according to the above process.

Referring to FIG. 7B , when the second mode is selected by the mode selector 200, the start signal generator 320 causes the first start signal STV_O to have a low level state for a preset time Δt1, but the first When the low-level state of the start signal STV_O ends, the second start signal STV_E has a low-level state for a preset time after a preset time Timing A.

The clock generator 310 generates a first odd clock CLKO1 and a second odd clock CLKO2 having different falling edge timings but having the same duty ratio when the second mode is selected by the mode selection part 200, , a first even clock CLKE1 identical to the second odd clock CLKO2 , and a second even clock CLKE2 identical to the first odd clock CLKO1 may be generated.

When the second mode is selected by the mode selector 200, the first odd clock CLKO1, the second odd clock CLKO2, When the first even clock CLKE1 and the second even clock CLKE2 are generated by the clock generator 310, interlaced driving is possible, but the first odd clock CLKO1, the second odd clock CLKO2, and the first even clock There is a problem in that an unnecessary time delay occurs due to a time difference between the low-level or high-level states of the clock CLKE1 and the second even clock CLKE2 .

Accordingly, when the display panel 100 is a PMOS type (or an NMOS type), the clock generator 310 according to embodiments of the present invention performs a preset first time ( Δt ₁₎ the low level (or high level) with the state, the low level (or high level), the rising edge time point (or a falling edge when the state is completed) from a first time (Δt ₁₎ a high level for a while (or low level ) state, the first odd clock CLKO1 , the second odd clock CLKO2 , the first even clock CLKE1 , and the second even clock CLKE2 may be generated, respectively.

The clock generator 310 according to the embodiments of the present invention repeats a high-level or low-level state for the same time when the second mode is selected by the mode selector 200, and the first odd-numbered clocks having opposite phases An unnecessary time delay may be minimized by generating the CLKO1, the second odd clock CLKO2, the first even clock CLKE1, and the second even clock CLKE2, respectively.

Hereinafter, the driving of the scan driving units SDU1, ..., SDUM when the second mode is selected by the mode selection unit 200 when the display panel 100 is of the PMOS type will be described in more detail with reference to FIGS. 5 and 6B . let it do

When the display panel 100 is a PMOS type, when the second mode is selected by the mode selector 200, the signal out1 output from the first buffer 501 of the scan driving units SDU1, ..., SDUM starts The signal S and the second clock CLK2 may have a low-level state from a first time point t1 that is a falling edge point of the second clock CLK2 to a third time point t3 that is a next falling edge point of the second clock CLK2. .

In addition, the signal out2 output from the second buffer 503 is synchronized with the signal out1 output from the first buffer 501 at the second time point t2 which is the time of the falling edge of the first clock CLK1. The first clock CLK1 is maintained until the fourth time t4, which is the time of the next falling edge, and has a low level state from the second time t2 to the fourth time t4, and the operation unit 505 operates the second buffer A scan signal Scan having a low level state is output from the second time point t2 to the third time point t3 according to the logical OR of the signal out2 output at step 503 and the first clock CLK1 .

Referring to FIG. 7B , the first scan driving unit SDU 1 receives the first start signal STV_O as the start signal S and delays the time according to the second odd clock CLKO2 that is the second clock CLK2 . and output as a scan signal in synchronization with the first odd clock CLKO1 which is the first clock CLK1.

The scan driving unit SDU 3 receiving the scan signal Scan 1 output to the scan line Scan1 of the first row as a start signal delays the time according to the first odd clock CLKO1 which is the second clock CLK2, , output as a scan signal to the third scan line Scan3 in synchronization with the second odd clock CLKO2, which is the first clock CLK1, low level state of the scan signal output to the scan line Scan1 in the first row The scan signal output to the scan line Scan3 in the third row is set to a low level state for a preset time from the point in time when ?

In addition, when the low-level state of the last scan line Scan 2n-1 of the odd-numbered row ends, the second start signal STV_E is in the low-level state for a preset time, so that the second scan driving unit SDU 2 is Receives the second start signal STV_E as the start signal S, delays the time according to the second even clock CLKE2 that is the second clock CLK2, and the first even clock CLKE1 that is the first clock CLK1 ) and output as a scan signal to the scan line Scan2 of the second row, after the low-level state of the last scan line Scan 2n-1 of the odd-numbered row is terminated, The output scan signal is set to a low level state for a preset period of time.

The scan driving circuit units 330 , 330a , 330b according to the embodiments of the present invention sequentially apply first sequential scan signals to the scan lines of odd rows among the plurality of scan lines scan1 , scan2 , ..., scanM according to the above process. , and sequentially outputting scan signals to scan lines of even rows.

In the above description, the scan lines of odd rows are first sequentially driven and the scan lines of even rows are sequentially driven as an example. First, after sequentially outputting the scan signal, the scan signal may be sequentially outputted to the scan lines of odd rows.

8 to 9A, when the first mode is selected by the mode selector 200 when the display panel 100 is an NMOS type, the first buffer 801 of the scan driving units SDU1, ..., SDUM The signal out1 output from the start signal S and the first time t1 which is the rising edge time of the second clock CLK2 to the fifth time t5 which is the next rising edge time of the second clock CLK2 up to the high level state, and the signal out2 output from the second buffer 803 is the signal output from the first buffer 801 ( out1) and maintained until the seventh time point t7, which is the time of the next rising edge of the first clock CLK1, and has a high level state from the third time point t3 to the seventh time point t7, and the operation unit ( 805 is a scan signal having a high level state from the third time point t3 to the fourth time point t4 according to the logical product of the signal out2 output from the second buffer 803 and the first clock CLK1. Scan) is printed.

Also, referring to FIGS. 8 to 9B , when the second mode is selected by the mode selector 200 when the display panel 100 is an NMOS type, the first buffer 801 of the scan driving units SDU1, ..., SDUM ) is the start signal S and the first time t1 which is the rising edge of the second clock CLK2 and the third time t3 which is the next rising time of the second clock CLK2. up to the high level state, and the signal out2 output from the second buffer 803 is the signal output from the first buffer 801 out1) and maintained until the fourth time t4, which is the time of the next rising edge of the first clock CLK1, and has a high level state from the second time t2 to the fourth time t4, and the operation unit 805 ) is a scan signal Scan having a high level state from the second time point t2 to the third time point t3 according to the logical product of the signal out2 output from the second buffer 803 and the first clock CLK1 . ) is output.

When the display panel 100 is an NMOS type, a first start signal STV_O, a second start signal STV_E, a first odd clock CLKO 1 , a second odd clock CLKO 2 , and a first even clock CLKE 1) and outputting the scan signal Scan according to the high level state of the second even clock CLKE 2 and driving a plurality of subpixels of the display panel 100 according to the high level state of the scan signal Scan it could be

That is, when the display panel 100 is an NMOS type, the first start signal STV_O and the second start signal STV_E generated by the start signal generator 320 , and the first odd number generated by the clock generator 310 . Each of the scan signals output from the clock CLKO 1 , the second odd clock CLKO 2 , the first even clock CLKE 1 and the second even clock CLKE 2 , and the scan driving circuit units 330 , 330a and 330b is When the display panel 100 is of the PMOS type, the first start signal STV_O and the second start signal STV_E generated by the start signal generating unit 320 , and the first odd clock generated by the clock generating unit 310 ( CLKO 1), the second odd clock CLKO 2, the first even clock CLKE 1 and the second even clock CLKE 2, and the scan signals output from the scan driving circuit units 330, 330a, 330b are complementary to each other. it could be

Here, one and the other are complementary, which means that while one is in a high-level state, the other has a low-level state, and when one is synchronized at the rising edge time, the other is synchronized at the falling edge point, which This means that when one operates by the high-level state, the other operates by the low-level state.

The display device 10 capable of selectively driving progressive scan and interlaced scan according to embodiments of the present invention sequentially outputs a scan signal to a plurality of scan lines according to a user input, or either an odd row or an even row. First, a scan signal may be sequentially output to one scan line, and a scan signal may be sequentially outputted to the other one.

10, 11, and 12 are block diagrams illustrating the arrangement of a scan driving unit in a display device capable of selectively driving progressive scan and interlaced scan according to embodiments of the present invention.

Referring to FIG. 10 , a plurality of scan driving units of the scan driving circuit unit 330 may be disposed on one side of the display panel 100 according to an embodiment of the present invention.

Referring to FIG. 11 , in another embodiment of the present invention, the plurality of scan driving units of the scan driving circuit unit 330 may be equally disposed on both sides of the display panel 100 to enhance the output signal.

12 , in another embodiment of the present invention, an odd-numbered plurality of scan driving units 331 among a plurality of scan driving units of the scan driving circuit unit 330 are disposed on one side of the display panel 100 , , the even-numbered plurality of scan driving units 333 may be disposed on the other side of the display panel 100 .

Those of ordinary skill in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing the essential features of the technical idea. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

10: a display device capable of selectively driving progressive scan and interlaced scan
100: display panel
200: mode selection unit
300: drive unit
310: clock generator
320: start signal generator
330: scan driving circuit unit

Claims (8)

a plurality of subpixels arranged along a plurality of rows and columns, a plurality of scan lines connected to the subpixels along a row, and a plurality of source lines connected to the subpixels along a column display panel;
a mode selector configured to select one of a first mode and a second mode different from the first mode according to a user input; and
When the first mode is selected by the mode selector, scan signals are sequentially output to the plurality of scan lines, and when the second mode is selected by the mode selector, an odd-numbered scan line or a driving unit that sequentially outputs a scan signal first to any one of the scan lines of an even row and sequentially outputs a scan signal to the other one;
the driving unit
a clock generator for generating a first odd-numbered clock, a second odd-numbered clock, a first even-numbered clock, and a second even-numbered clock, each having a falling edge time point or a rising edge time point corresponding to the mode selected by the mode selector; a start signal generator for generating a first start signal and a second start signal that have a high level or a low level state for a set period of time but have different timings of a falling edge or a rising edge; and the first odd clock and the second odd number the first odd clock having a plurality of clock input terminals for receiving a clock, the first even clock, and the second even clock and a start signal input terminal for receiving the first start signal or the second start signal; A scan signal according to a high-level or low-level state of the first start signal or the second start signal at a time of a falling edge or a rising edge of the second odd clock, the first even clock, and the second even clock, respectively to include a scan driving circuit unit including a plurality of scan driving units each outputting
When the first mode is selected in the mode selection unit,
The clock generator has different falling edge timing or rising edge timing, but having the same duty ratio. remind generating the first odd clock, the second odd clock, the first even clock, and the second even clock,
The start signal generating unit causes the first start signal to have a high level or a low level state for a preset time, and the second start signal is the start time point at which the high level or low level state of the first start signal ends. to have a high-level or low-level state for a preset time,
The scan driving circuit unit sequentially scans a plurality of scan lines according to the first start signal, the second start signal, the first odd clock, the second odd clock, the first even clock, and the second even clock outputting a signal
A display device capable of selectively driving in progressive scan and interlaced scan. delete delete According to claim 1,
When the second mode is selected in the mode selection unit,
The clock generator has different falling edge timing or rising edge timing, but having the same duty ratio. remind generating a first odd-numbered clock and the second odd-numbered clock, and generating the first even-numbered clock identical to the second odd-numbered clock and the second even-numbered clock identical to the first odd-numbered clock;
The start signal generating unit causes the first start signal to have a high level or a low level state for a predetermined time, but the second start signal after a predetermined time when the high level or low level state of the first start signal ends The start signal is to have a high-level or low-level state for a preset time,
The scan driving circuit unit sequentially outputs a scan signal to the scan lines of odd rows according to the first start signal, the first odd clock, and the second odd clock, then the second start signal and the first even clock , sequentially outputting scan signals to the scan lines of even rows according to the second even clock
A display device capable of selectively driving in progressive scan and interlaced scan. According to claim 1,
The plurality of scan driving units are
receiving the first start signal as a start signal input terminal, receiving the first odd-numbered clock as a first clock input terminal, and receiving the second odd-numbered clock as a second clock input terminal to be connected to sub-pixels of the display panel a first scan driving unit for outputting a scan signal for driving a first scan line among a plurality of scan lines to a first scan line of the display panel;
receiving the second start signal as a start signal input terminal, receiving the first even clock as a first clock input terminal, and receiving the second even clock as a second clock input terminal to be connected to sub-pixels of the display panel a second scan driving unit for outputting a scan signal for driving to a second scan line among a plurality of scan lines to a second scan line of the display panel;
A scan signal output to a first odd scan line that is any one of scan lines in an odd row of the display panel is input through a start signal input terminal, and any one of the first odd clock and the second odd clock is applied to a first It receives a clock input and outputs the other one as a second clock input, and outputs a scan signal to a second odd line corresponding to the next odd row of the first odd scan line in row order among the scan lines in the odd row of the display panel a plurality of odd scan driving units; and
A scan signal output to a first even scan line that is any one of scan lines in an even row of the display panel is input to a start signal input terminal, and any one of the first even clock and the second even clock is input to a first clock input terminal a plurality of outputting scan signals to a second even line corresponding to the next even row of the first even scan line in the row order among the scan lines in the even row of the display panel by receiving the other one as input to the second clock input terminal an even scan driving unit comprising
A display device capable of selectively driving in progressive scan and interlaced scan. 6. The method of claim 5,
At least one of the first scan driving unit, the second scan driving unit, the odd scan driving unit, and the even scan driving unit,
a first buffer for outputting a start signal inputted from the start signal input terminal with a delay of a predetermined time according to a second clock inputted from the second clock input terminal; and a signal output from the first buffer inputted from the first clock input terminal Comprising a second buffer for outputting with a delay of a predetermined time according to the first clock to be used, and an operation unit for outputting a scan signal obtained by ORing or ORing a signal output from the second buffer and the first clock
A display device capable of selectively driving in progressive scan and interlaced scan. 7. The method of claim 6,
At least one of the first scan driving unit, the second scan driving unit, the odd scan driving unit, and the even scan driving unit,
a transistor for switching operation by receiving a third clock different from the first clock and the second clock from a gate, and one end is connected to a source of the transistor; a capacitor having the other end connected to the drain of the transistor, wherein the capacitor performs a charging/discharging operation according to a switching operation of the transistor and an output of the operation unit, and a scan signal is output from a node to which the drain of the transistor is connected
A display device capable of selectively driving in progressive scan and interlaced scan. 8. The method of claim 7,
wherein the clock generator further generates a clock signal having an opposite phase with respect to each of the first odd clock, the second odd clock, the first even clock, and the second even clock;
At least one of the first scan driving unit, the second scan driving unit, the odd scan driving unit, and the even scan driving unit generates a third clock inputted from a first clock input terminal with a third clock opposite in phase to the clock generator receiving input from
A display device capable of selectively driving in progressive scan and interlaced scan.

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