CN216388720U - Shift register unit and gate drive circuit - Google Patents

Abstract

A shift register cell and gate drive circuit, the shift register cell comprising: a pull-up circuit configured to supply an input signal terminal signal to the total pull-up node and pull up the node potential at the pull-down total; a control circuit connected to the total pull-up node and the pull-down node, configured to control a pull-down node potential; a cascade circuit connected to the global pull-up node, the pull-down node, and the cascade output terminal and the control clock signal terminal, configured to provide the control clock signal terminal signal to the cascade output terminal, and the pull-down cascade output terminal potential; the nth output circuit of the N output circuits is connected to the input signal terminal, the pull-down node, the nth output signal terminal and the nth pull-up node, is configured to input an input signal terminal signal to the nth pull-up node, supply an nth output clock signal terminal signal to the nth output signal terminal under potential control thereof, and pull down an nth output signal terminal potential under potential control of the pull-down node.

Description

Shift register unit and gate drive circuit

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a gate driving circuit.

Background

In the conventional display device, at least one gate driving circuit is generally included. When the display device displays images, the gate drive circuit can realize the scanning of each sub-pixel row of the display device, so that each sub-pixel in the sub-pixel row is charged according to the image data corresponding to the images to be displayed, and the image display is realized.

Disclosure of Invention

In one aspect, a shift register cell is provided that includes a pull-up circuit, a control circuit, a cascade circuit, and N output circuits. The pull-up circuit is connected to an input signal terminal of the shift register unit, a total pull-up node, and a pull-down node, and is configured to supply a signal of the input signal terminal to the total pull-up node and pull down a potential of the total pull-up node under control of a potential of the pull-down node. A control circuit is connected to the total pull-up node and the pull-down node, the control circuit being configured to control a potential of the pull-down node according to a potential of the total pull-up node. A cascade circuit is connected to the total pull-up node, the pull-down node, and a cascade output terminal and a control clock signal terminal of the shift register unit, the cascade circuit being configured to provide a signal of the control clock signal terminal to the cascade output terminal under control of a potential of the total pull-up node, and to pull down a potential of the cascade output terminal under control of a potential of the pull-down node. N output circuits are respectively connected to the input signal terminal, the pull-down node, and N output clock signal terminals, N pull-up nodes, and N output signal terminals of the shift register unit, wherein an nth output circuit is connected to the input signal terminal, the pull-down node, an nth output signal terminal, and an nth pull-up node, and is configured to input a signal of the input signal terminal to the nth pull-up node, supply a signal of the nth output clock signal terminal to the nth output signal terminal under control of a potential of the nth pull-up node, and pull down a potential of the nth output signal terminal under control of a potential of the pull-down node, wherein N is an integer greater than 1, N is an integer, and 1 ≦ N ≦ N.

In some embodiments, the nth output circuit comprises: an input sub-circuit, an output sub-circuit, and a pull-down sub-circuit. An input sub-circuit is connected to the input signal terminal and the nth pull-up node, and is configured to provide a signal of the input signal terminal to the nth pull-up node. An output sub-circuit is connected to the nth pull-up node, the nth output clock signal terminal, and the nth output signal terminal, and is configured to supply a signal of the nth output clock signal terminal to the nth output signal terminal under control of a potential of the nth pull-up node. The pull-down sub-circuit is connected to the pull-down node, and is configured to pull down potentials of the nth pull-up node and the nth output signal terminal under control of a potential of the pull-down node.

In some embodiments, the pull-down node comprises a first pull-down node and a second pull-down node, and the pull-down sub-circuit comprises a first pull-down sub-circuit and a second pull-down sub-circuit. The first pull-down sub-circuit is connected to the first pull-down node, and is configured to pull down a potential of at least one of the nth pull-up node and the nth output signal terminal under control of a potential of the first pull-down node. The second pull-down sub-circuit is connected to the second pull-down node, and is configured to pull down a potential of at least one of the nth pull-up node and the nth output signal terminal under control of a potential of the second pull-down node.

In some embodiments, the control circuit comprises: a first control sub-circuit and a second control sub-circuit. A first control sub-circuit is connected to the total pull-up node and the first pull-down node, and is configured to control a potential of the first pull-down node according to a potential of the total pull-up node. A second control sub-circuit connected to the total pull-up node and the second pull-down node, and configured to control a potential of the second pull-down node according to a potential of the total pull-up node.

In some embodiments, the nth output circuit further comprises: a reset sub-circuit connected to the nth pull-up node and the reset signal terminal and the reference signal terminal of the shift register unit, and configured to reset the nth pull-up node with a potential of the reference signal terminal under control of a signal of the reset signal terminal.

In some embodiments, the input sub-circuit is further connected to a power supply signal terminal, and is configured to supply a potential of the power supply signal terminal to the nth pull-up node under control of a signal of the input signal terminal.

In some embodiments, a first output clock signal terminal of the N output clock signal terminals is connected to the control clock signal terminal.

In some embodiments, the input sub-circuit comprises: a first transistor, a gate of the first transistor and a first pole of the first transistor being connected to the input signal terminal, a second pole of the first transistor being connected to the n-th pull-up node.

In some embodiments, the input sub-circuit comprises: a first transistor, a gate of which is connected to the input signal terminal, a first pole of which is connected to the power supply signal terminal, and a second pole of which is connected to the n-th pull-up node.

In some embodiments, the output sub-circuit includes a second transistor and a first capacitor. A gate of the second transistor is connected to the nth pull-up node, a first pole of the second transistor is connected to the nth output clock signal terminal, and a second pole of the second transistor is connected to the nth output signal terminal. A first terminal of the first capacitor is connected to the nth pull-up node, and a second terminal of the first capacitor is connected to the nth output signal terminal.

In some embodiments, the pull-down subcircuit includes: a third transistor and a fourth transistor. A gate of the third transistor is coupled to the pull-down node, a first pole of the third transistor is coupled to the first reference signal terminal of the shift register unit, and a second pole of the third transistor is coupled to the n-th pull-up node. A gate of the fourth transistor is connected to the pull-down node, a first pole of the fourth transistor is connected to the second reference signal terminal of the shift register unit, and a second pole of the fourth transistor is connected to the nth output signal terminal.

In some embodiments, the first pull-down sub-circuit includes a third transistor and a fourth transistor, a gate of the third transistor is connected to the first pull-down node, a first pole of the third transistor is connected to the first reference signal terminal of the shift register unit, a second pole of the third transistor is connected to the nth pull-up node, a gate of the fourth transistor is connected to the first pull-down node, a first pole of the fourth transistor is connected to the second reference signal terminal of the shift register unit, and a second pole of the fourth transistor is connected to the nth output signal terminal. The second pull-down sub-circuit includes a fifth transistor and a sixth transistor, a gate of the fifth transistor is connected to the second pull-down node, a first pole of the fifth transistor is connected to the first reference signal terminal, a second pole of the fifth transistor is connected to the n-th pull-up node, a gate of the sixth transistor is connected to the second pull-down node, a first pole of the sixth transistor is connected to the second reference signal terminal, and a second pole of the sixth transistor is connected to the n-th output signal terminal.

In some embodiments, the reset sub-circuit includes a seventh transistor, a gate of the seventh transistor is connected to the reset signal terminal, a first pole of the seventh transistor is connected to the reference signal terminal, and a second pole of the seventh transistor is connected to the n-th pull-up node.

In some embodiments, the control circuit comprises: an eighth transistor and a ninth transistor. And a gate of the eighth transistor and a first pole of the eighth transistor are connected to a power signal terminal of the shift register unit, and a second pole of the eighth transistor is connected to the pull-down node. A ninth transistor having a gate connected to the total pull-up node, a first pole connected to the reference signal terminal of the shift register unit, and a second pole connected to the pull-down node.

In some embodiments, the first control sub-circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor, a gate of the tenth transistor and a first pole of the tenth transistor are connected to the power supply signal terminal of the shift register unit, a second pole of the tenth transistor is connected to the gate of the eleventh transistor, a first pole of the eleventh transistor is connected to the power supply signal terminal, a second pole of the eleventh transistor is connected to the first pull-down node, a gate of the twelfth transistor is connected to the total pull-up node, a first pole of the twelfth transistor is connected to the reference signal terminal of the shift register unit, a second pole of the twelfth transistor is connected to the gate of the eleventh transistor, a gate of the thirteenth transistor is connected to the total pull-up node, a first pole of the thirteenth transistor is connected to the reference signal terminal, and a second pole of the thirteenth transistor is connected to the first pull-down node. The second control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor, a gate of the fourteenth transistor and a first pole of the fourteenth transistor are connected to the power supply signal terminal, a second pole of the fourteenth transistor is connected to the gate of the fifteenth transistor, a first pole of the fifteenth transistor is connected to the power supply signal terminal, a second pole of the fifteenth transistor is connected to the second pull-down node, a gate of the sixteenth transistor is connected to the total pull-up node, a first pole of the sixteenth transistor is connected to the reference signal terminal, a second pole of the sixteenth transistor is connected to the gate of the fifteenth transistor, a gate of the seventeenth transistor is connected to the total pull-up node, a first pole of the seventeenth transistor is connected to the reference signal terminal, a second pole of the seventeenth transistor is connected to the second pull-down node.

In some embodiments, the pull-up circuit comprises: an eighteenth transistor, a nineteenth transistor, and a twentieth transistor. A gate of the eighteenth transistor and a first pole of the eighteenth transistor are connected to the input signal terminal, and a second pole of the eighteenth transistor is connected to the total pull-up node. A nineteenth transistor having a gate connected to the pull-down node, a first pole connected to the reference signal terminal of the shift register unit, and a second pole connected to the total pull-up node. A twentieth transistor, a gate of which is connected to the reset signal terminal of the shift register unit, a first pole of which is connected to the reference signal terminal, and a second pole of which is connected to the total pull-up node.

In some embodiments, the pull-down node comprises a first pull-down node and a second pull-down node, and the pull-up circuit further comprises a twenty-first transistor. A gate of the nineteenth transistor is connected to the first pull-down node, a gate of the twenty-first transistor is connected to the second pull-down node, a first pole of the twenty-first transistor is connected to the reference signal terminal, and a second pole of the twenty-first transistor is connected to the total pull-up node.

In some embodiments, the cascade circuit comprises: a twenty-second transistor, a twenty-third transistor, and a second capacitor. The gate of the twenty-second transistor is connected to the total pull-up node, the first pole of the twenty-second transistor is connected to the control clock signal terminal, and the second pole of the twenty-second transistor is connected to the cascade output terminal. A twenty-third transistor, a gate of the twenty-third transistor being connected to the pull-down node, a first pole of the twenty-third transistor being connected to the reference signal terminal of the shift register unit, and a second pole of the twenty-third transistor being connected to the cascade output terminal. A second capacitor, a first end of the second capacitor is connected to the gate of the twenty-second transistor, and a second end of the second capacitor is connected to the cascade output terminal.

In some embodiments, the pull-down node comprises a first pull-down node and a second pull-down node, and the cascode circuit further comprises a twenty-fourth transistor. A gate of the twenty-fourth transistor is connected to the first pull-down node, a gate of the twenty-fourth transistor is connected to the second pull-down node, a first pole of the twenty-fourth transistor is connected to the reference signal terminal, and a second pole of the twenty-fourth transistor is connected to the cascade output terminal.

In some embodiments, the shift register cell further comprises a global reset circuit. The total reset circuit comprises a twenty-fifth transistor, wherein the grid electrode of the twenty-fifth transistor is connected to the total reset end of the shift register unit, the first pole of the twenty-fifth transistor is connected to the reference signal end of the shift register unit, and the second pole of the twenty-fifth transistor is connected to the total pull-up node.

In some embodiments, N ═ 4 or 2.

In another aspect, a gate driving circuit is provided, which includes M cascaded shift register units, and the shift register unit is the shift register unit as described above. The input signal end of the mth stage shift register unit is connected with the cascade output end of the (M-1) th stage shift register unit, the reset signal end of the mth stage shift register unit is connected with the cascade output end of the (M +2) th stage shift register unit, wherein M is an integer larger than 1, M is an integer and is more than 1 and less than M-1. The M cascaded shift register units are connected to K clock signal lines, wherein K is an even number greater than or equal to 2N.

In some embodiments, N is 4, and K is 12, the M cascaded shift register units are divided into a plurality of groups, each group includes 3 cascaded first, second, and third shift register units, where N output clock signal terminals of the first shift register unit are connected to the first to fourth clock signal lines in a one-to-one correspondence, N output clock signal terminals of the second shift register unit are connected to the fifth to eighth clock signal lines in a one-to-one correspondence, and N output clock signal terminals of the third shift register unit are connected to the ninth to twelfth clock signal lines in a one-to-one correspondence.

In some embodiments, N is 4, and K is 8, the M cascaded shift register units are divided into a plurality of groups, each group includes 2 cascaded first and second shift register units, where N output clock signal terminals of the first shift register unit are connected to the first to fourth clock signal lines in a one-to-one correspondence, and N output clock signal terminals of the second shift register unit are connected to the fifth to eighth clock signal lines in a one-to-one correspondence.

In some embodiments, a first output clock signal terminal of the N output clock signal terminals of each shift register cell is connected to a control clock signal terminal of the shift register cell.

In some embodiments, N is 2 and K is 6, and the K clock signal lines include a first control clock signal line, a second control clock signal line, a first output clock signal line, a second output clock signal line, a third output clock signal line, and a fourth output clock signal line. The shift register units of the M-level cascade are divided into a plurality of groups, each group comprises a first shift register unit and a second shift register unit of 2-level cascade, N output clock signal ends of the first shift register unit are connected with a first output clock signal line and a second output clock signal line in a one-to-one correspondence mode, a control clock signal end of the first shift register unit is connected with a first control clock signal line, N output clock signal ends of the second shift register unit are connected with a third clock signal line and a fourth clock signal line in a one-to-one correspondence mode, and a control clock signal end of the second shift register unit is connected with a second control clock signal line.

Drawings

FIG. 1 is a schematic block diagram of a shift register cell according to some embodiments;

FIG. 2 is a circuit diagram of a shift register cell according to some embodiments;

FIG. 3 is a circuit diagram of another shift register cell according to some embodiments;

FIG. 4 is a circuit diagram of yet another shift register cell according to some embodiments;

FIG. 5 is a circuit diagram of yet another shift register cell according to some embodiments;

FIG. 6 is a schematic diagram of a gate driver circuit according to some embodiments;

FIG. 7 is a schematic diagram of another gate driver circuit according to some embodiments;

FIG. 8 is a schematic diagram of yet another gate driver circuit according to some embodiments;

FIG. 9 is a signal timing diagram of a method of driving a shift register cell according to some embodiments;

fig. 10 is a signal timing diagram of a driving method of a gate driving circuit in a first mode according to some embodiments;

FIG. 11 is a signal timing diagram of a driving method of a gate driving circuit in a second mode according to some embodiments;

fig. 12 is a signal timing diagram of another driving method of a gate driving circuit in a first mode according to some embodiments;

fig. 13 is a signal timing diagram of another driving method of a gate driving circuit in a second mode according to some embodiments; and

fig. 14 is a signal timing diagram of a driving method of a gate driving circuit in a first mode and a second mode according to some embodiments.

Detailed Description

While the present disclosure will be fully described with reference to the accompanying drawings, which contain preferred embodiments of the disclosure, it should be understood before this description that one of ordinary skill in the art can modify the disclosure described herein while obtaining the technical effects of the present disclosure. Therefore, it should be understood that the foregoing description is a broad disclosure directed to persons of ordinary skill in the art, and that there is no intent to limit the exemplary embodiments described in this disclosure.

Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in schematic form in order to simplify the drawing.

Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given their ordinary meanings as understood by those skilled in the art. The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another.

It should be noted that, although the terms "first", "second", etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one element, component, element, region, layer or section from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion discussed below could be termed a second component, a second member, a second element, a second region, a second layer, and/or a second portion without departing from the teachings of the present disclosure.

In the description of the embodiments of the present disclosure, the term "connected", "connected" or "electrically connected" may mean that two components are directly connected, or may mean that two components are connected via one or more other components.

In the related art, a display device generally includes a display panel and at least one gate driving circuit electrically connected to the display panel. Illustratively, the gate driving circuit may be fabricated separately from the display panel, and the two may be connected together by, for example, a flexible printed circuit board. As another example, in the process of manufacturing the display panel, the gate driving circuit may be directly formed On the substrate of the display panel, for example, in the peripheral area around the display area of the display panel, which is also called a goa (gate On array) technology. In the case where the display device employs the GOA technology, each sub-pixel in a sub-pixel row in the display panel may be driven by a corresponding one of the shift register units in the gate driving circuit.

However, in the case that the resolution of the display device is high and the refresh rate of the display device is high (for example, 8K resolution), the number of shift register units required by the display device is large, which results in a large size of the frame of the display device and affects the aesthetic quality of the product.

Referring to fig. 1, some embodiments of the present disclosure provide a shift register cell 100. The shift register cell 100 includes a pull-up circuit 10, a control circuit 20, a cascade circuit 30, and N output circuits 40.

The pull-up circuit 10 is connected to the INPUT signal terminal INPUT, the total pull-up node PU, and the pull-down node PD of the shift register unit 100, and the pull-up circuit 10 is configured to supply a signal of the INPUT signal terminal INPUT to the total pull-up node PU and pull down a potential of the total pull-up node PU under control of a potential of the pull-down node PD.

The control circuit 20 is connected to the total pull-up node PU and the pull-down node PD, and the control circuit 20 is configured to control the potential of the pull-down node PD according to the potential of the total pull-up node PU.

The cascade circuit 30 is connected to the overall pull-up node PU, the pull-down node PD, and the cascade output terminal OUT _ C and the control clock signal terminal CLK _ C of the shift register unit 100, and the cascade circuit 30 is configured to supply a signal of the control clock signal terminal CLK _ C to the cascade output terminal OUT _ C under control of a potential of the overall pull-up node PU, and pull down a potential of the cascade output terminal OUT _ C under control of a potential of the pull-down node PD.

The N output circuits 40 are respectively connected to the INPUT signal terminal INPUT, the pull-down node PD, and N output clock signal terminals (e.g., CLK _1 to CLK _ N in fig. 1), N pull-up nodes (e.g., PU _1 to PU _ N in fig. 1), and N output signal terminals (e.g., OUT _1 to OUT _ N in fig. 1) of the shift register unit 100. The nth output circuit 40 is connected to the INPUT signal terminal INPUT, the pull-down node PD, the nth output signal terminal OUT _ n, and the nth pull-up node PU _ n, and is configured to INPUT a signal of the INPUT signal terminal INPUT to the nth pull-up node PU _ n, supply a signal of the nth output clock signal terminal CLK _ n to the nth output signal terminal OUT _ n under control of a potential of the nth pull-up node PU _ n, and pull down a potential of the nth output signal terminal OUT _ n under control of a potential of the pull-down node PD. Where N is an integer greater than 1, N is an integer and 1. ltoreq. n.ltoreq.N. In some embodiments, 2 ≦ N ≦ 8, for example, N may be 2, 3, 4, 5, or 6.

The shift register unit has a structure that the N output circuits share one control circuit, so that the shift register unit can replace a plurality of traditional shift register units to independently generate a plurality of output signals, and has a simpler circuit structure compared with a combination of a plurality of traditional shift register units. For example, in the shift register unit described above, N output circuits share one control circuit, that is, are controlled by the potential of the same pull-down node PD. Each output circuit includes a respective pull-up node capable of producing an output independently of the other. Compared with the related art, under the condition of driving the same number of sub-pixel rows, the shift register unit of the embodiment of the disclosure can reduce the number of control circuits required to be arranged, has a simpler circuit structure, and is beneficial to reducing the frame size of the display device.

Fig. 2 is a circuit diagram of a shift register cell 200 according to some embodiments.

As shown in fig. 2, the shift register unit 200 includes a pull-up circuit 10, a control circuit 20, a cascade circuit 30, and N output circuits. N may be 2, that is, the N output circuits include a first output circuit 401 and a second output circuit 402 (hereinafter collectively referred to as an output circuit 40). The first output circuit 401 and the second output circuit 402 share one control circuit 20. In this case, the shift register unit 200 may include first and second output clock signal terminals CLK _1 and CLK _2, first and second output signal terminals OUT _1 and OUT _2, and first and second pull-up nodes PU _1 and PU _ 2.

Referring to fig. 2, each output circuit 40 includes an input sub-circuit 401, an output sub-circuit 402, and a pull-down sub-circuit 403. The configuration of the output sub-circuit will be described below by taking as an example any one of the output sub-circuits 40 (i.e., the nth output sub-circuit 40, n being 1 or 2).

The INPUT sub circuit 401 is connected to the INPUT signal terminal INPUT and the nth pull-up node PU _ n, and is configured to provide a signal of the INPUT signal terminal INPUT to the nth pull-up node PU _ n.

The output sub-circuit 402 is connected to the nth pull-up node PU _ n, the nth output clock signal terminal CLK _ n, and the nth output signal terminal OUT _ n, and is configured to supply a signal of the nth output clock signal terminal CLK _ n to the nth output signal terminal OUT _ n under control of a potential of the nth pull-up node PU _ n.

The pull-down sub-circuit 403 is connected to the pull-down node PD, and is configured to pull down the potentials of the nth pull-up node PU _ n and the nth output signal terminal OUT _ n under the control of the potential of the pull-down node PD.

As shown in fig. 2, in the first output circuit 40_1, the input sub-circuit 401 may include a first transistor M1. A gate of the first transistor M1 and a first pole of the first transistor M1 are connected to the INPUT signal terminal INPUT, and a second pole of the first transistor M1 is connected to the first pull-up node PU _ 1.

In the first output circuit 401, the output sub-circuit 402 may include a second transistor M2 and a first capacitor C1. The gate of the second transistor M2 is connected to the first pull-up node PU _1, the first pole of the second transistor M2 is connected to the first output clock signal terminal CLK _1, and the second pole of the second transistor M2 is connected to the first output signal terminal OUT _ 1. A first terminal of the first capacitor C1 is connected to the first pull-up node PU _1, and a second terminal of the first capacitor C1 is connected to the first output signal terminal OUT _ 1.

In the first output circuit 40_1, the pull-down sub-circuit 403 may include a third transistor M3 and a fourth transistor M4. A gate of the third transistor M3 is coupled to the pull-down node PD, a first pole of the third transistor M3 is coupled to a reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit 200, and a second pole of the third transistor M3 is coupled to the first pull-up node PU _ 1. A gate of the fourth transistor M4 is connected to the pull-down node PD, a first pole of the fourth transistor M4 is connected to a reference signal terminal (e.g., a second reference signal terminal VGL) of the shift register unit 200, and a second pole of the fourth transistor M4 is connected to the first output signal terminal OUT _ 1.

The second output circuit 40_2 has a similar structure to the second output circuit 40_1 except that it connects the second division pull-up node PU _2, the second output clock signal terminal CLK _2, and the second output signal terminal OUT _ 2. As shown in fig. 2, in the second output circuit 402, the gate of the first transistor M1 and the first pole of the first transistor M1 are connected to the INPUT signal terminal INPUT, and the second pole of the first transistor M1 is connected to the second divided pull-up node PU _ 2. The gate of the second transistor M2 is connected to the second divided pull-up node PU _2, the first pole of the second transistor M2 is connected to the second output clock signal terminal CLK _2, and the second pole of the second transistor M2 is connected to the second output signal terminal OUT _ 2. The first terminal of the first capacitor C1 is connected to the second pull-up node PU _2, and the second terminal of the first capacitor C1 is connected to the second output signal terminal OUT _ 2. A gate of the third transistor M3 is coupled to the pull-down node PD, a first pole of the third transistor M3 is coupled to the first reference signal terminal LVGL, and a second pole of the third transistor M3 is coupled to the second sub-pull-up node PU _ 2. A gate of the fourth transistor M4 is connected to the pull-down node PD, a first pole of the fourth transistor M4 is connected to the second reference signal terminal VGL, and a second pole of the fourth transistor M4 is connected to the second output signal terminal OUT _ 2.

The control circuit 20 may include an eighth transistor M8 and a ninth transistor M9. A gate and a first pole of the eighth transistor M8 are connected to the power signal terminal VDD of the shift register unit 200, and a second pole of the eighth transistor M8 is connected to the pull-down node PD. A gate of the ninth transistor M9 is connected to the total pull-up node PU, a first pole of the ninth transistor M9 is connected to a reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit 200, and a second pole of the ninth transistor M9 is connected to the pull-down node PD.

The pull-up circuit 10 includes an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20. A gate of the eighteenth transistor M18 and a first pole thereof are connected to the INPUT signal terminal INPUT, and a second pole of the eighteenth transistor M18 is connected to the total pull-up node PU. A gate of the nineteenth transistor M19 is connected to the pull-down node, a first pole of the nineteenth transistor M19 is connected to a reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit 200, and a second pole of the nineteenth transistor M19 is connected to the total pull-up node PU. A gate of the twentieth transistor M20 is connected to the reset signal terminal RST _ PU of the shift register unit, a first pole of the twentieth transistor M20 is connected to a reference signal terminal (e.g., the first reference signal terminal LVGL), and a second pole of the twentieth transistor M20 is connected to the total pull-up node PU.

The cascode circuit 30 may include a twentieth transistor M22, a twenty-third transistor M23, and a second capacitor C2. The gate of the twentieth transistor M22 is connected to the total pull-up node PU, the first pole of the twentieth transistor M22 is connected to the control clock signal terminal CLK _ C, and the second pole of the twentieth transistor M22 is connected to the cascade output terminal OUT _ C. A gate of the twenty-third transistor M23 is connected to the pull-down node PD, a first pole of the twenty-third transistor M23 is connected to a reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit 100, and a second pole of the twenty-third transistor M23 is connected to the cascade output terminal OUT _ C. A first terminal of the second capacitor C2 is connected to the gate of the twenty-second transistor M22, and a second terminal of the second capacitor C2 is connected to the cascade output terminal OUT _ C.

Fig. 3 is a circuit diagram of another shift register cell 300 according to some embodiments. The circuit of fig. 3 is similar to that of fig. 2, except at least that the pull-down nodes of the shift register unit include a first pull-down node PD _1 and a second pull-down node PD _ 2. For the sake of simplifying the description, the following description will mainly explain the difference in detail.

Referring to fig. 3, the pull-down sub-circuit of each of the output circuits 40_1 and 40_2 may include a first pull-down sub-circuit and a second pull-down sub-circuit. In fig. 3, the first pull-down sub-circuit includes a third transistor M3 and a fourth transistor M4. The second pull-down sub-circuit includes a fifth transistor M5 and a sixth transistor M6. The following describes the configuration of the output circuit by taking the first output circuit 40_1 as an example.

In the output circuit 40_1, a first pull-down sub-circuit is connected to the first pull-down node PD _1, and is configured to pull down the potentials of the first division pull-up node PU _1 and the first output signal terminal OUT _1 under the control of the potential of the first pull-down node PD _ 1. For example, the first pull-down sub-circuit includes a third transistor M3 and a fourth transistor M4. A gate of the third transistor M3 is coupled to the first pull-down node PD _1, a first pole of the third transistor M3 is coupled to a first reference signal terminal LVGL, and a second pole of the third transistor M3 is coupled to the first pull-up node PU _ 1. A gate of the fourth transistor M4 is connected to the first pull-down node PD _1, a first pole of the fourth transistor M4 is connected to a second reference signal terminal VGL, and a second pole of the fourth transistor M4 is connected to the first output signal terminal OUT _ 1.

In the output circuit 401, the second pull-down sub-circuit is connected to the second pull-down node PD _2, and is configured to pull down the potentials of the second division pull-up node PU _2 and the second output signal terminal OUT _2 under the control of the potential of the second pull-down node PD _ 2. For example, the second pull-down sub-circuit includes a fifth transistor M5 and a sixth transistor M6. A gate of the fifth transistor M5 is connected to the second pull-down node PD _2, a first pole of the fifth transistor M5 is connected to the first reference signal terminal LVGL, and a second pole of the fifth transistor M5 is connected to the first pull-up node PU _ 1. A gate of the sixth transistor M6 is connected to the second pull-down node PD _2, a first pole of the sixth transistor M6 is connected to the second reference signal terminal VGL, and a second pole of the sixth transistor M6 is connected to the first output signal terminal OUT _ 1.

The pull-down sub-circuit of the second output circuit 40_2 has a similar structure to the first output circuit 40_1, and is not described herein again.

In some embodiments, referring to fig. 3, each output circuit 40_1 and 40_2 may further include a reset sub-circuit. The reset sub-circuit may include a seventh transistor M7. Taking the first output circuit 40_1 as an example, the gate of the seventh transistor M7 is connected to the reset signal terminal RST _ PU, the first pole of the seventh transistor M7 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and the second pole of the seventh transistor M7 is connected to the first pull-up node PU _ 1. The reset sub-circuit of the second output circuit 40_2 has a similar structure and will not be described again.

In fig. 3, the control circuit 20 may include a first control sub-circuit 201 and a second control sub-circuit 202. The first control sub-circuit 201 is connected to the total pull-up node PU and the first pull-down node PD _1, and is configured to control a potential of the first pull-down node PD _1 according to a potential of the total pull-up node PU. The second control sub-circuit 202 is connected to the total pull-up node PU and the second pull-down node PD _2, and is configured to control the potential PD _2 of the second pull-down node according to the potential of the total pull-up node PU.

The first control sub-circuit 201 may include a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13. The gate and the first pole of the tenth transistor M10 are connected to a power signal terminal (e.g., a power signal terminal VDDO) of the shift register unit 300, the second pole of the tenth transistor M10 is connected to the gate of the eleventh transistor M11, and the first pole of the eleventh transistor M11 is connected to the power signal terminal (e.g., a power signal terminal VDDO). A second pole of the eleventh transistor M11 is connected to the first pull-down node PD _ 1. A gate of the twelfth transistor M12 is connected to the total pull-up node PU, a first pole of the twelfth transistor M12 is connected to a reference signal terminal (e.g., the first reference signal terminal LVGL) of the shift register unit 300, and a second pole of the twelfth transistor M12 is connected to a gate of the eleventh transistor M11. A gate of the thirteenth transistor M13 is connected to the total pull-up node PU, a first pole of the thirteenth transistor M13 is connected to a reference signal terminal (e.g., the first reference signal terminal LVGL), and a second pole of the thirteenth transistor M13 is connected to the first pull-down node PD _ 1.

The second control sub-circuit 202 may include a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17. A gate of the fourteenth transistor M14 and a first pole of the fourteenth transistor M14 are connected to a power signal terminal (e.g., a power signal terminal VDDE), and a second pole of the fourteenth transistor M14 is connected to a gate of the fifteenth transistor M15. A first pole of the fifteenth transistor M15 is connected to a power signal terminal (e.g., a power signal terminal VDDE), and a second pole of the fifteenth transistor M15 is connected to the second pull-down node PD _ 2. A gate of the sixteenth transistor M16 is connected to the total pull-up node PU, a first pole of the sixteenth transistor M16 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and a second pole of the sixteenth transistor M16 is connected to the gate of the fifteenth transistor M15. The gate of the seventeenth transistor M17 is connected to the total pull-up node, the first pole of the seventeenth transistor M17 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and the second pole of the seventeenth transistor M17 is connected to the second pull-down node PD _ 2.

By providing the first control sub-circuit 201 and the second control sub-circuit 202 to control the signal output of the N output circuits 40, the N output circuits 40 can be divided into two independent portions, one of which is controlled by the first control sub-circuit 201 to output a signal and the other of which is controlled by the first control sub-circuit 201 to output a signal. Therefore, the alternative on and off of the gates of the sub-pixels in the corresponding two sub-pixel rows can be realized.

In fig. 3, the cascode circuit 30 may include a twenty-fourth transistor M24 in addition to the twenty-second transistor M22, the twenty-third transistor M23, and the second capacitor C2. The above description of the twentieth transistor M22 and the twenty-third transistor M23 also applies to fig. 3. In fig. 3, a gate of a twenty-fourth transistor M24 is connected to the first pull-down node PD _1, a gate of the twenty-fourth transistor M24 is connected to the second pull-down node PD _2, a first pole of the twenty-fourth transistor M24 is connected to the reference signal terminal (e.g., the first reference signal terminal LVGL), and a second pole of the twenty-fourth transistor M24 is connected to the cascade output terminal OUT _ C.

In fig. 3, the pull-up circuit 10 includes a twenty-first transistor M21 in addition to an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20. Unlike fig. 2, a gate of the nineteenth transistor M19 is connected to the first pull-down node PD _1, a gate of the twentieth transistor M20 is connected to the reset signal terminal RST _ PU of the shift register unit 300, a first pole of the twentieth transistor M20 is connected to a reference signal terminal (e.g., the first reference signal terminal LVGL), and a second pole of the twentieth transistor M20 is connected to the total pull-up node PU.

In some embodiments, referring to fig. 3, the shift register cell 300 further includes an overall reset circuit 50. The overall reset circuit 50 may include a twenty-fifth transistor M25. A gate of the twenty-fifth transistor M25 is connected to the global reset terminal RST _ T of the shift register unit 300, a first pole of the twenty-fifth transistor M25 is connected to a reference signal terminal (e.g., the first reference signal terminal LVGL), and a second pole of the twenty-fifth transistor M25 is connected to the global pull-up node PU.

Fig. 4 is a circuit diagram of yet another shift register cell 400 according to some embodiments. Shift register 400 of FIG. 4 is similar to shift register 200 of FIG. 2, except at least for the manner in which the input subcircuits of each output circuit are connected. For the sake of brevity, the following description will mainly describe the differences in detail.

Referring to fig. 4, the INPUT sub-circuit 401 of the first INPUT sub-circuit 401 is connected to the power supply signal terminal VGH in addition to the INPUT signal terminal INPUT. The INPUT sub-circuit 401 may provide the signal of the power supply signal terminal VGH to the first pull-up node PU _1 based on the potential of the signal of the INPUT signal terminal INPUT. For example, in the INPUT sub-circuit 401, the gate of the first transistor M1 is connected to the INPUT signal terminal INPUT, the first pole is connected to the power supply signal terminal VGH, and the second pole is connected to the first pull-up node PU _ 1. The input sub-circuit 401 of the second input sub-circuit 402 is similar to the first input sub-circuit 40_1 and is not described again here.

In some embodiments, the eighteenth transistor M18 in the input circuit 10 may also be connected in a similar manner. As shown in fig. 14, the gate of the eighteenth transistor M18 is connected to the INPUT signal terminal INPUT, the first pole of the eighteenth transistor M18 is connected to the power supply signal terminal VGH, and the second pole of the eighteenth transistor M18 is connected to the total pull-up node PU.

The signal of the power signal end VGH is stable and cannot be interfered, so that the working stability of the shift register unit can be improved.

FIG. 5 is a circuit diagram of yet another shift register cell according to some embodiments. The shift register cell 500 of fig. 5 is similar to the shift register cell 200 of fig. 2, except at least for the number of output circuits and the manner of connection of the clock signal terminals. For convenience of description, the following description will mainly explain the difference in detail.

In the shift register unit 500, N is 4, that is, 4 output circuits, 4 output clock signal terminals, 4 output signal terminals, and 4 pull-up nodes are included. As shown in fig. 5, the shift register unit 500 includes a first output circuit 40_1, a second output circuit 40_2, a third output circuit 40_3, and a fourth output circuit 404. The shift register unit 500 further includes first to fourth output clock signal terminals CLK _1 to CLK _4, first to fourth output signal terminals OUT _1 to OUT _4, and first to fourth output pull-up nodes PU _1 to PU _ 2. Each output circuit is connected to a respective output clock signal terminal, a respective output signal terminal, and a respective pull-up node. For example, the first output circuit 40_1 is connected to the first output clock signal terminal CLK _1, the first output signal terminal OUT _1 and the first output pull-up node PU _1, the second output circuit 40_2 is connected to the second output clock signal terminal CLK _2, the second output signal terminal OUT _2 and the first output pull-up node PU _3, and so on. As shown in fig. 5, the respective structures and connection manners of the first output circuit 40_1, the second output circuit 40_2, the third output circuit 40_3, and the fourth output circuit 40_4 are similar to those of the output circuit described above with reference to fig. 2, and are not repeated here.

In fig. 5, the first output clock signal terminal CLK _1 is connected to the control clock signal terminal CLK _ C as one signal terminal. In this way, wiring can be reduced, further simplifying the circuit configuration.

Although it is illustrated in fig. 5 that the first output clock signal terminal CLK _1 and the control clock signal terminal CLK _ C may be connected to each other, embodiments of the present disclosure are not limited thereto. In the shift register unit of any of the embodiments described above, one of the N output clock signal terminals may be connected to the control clock signal terminal CLK _ C.

Although the embodiment of fig. 5 increases the number of output circuits on the basis of the shift register unit of fig. 2, embodiments of the present disclosure are not limited thereto. The number of output circuits of the shift register unit of any of the above embodiments can be set as needed. For example, the number of output circuits of the shift register units 300 and 400 described above may be set to 3, 4, or more.

Some implementations of the present disclosure provide a gate driving circuit, which will be described below with reference to fig. 6 and 7.

Fig. 6 is a schematic diagram of a gate driving circuit according to some embodiments.

Referring to fig. 6, the gate driving circuit includes M cascaded shift register cells GOA1, GOA2, …, GOAM, each of which can be implemented by the shift register cell of any of the embodiments described above. For ease of description, in fig. 6, M ═ 3 is illustrated, i.e., GOA1, GOA2, and GOA 3. As shown in fig. 6, the INPUT signal terminal INPUT of the mth stage shift register unit GOAm is connected to the cascade output terminal OUT _ C of the (M-1) th stage shift register unit GOA, and the reset signal terminal RST _ PU of the mth stage shift register unit GOAm is connected to the cascade output terminal OUT _ C of the (M +2) th stage shift register unit GOA, where M is an integer greater than 1, M is an integer, and 1 < M-1. As shown in fig. 6, the M cascaded shift register units GOA1, GOA2, …, GOAM are connected to K clock signal lines, where K is an even number greater than or equal to 2N.

Referring to fig. 6, N is 4, and K is 12, that is, the gate driving circuit is connected to 12 clock signal lines, and each shift register unit in the gate driving circuit has 4 output circuits, and may be implemented by the shift register unit described above with reference to fig. 5, for example. The M-level cascaded shift register units GOA1, GOA2 and GOAM … are divided into multiple groups, and each group comprises 3 levels of cascaded first shift register units, second shift register units and third shift register units. For example, in fig. 6, the first group includes first to third stage shift register units GOA1, GOA2, and GOA3 as first to third shift register units in the first group, respectively, the second group includes fourth to sixth stage shift register units GOA4, GOA5, and GOA6 as first to third shift register units in the second group, respectively, and so on.

Taking the first group as an example, the 4 output clock signal terminals CLK _1 to CLK _4 of the first shift register unit GOA1 in the group are connected to the first clock signal line CLK1 to the fourth clock signal line CLK4 in a one-to-one correspondence, the 4 output clock signal terminals CLK _1 to CLK _4 of the second shift register unit GOA2 are connected to the fifth clock signal line CLK5 to the eighth clock signal line CLK8 in a one-to-one correspondence, and the 4 output clock signal terminals CLK _1 to CLK _4 of the third shift register unit GOA3 are connected to the ninth clock signal line CLK9 to the twelfth clock signal line CLK12 in a one-to-one correspondence.

Similarly, the 4 output clock signal terminals CLK _1 to CLK _4 of the first shift register unit GOA4 in the second group are connected to the first to fourth clock signal lines CLK1 to CLK4 in a one-to-one correspondence, the 4 output clock signal terminals CLK _1 to CLK _4 of the second shift register unit GOA5 are connected to the fifth to eighth clock signal lines CLK5 to CLK8 in a one-to-one correspondence, the 4 output clock signal terminals CLK _1 to CLK _4 of the third shift register unit GOA6 are connected to the ninth to twelfth clock signal lines CLK9 to CLK12 in a one-to-one correspondence, and so on.

In fig. 6, INPUT signal terminal INPUT of first stage shift register GOA1 is connected to start signal line STV for receiving start signal.

In operation, the first stage shift register unit GOA1 outputs 4 output signals G1 through G4 at 4 output signal terminals OUT _1 through OUT _4, respectively, based on signals on the start signal line STV under the control of clock signals on the clock signal lines CLK1 through CLK4, and outputs a cascade signal at the cascade output terminal OUT _ C to the INPUT signal terminal INPUT of the second stage shift register unit GOA 2. The second stage shift register unit GOA2 outputs 4 output signals G5 through G8 at 4 output signal terminals OUT _1 through OUT _4, respectively, based on a cascade signal at the INPUT signal terminal INPUT under the control of the clock signal lines CLK5 through CLK8, and so on.

Fig. 7 is a schematic diagram of another gate driver circuit according to some embodiments. The gate driving circuit of fig. 7 is similar to that of fig. 6, except that at least K-8, i.e., the gate driving circuit is connected to 8 clock signal lines.

As shown in fig. 7, the gate driving circuit includes M cascaded shift register units GOA1, GOA2, …, and GOAM. For convenience of description, fig. 7 illustrates M ═ 3, i.e., GOA1, GOA2, and GOA 3. Each shift register cell may be implemented by a shift register cell having 4 output circuits (i.e., N-4) in the above-described embodiment, for example, by the shift register cell described above with reference to fig. 5.

Similar to fig. 6, the INPUT signal terminal INPUT of the mth stage shift register unit GOAm is connected to the cascade output terminal OUT _ C of the (M-1) th stage shift register unit GOA, and the reset signal terminal RST _ PU of the mth stage shift register unit GOAm is connected to the cascade output terminal OUT _ C of the (M +2) th stage shift register unit GOA, where M is an integer greater than 1, M is an integer, and 1 < M-1.

As shown in fig. 7, the M-stage cascade of shift register cells GOA1, GOA2, …, GOAM are connected to 8 clock signal lines CLK1 to CLK 8. The M-stage cascaded shift register units GOA1, GOA2, …, and GOAM are divided into multiple groups, each group including 2-stage cascaded first and second shift register units. For example, in fig. 7, the first group includes first and second stage shift register cells GOA1, GOA2 as first and second shift register cells in the first group, respectively, the second group includes third and sixth stage shift register cells GOA3, GOA4 as first and second shift register cells in the second group, respectively, and so on. Taking the first group as an example, the 4 output clock signal terminals CLK _1 to CLK _4 of the first shift register unit GOA1 in the group are connected to the first clock signal line CLK1 to the fourth clock signal line CLK4 in a one-to-one correspondence, and the 4 output clock signal terminals CLK _1 to CLK _4 of the second shift register unit GOA2 are connected to the fifth clock signal line CLK5 to the eighth clock signal line CLK8 in a one-to-one correspondence. The shift register units GOA3 and GOA4 in the second group connect the clock signal lines CLK1 to CLK8 in a similar manner, and are not described in detail here.

In the gate driving circuits of fig. 6 and 7, a first output clock signal terminal CLK _1 of the N output clock signal terminals CLK _1 to CLK _ N of each shift register unit is connected to a control clock signal terminal of the shift register unit CLK _ C, so that the first output circuit and the cascade circuit generate outputs based on the same clock signal, thereby outputting signals having the same waveform at the first output signal terminal OUT _1 and the cascade output terminal OUT _ C.

FIG. 8 is a schematic diagram of yet another gate driver circuit according to some embodiments. The gate driving circuit of fig. 8 is similar to that of fig. 7, except that at least N is 2 and K is 6, that is, the gate driving circuit is connected to 6 clock signal lines, and each shift register unit of the gate driving circuit can be implemented by a shift register unit having 2 output circuits in the above-described embodiment.

Referring to fig. 8, the gate driving circuit includes M stages of cascaded shift register cells GOA1, GOA2, …, GOAM. For convenience of description, in fig. 8, M ═ 3 is illustrated, i.e., GOA1, GOA2, and GOA 3. Each shift register cell may be implemented by a shift register cell having 2 output circuits in the above-described embodiments, for example, by any of the shift register cells described above with reference to fig. 2 to 4.

Similar to fig. 7, the INPUT signal terminal INPUT of the mth stage shift register unit GOAm is connected to the cascade output terminal OUT _ C of the (M-1) th stage shift register unit GOA, and the reset signal terminal RST _ PU of the mth stage shift register unit GOAm is connected to the cascade output terminal OUT _ C of the (M +2) th stage shift register unit GOA, where M is an integer greater than 1, M is an integer, and 1 < M-1.

Referring to fig. 8, the 6 clock signal lines include a first control clock signal line CLKC1, a second control clock signal line CLKC2, a first output clock signal line CLK1, a second output clock signal line CLK2, a third output clock signal line CLK3, and a fourth output clock signal line CLK 4.

The M-level cascaded shift register units GOA1, GOA2, GOAM … are divided into multiple groups, and each group comprises 2 levels of cascaded first shift register units and second shift register units. For example, in fig. 8, the first group includes first and second stage shift register cells GOA1, GOA2 as first and second shift register cells in the first group, respectively, the second group includes third and sixth stage shift register cells GOA3, GOA4 as first and second shift register cells in the second group, respectively, and so on. Taking the first group as an example, the 2 output clock signal terminals CLK _1 and CLK _2 of the first shift register unit GOA1 are connected to the first output clock signal line CLK1 and the second output clock signal line CLK2 in a one-to-one correspondence, the control clock signal terminal CLK _ C of the first shift register unit GOA1 is connected to the first control clock signal line CLKC1, the 2 output clock signal terminals CLK _1 and CLK _2 of the second shift register unit GOA2 are connected to the third clock signal line CLK3 and the fourth clock signal line CLK4 in a one-to-one correspondence, and the control clock signal terminal CLK _ C of the second shift register unit GOA2 is connected to the second control clock signal line CLKC 2. The shift register units GOA3 and GOA4 in the second group are connected to clock signal lines CLKC1, CLKC2, CLK1-CLK8 in a similar manner, and are not described again here.

In the gate driving circuit of fig. 8, the N output clock signal terminals CLK _1 to CLK _ N of each shift register unit and the control clock signal terminal CLK _ C of the shift register unit are separated from each other, so that the cascade circuit can be independently clocked with respect to the N output circuits, improving control flexibility.

Fig. 9 is a signal timing diagram of a driving method of a shift register unit according to some embodiments. The method is applicable to the shift register unit of any of the embodiments described above. The driving method will be described by way of example with reference to the shift register unit shown in fig. 2.

In the first period T1, the pull-up circuit 10 supplies the first level of the INPUT signal terminal INPUT to the total pull-up node PU, and the nth output circuit 40 of the N output circuits 40 INPUTs the first level of the INPUT signal terminal INPUT to the nth pull-up node PU _ N. In conjunction with fig. 2, in this period, the high level of the INPUT signal terminal INPUT turns on the transistor M11, thereby supplying the high level of the INPUT signal terminal INPUT to the overall pull-up node PU, and the high level of the pull-up node PU turns on the transistor M22. The high level of the INPUT signal terminal INPUT also turns on the transistor M1 of each of the first and second output circuits 401 and 402, thereby providing the high level of the INPUT signal terminal INPUT to the first and second pull-up nodes PU _1 and PU _2, respectively. The high level of the first pull-up node PU _1 turns on the transistor M2 in the first output circuit 40_1, and the high level of the second pull-up node PU _2 turns on the transistor M2 in the second output circuit 40_ 2.

In the second period T2, the cascade circuit 30 supplies the signal of the control clock signal terminal CLK _ C to the cascade output terminal OUT _ C under the control of the potential of the overall pull-up node PU, and the nth output circuit 40 of the N output circuits 40 supplies the signal of the nth output clock signal terminal CLK _ N to the nth output signal terminal OUT _ N under the control of the potential of the nth pull-up node PU _ N. In conjunction with fig. 2, in this period, the high levels of the first and second output clock signal terminals CLK _1 and CLK _2 come in sequence, and since the respective transistors M2 of the first and second output circuits 40_1 and 40_2 are both in a conductive state, the signals of the first and second output clock signal terminals CLK _1 and CLK _2 are supplied to the first and second output signal terminals OUT _1 and OUT _2, respectively. During this time, the high levels of the first and second output signal terminals OUT _1 and OUT _2 further increase the potentials of the first and second pull-up nodes PU _1 and PU _2, respectively, due to the bootstrap action of the capacitor C1.

The signal at the control clock signal terminal CLK _ C is the same as the signal at the first output clock signal terminal CLK _1, and also, since the transistor M22 is in a conductive state, the signal at the control clock signal terminal CLK _ C is supplied to the cascade output terminal OUT _ C.

In the third period T3, the pull-up circuit 10 supplies the second level of the reset signal terminal RST _ PU to the total pull-up node PU, the potential of the pull-up node PU causes the control circuit 20 to control the pull-down node PD to the first level, the potential of the pull-down node PD causes the cascade circuit 30 to pull down the cascade output terminal OUT _ C to the second level, and the nth output circuit 40 of the N output circuits 40 to pull down the nth output signal terminal OUT _ N to the second level. Referring to fig. 2, in this period, the reset signal terminal RST _ PU is at a high level, and the transistor M20 is turned on, thereby pulling the total pull-up node PU down to a low level of the first reference signal terminal LVGL. The low level of the overall pull-up node PU turns off the transistor M9, and the pull-down node PD goes high. The high level of the pull-down node PD turns on the transistor M23 and the transistors M3 and M4 of the first output circuit 40_1 and the second output circuit 40_2, respectively. The turning on of the transistor M23 causes the cascade output terminal OUT _ C to be pulled down to the low level of the first reference signal terminal LVGL. The turn-on of the two transistors M3 causes the first and second pull-up nodes PU _1 and PU _12 to be pulled down to a low level of the first reference signal terminal LVGL. The turn-on of the two transistors M4 causes the first and second output signal terminals OUT _1 and OUT _2 to be pulled down to the low level of the second reference signal terminal VGL.

Some embodiments of the present disclosure also provide a driving method of a gate driving circuit, the method including: in a first mode, applying K first clock signals shifted sequentially row by row to the K clock signal lines, so that M-level shift register units of the gate driving circuit generate a plurality of first output signals shifted sequentially row by row; in a second mode, K second clock signals sequentially shifted by K rows are applied to the K clock signal lines so that M-stage shift register units of a gate driving circuit generate a plurality of second output signals sequentially shifted by K rows, where a frequency of the K second clock signals is K times that of the K first clock signals, where K is an integer less than or equal to K. The method will be exemplified below with reference to fig. 10 and 11.

Fig. 10 is a signal timing diagram of a driving method of a gate driving circuit in a first mode according to some embodiments; fig. 11 is a signal timing diagram of a driving method of a gate driving circuit in a second mode according to some embodiments. The method is applicable to the gate driving circuit of any of the embodiments described above. The driving method will be exemplarily described below by taking the gate driving circuit of fig. 6 as an example.

Referring to fig. 10 and 6, in the first mode, 12 first clock signals sequentially shifted row by row are applied to the 12 clock signal lines CLK1 to CLK12 of the gate driving circuit, so that the M-stage shift register cells GOA1, GOA2, …, GOAM of the gate driving circuit generate a plurality of first output signals G1, G2, … GM sequentially shifted row by row. The 12 first clock signals may be periodic signals, by shifting row by row, it is meant that the first clock signal on the second clock signal line CLK2 is shifted with respect to the first clock signal on the first clock signal line, the first clock signal on the third clock signal line CLK3 is shifted with respect to the first clock signal on the second clock signal line CKK2, and so on. The shift sizes may be equal, for example, each being H or an integer multiple of H, where H represents the time required to scan a row of subpixels, also referred to as a unit scan time.

Referring to fig. 6, at the start of scanning, the signal on the start signal line STV is at a high level, the first stage shift register unit GOA1 outputs 4 sequentially shifted output signals G1 to G4 at 4 output signal terminals OUT _1 to OUT _4 respectively based on the signal on the start signal line STV under the control of the clock signals on the clock signal lines CLK1 to CLK4, and outputs the same cascade signal as the output signal G1 at the cascade output terminal OUT _ C to the INPUT signal terminal INPUT of the second stage shift register unit GOA 2. The second stage shift register unit GOA2 outputs 4 sequential shift output signals G5 through G8 at 4 output signal terminals OUT _1 through OUT _4, respectively, under the control of clock signal lines CLK5 through CLK8 based on the cascade signal received at the INPUT signal terminal INPUT. At the timing indicated by the dotted line in fig. 10, the 4 th-stage shift register cell GOA4 generates the output signal G9 of high level and the cascade signal identical to G9. The cascade signal is received by the reset signal terminal RST _ PU of the first stage shift register GOA1, so that the total pull-up node PU and the four pull-up nodes PU _1 to PU _4 of the first stage shift register GOA1 are all pulled low, thereby implementing the reset. By analogy, in this way, the gate drive circuit outputs the sequentially shifted output signals G1, G2, … GM.

Referring to fig. 11 and 6, in the second mode, 12 second clock signals sequentially shifted by k lines (e.g., k ═ 2 in fig. 11) are applied to the 12 clock signal lines CLK1 to CLK12 of the gate driving circuit, so that the M-stage shift register units of the gate driving circuit generate a plurality of second output signals G1 to G4 sequentially shifted by k lines, wherein the frequency of the 12 second clock signals is k times that of the 12 first clock signals CLK1 to CLK 12. For example, in fig. 11, the first clock signal on the first clock signal line CLK1 and the second clock signal line CLK2 is the same, the first clock signal on the third clock signal line CLK3 and the fourth clock signal line CLK3 is the same, and shifted with respect to the first clock signal on the first and second clock signal lines CLK1 and CLK 2. Likewise, the clock signals on the fifth and sixth clock signal lines CLK5 and CLK6 are the same and shifted with respect to the first clock signal on the third and fourth clock signal lines CLK3 and CLK4, and so on.

Referring to fig. 6, at the start of scanning, the start signal STV is at a high level, and the first stage shift register cell GOA1 of the gate driving circuit generates 4 output signals G1 to G4 under the control of the first clock signal on the first to fourth clock signal lines CLK1 to CLK4 based on the start signal STV, wherein the output signals G1 and G2 are the same, and the output signals G3 and G4 are the same and shifted with respect to the output signals G1 and G2. By analogy, every two lines of simultaneous scanning can be realized. In the second mode of fig. 11, the frequencies of the 12 second clock signals on the clock signal lines CLK1 to CLK12 are 2 times that of the 12 first clock signals CLK1 to CLK12 of fig. 10, thereby improving the scanning speed. The pixel data lines can be charged as in the first mode (still 1H because two rows of pixels are charged at the same time), so that the image quality is not degraded, thereby realizing a 2-time refresh rate driven display.

Although K-12 and K-2 are exemplified in fig. 11, embodiments of the present disclosure are not limited thereto, and K may be set to other integers less than or equal to K as needed. For example, where 12 clock signals are used, the second mode may perform a 4-line scan, with the driving principle being similar to that described above, except that the frequency of the second clock signal used in the second mode is 1/4 which is the frequency of the first clock signal used in the first mode. Similarly, in the case of K-8, 2-line-by-2 (K-2) or 4-line-by-4 (K-4) scanning may also be performed.

Although the driving methods of fig. 10 and 11 are described above by taking the gate driving circuit of fig. 6 as an example, embodiments of the present disclosure are not limited thereto. The above driving method is also applicable to other gate driving circuits, for example, a gate driving circuit with K-8 and N-4, for example, the gate driving circuit of fig. 7. When this driving method is applied to the gate driving circuit of fig. 7, 8 clock signals are applied to 8 clock signal lines CLK1 to CLK8, respectively. In the first mode, the first clock signal on the clock signal lines CLK1-CLK8 has a pulse width of 4H and a duty cycle of 50%; in the second mode, the pulse width of the second clock signal on the clock signal lines CLK1-CLK8 is 2H, the duty cycle is still 50%, and the frequency is 2 times that of the first clock signal.

The embodiment of the present disclosure further provides another driving method of a gate driving circuit, where K clock signal lines connected to the gate circuit include a plurality of output clock signal lines, the method including: in a first mode, a plurality of first output clock signals which are sequentially shifted row by row are applied to the plurality of output clock signal lines, so that M stages of shift register units of the grid driving circuit generate a plurality of first output signals which are sequentially shifted row by row, wherein N output circuits of each stage of shift register unit generate output signals; in a second mode, a plurality of second output clock signals are applied to a part of the plurality of output clock signal lines, so that the M-stage shift register units of the gate driving circuit generate the plurality of second output signals sequentially shifted, wherein at least one output circuit of the N output circuits of each stage of the shift register does not generate an output signal. This method will be exemplified below with reference to fig. 12 and 13.

Fig. 12 is a signal timing diagram of another driving method of a gate driving circuit in a first mode according to some embodiments; fig. 13 is a signal timing diagram of another driving method of a gate driving circuit in a second mode according to some embodiments. The method is applicable to a gate driving circuit of a shift register unit, such as the gate driving circuit described above with reference to fig. 8, which controls the separation of the clock signal terminal CLK _ C and the output signal terminals CLK _1 to CLK _ N.

Referring to fig. 12 and 13, an example of the driving method will be described by taking the gate driving circuit shown in fig. 8 as an example.

Referring to fig. 12 and 8, in the first mode, 4 first output clock signals sequentially shifted row by row are applied to 4 output clock signal lines CLK1 to CLK4 of the gate driving circuit, so that the M-stage shift register cells GOA1, GOA2, …, GOAM of the gate driving circuit generate a plurality of first output signals G1, G2, … GM sequentially shifted row by row, wherein 2 output circuits of each stage of the shift register cells generate the output signals. In some embodiments, the first output clock signal has a pulse width of 4H and a duty cycle of 50%.

For example, in conjunction with fig. 8, a first control clock signal may be applied to the first control clock signal line CLKC1, a second control clock signal may be applied to the second control clock signal line CLKC2, and four first output clock signals sequentially shifted may be applied to the first output clock signal line CLK1, the second output clock signal line CLK2, the third output clock signal line CLK3, and the fourth output clock signal line CLK4, respectively, so that 2 output circuits of each stage of the shift register units GOA1, GOA2, …, GOAM all generate output signals.

As shown in fig. 12, at the start of scanning, the signal on the start signal line STV is at a high level, the first stage shift register unit GOA1 outputs 2 sequentially shifted output signals G1 and G2 at 2 output signal terminals OUT _1 and OUT _2, respectively, based on the signal on the start signal line STV under the control of the clock signals on the output clock signal lines CLK1 and CLK2, and outputs a cascade signal at the cascade output terminal OUT _ C under the control of the control clock signal on the control clock signal line CLKC 1. The cascade signal is provided to INPUT signal terminal INPUT of second stage shift register unit GOA 2. The second stage shift register unit GOA2 outputs 2 sequential shift output signals G3 and G4 at 2 output signal terminals OUT _1 and OUT _2, respectively, under the control of the output clock signal lines CLK3 and CLK4 based on the cascade signal received at the INPUT signal terminal INPUT, and outputs the cascade signal at the cascade output terminal OUT _ C under the control of the control clock signal on the control clock signal line CLKC 2. By analogy, in this way, the gate drive circuit outputs the sequentially shifted output signals G1, G2, … GM.

Referring to fig. 13 and 8, in the second mode, the second output clock signal is applied to a part of the output clock signal lines (in fig. 13, even output clock signal lines CLK2 and CLK4) among the output clock signal lines CLK1 to CLK4, so that the M-stage shift register cells GOA1, GOA2, …, GOAM of the gate driving circuit generate a plurality of second output signals G2, G4, G6, … that are sequentially shifted, wherein at least one of the 2 output circuits of each stage of the shift register cells does not generate an output signal.

For example, in conjunction with fig. 8, the first control clock signal CLKC1 may be applied to the first control clock signal line CLKC1, the second control clock signal CLKC2 may be applied to the second control clock signal line CLKC2, and two second output clock signals sequentially shifted may be applied to odd or even output clock signal lines among the first output clock signal line CLK1, the second output clock signal line CLK2, the third output clock signal line CLK3, and the fourth output clock signal line CLK4, respectively, so that one of the 2 output circuits of each stage of the shift register unit generates an output signal. In the example of fig. 13, the first output circuit of each shift register cell does not generate an output because it does not receive a clock signal, and the second output circuit generates an output based on the received clock signal, such that the first stage shift register cell GOA1 generates the output signal G2, the second stage shift register cell GOA2 generates the output signal G4, and so on, achieving that the odd rows of pixels are turned off, the even rows are scanned, and vice versa. For example, the output clock signals may be applied to the output clock signal lines CLK1 and CLK3 without applying the output clock signals to the output clock signal lines CLK2 and CLK4 such that the second output circuit of each stage of the shift register unit generates a signal while the first output circuit does not generate an output signal, thereby achieving the even rows of pixels being turned off and the odd rows being scanned.

By turning off one or more output signals, the gates of one or more sub-pixel rows are kept off, and data signals are prevented from being written. Thus, the delay caused by large load of data signals and short switching time can be avoided, thereby avoiding the problem of serial connection caused by wrongly writing the data signals into the adjacent sub-pixel rows and improving the display quality of the display device. For example, the gates of the sub-pixels in the odd sub-pixel row may be turned off, and the gates of the sub-pixels in the even sub-pixel row may be normally turned on to write the corresponding data signals. In this way, even if a delay occurs in the transmission of the data signal of a certain even sub-pixel row, since the gate of each sub-pixel of the next odd sub-pixel row is turned off, the data signal of the even sub-pixel row is not written into the following odd sub-pixel row, and thus the display serial phenomenon during the image display process can be avoided.

In some embodiments, the gate driving signals may be generated in an even line scanning manner in one frame, and the gate driving signals may be generated in an odd line scanning manner in the next frame. By alternating the odd line and even line closing modes between different frames, the effect of displaying complete pictures by overlapping frames can be realized by using the phenomenon of visual persistence of human eyes.

Fig. 14 is a signal timing diagram of a driving method of a gate driving circuit in a first mode and a second mode according to some embodiments. The driving method shown in fig. 14 is similar to the driving method described above with reference to fig. 12 and 13, except that at least in fig. 14, the output clock signals are applied to the output clock signal lines CLK1 and CLK3 in the second mode, and the output clock signals are not applied to the output clock signal lines CLK2 and CLK4, so that the second output circuit of each stage of the shift register unit generates a signal while the first output circuit generates no output signal, thereby achieving the even-numbered rows of the pixels being turned off and the odd-numbered rows being scanned.

Referring to fig. 14, the period of the second output clock signal applied to the output clock signal lines CLK1 to CLK4 in the second mode is equal to the period of the first output clock signal applied to the clock signal lines CLK1 to CLK4 in the first mode, and the duty ratio is greater than the duty ratio of the first output clock signal, for example, the duration of the active level of the former is longer than the latter by T, T ≦ H. In this case, the pulse width of the Data signal Data may also be increased by T accordingly as compared to the first mode, so that the charging time per odd-numbered line is increased by T, thereby improving the charging rate. When displaying the next frame, the odd lines are closed, and the charging time is increased by adopting the same principle.

In the above embodiment, the manner of odd-even switching is taken as an example in the second mode, but the embodiment of the present disclosure is not limited thereto. The plurality of output circuits of the shift register unit of the gate driving circuit may be switched as needed to generate different gate driving signals. For example, in the case where each shift register unit of the gate driver circuit has 4 output circuits, the first output circuit may be controlled to be turned off, and the second to fourth output circuits may generate outputs, in one frame by the clock signal; and in the next frame the first output circuit produces an output and the second value the fourth output circuit is turned off, thereby effecting a 1: 3 switching. Other switching schemes are also permissible and are not limited by the present disclosure.

It will be appreciated by those skilled in the art that the embodiments described above are exemplary and can be modified by those skilled in the art, and that the structures described in the various embodiments can be freely combined without conflict in structure or principle.

Having described preferred embodiments of the present disclosure in detail, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and the disclosure is not limited to the exemplary embodiments set forth herein.

Claims (26)

1. A shift register cell, comprising:

a pull-up circuit connected to an input signal terminal of the shift register unit, a total pull-up node, and a pull-down node, the pull-up circuit being configured to supply a signal of the input signal terminal to the total pull-up node and pull down a potential of the total pull-up node under control of a potential of the pull-down node;

a control circuit connected to the total pull-up node and the pull-down node, the control circuit configured to control a potential of the pull-down node according to a potential of the total pull-up node;

a cascade circuit connected to the total pull-up node, the pull-down node, and a cascade output terminal and a control clock signal terminal of the shift register unit, the cascade circuit being configured to supply a signal of the control clock signal terminal to the cascade output terminal under control of a potential of the total pull-up node, and pull down a potential of the cascade output terminal under control of a potential of the pull-down node;

n output circuits respectively connected to the input signal terminal, the pull-down node, and N output clock signal terminals, N pull-up nodes, and N output signal terminals of the shift register unit, wherein an nth output circuit is connected to the input signal terminal, the pull-down node, an nth output signal terminal, and an nth pull-up node, and is configured to input a signal of the input signal terminal to the nth pull-up node, supply a signal of the nth output clock signal terminal to the nth output signal terminal under control of a potential of the nth pull-up node, and pull down a potential of the nth output signal terminal under control of a potential of the pull-down node, where N is an integer greater than 1, N is an integer, and 1 ≦ N.

2. The shift register cell of claim 1, wherein the nth output circuit comprises:

an input sub-circuit connected to the input signal terminal and the nth pull-up node, and configured to provide a signal of the input signal terminal to the nth pull-up node;

an output sub-circuit connected to the nth pull-up node, the nth output clock signal terminal, and the nth output signal terminal, and configured to supply a signal of the nth output clock signal terminal to the nth output signal terminal under control of a potential of the nth pull-up node; and the number of the first and second groups,

a pull-down sub-circuit connected to the pull-down node and configured to pull down potentials of the nth pull-up node and the nth output signal terminal under control of a potential of the pull-down node.

3. The shift register cell of claim 2, wherein the pull-down node comprises a first pull-down node and a second pull-down node, the pull-down sub-circuit comprises a first pull-down sub-circuit and a second pull-down sub-circuit, wherein,

the first pull-down sub-circuit is connected to the first pull-down node and configured to pull down a potential of at least one of the nth pull-up node and the nth output signal terminal under control of a potential of the first pull-down node;

the second pull-down sub-circuit is connected to the second pull-down node, and is configured to pull down a potential of at least one of the nth pull-up node and the nth output signal terminal under control of a potential of the second pull-down node.

4. The shift register cell of claim 3, wherein the control circuit comprises:

a first control sub-circuit connected to the total pull-up node and the first pull-down node, and configured to control a potential of the first pull-down node according to a potential of the total pull-up node;

a second control sub-circuit connected to the total pull-up node and the second pull-down node, and configured to control a potential of the second pull-down node according to a potential of the total pull-up node.

5. The shift register cell of claim 2 or 3, wherein the nth output circuit further comprises:

a reset sub-circuit connected to the nth pull-up node and the reset signal terminal and the reference signal terminal of the shift register unit, and configured to reset the nth pull-up node with a potential of the reference signal terminal under control of a signal of the reset signal terminal.

6. The shift register cell of any one of claims 2 to 5, wherein the input sub-circuit is further connected to a power supply signal terminal and configured to supply a potential of the power supply signal terminal to the nth pull-up node under control of a signal of the input signal terminal.

7. The shift register cell of any one of claims 1 to 6, wherein a first output clock signal terminal of the N output clock signal terminals is connected with the control clock signal terminal.

8. The shift register cell of claim 2, wherein the input subcircuit comprises: a first transistor, a gate of the first transistor and a first pole of the first transistor being connected to the input signal terminal, a second pole of the first transistor being connected to the n-th pull-up node.

9. The shift register cell of claim 6, wherein the input subcircuit comprises: a first transistor, a gate of which is connected to the input signal terminal, a first pole of which is connected to the power supply signal terminal, and a second pole of which is connected to the n-th pull-up node.

10. The shift register cell of claim 2, wherein the output subcircuit comprises:

a second transistor having a gate connected to the nth pull-up node, a first pole connected to the nth output clock signal terminal, and a second pole connected to the nth output signal terminal; and

a first terminal of the first capacitor is connected to the nth pull-up node, and a second terminal of the first capacitor is connected to the nth output signal terminal.

11. The shift register cell of claim 2, wherein the pull-down subcircuit comprises:

a third transistor having a gate connected to the pull-down node, a first pole connected to the first reference signal terminal of the shift register unit, and a second pole connected to the n-th pull-up node;

a fourth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the second reference signal terminal of the shift register unit, and a second pole of which is connected to the nth output signal terminal.

12. The shift register cell of claim 3,

the first pull-down sub-circuit includes a third transistor and a fourth transistor, a gate of the third transistor is connected to the first pull-down node, a first pole of the third transistor is connected to the first reference signal terminal of the shift register unit, a second pole of the third transistor is connected to the nth pull-up node, a gate of the fourth transistor is connected to the first pull-down node, a first pole of the fourth transistor is connected to the second reference signal terminal of the shift register unit, and a second pole of the fourth transistor is connected to the nth output signal terminal;

the second pull-down sub-circuit includes a fifth transistor and a sixth transistor, a gate of the fifth transistor is connected to the second pull-down node, a first pole of the fifth transistor is connected to the first reference signal terminal, a second pole of the fifth transistor is connected to the n-th pull-up node, a gate of the sixth transistor is connected to the second pull-down node, a first pole of the sixth transistor is connected to the second reference signal terminal, and a second pole of the sixth transistor is connected to the n-th output signal terminal.

13. The shift register cell of claim 5, wherein the reset subcircuit includes a seventh transistor, a gate of the seventh transistor is connected to the reset signal terminal, a first pole of the seventh transistor is connected to the reference signal terminal, and a second pole of the seventh transistor is connected to the n-th pull-up node.

14. The shift register cell of claim 1, wherein the control circuit comprises:

a gate of the eighth transistor and a first pole of the eighth transistor are connected to a power signal terminal of the shift register unit, and a second pole of the eighth transistor is connected to the pull-down node;

a ninth transistor having a gate connected to the total pull-up node, a first pole connected to the reference signal terminal of the shift register unit, and a second pole connected to the pull-down node.

15. The shift register cell of claim 4,

the first control sub-circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor, a gate of the tenth transistor and a first pole of the tenth transistor are connected to the power supply signal terminal of the shift register unit, a second pole of the tenth transistor is connected to the gate of the eleventh transistor, a first pole of the eleventh transistor is connected to the power supply signal terminal, a second pole of the eleventh transistor is connected to the first pull-down node, a gate of the twelfth transistor is connected to the total pull-up node, a first pole of the twelfth transistor is connected to the reference signal terminal of the shift register unit, a second pole of the twelfth transistor is connected to the gate of the eleventh transistor, a gate of the thirteenth transistor is connected to the total pull-up node, and a first pole of the thirteenth transistor is connected to the reference signal terminal, a second pole of the thirteenth transistor is connected to the first pull-down node;

the second control sub-circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor, a gate of the fourteenth transistor and a first pole of the fourteenth transistor are connected to the power supply signal terminal, a second pole of the fourteenth transistor is connected to the gate of the fifteenth transistor, a first pole of the fifteenth transistor is connected to the power supply signal terminal, a second pole of the fifteenth transistor is connected to the second pull-down node, a gate of the sixteenth transistor is connected to the total pull-up node, a first pole of the sixteenth transistor is connected to the reference signal terminal, a second pole of the sixteenth transistor is connected to the gate of the fifteenth transistor, a gate of the seventeenth transistor is connected to the total pull-up node, a first pole of the seventeenth transistor is connected to the reference signal terminal, a second pole of the seventeenth transistor is connected to the second pull-down node.

16. The shift register cell of claim 1, wherein the pull-up circuit comprises:

an eighteenth transistor having a gate thereof and a first pole thereof connected to the input signal terminal, a second pole thereof connected to the total pull-up node;

a nineteenth transistor having a gate connected to the pull-down node, a first pole connected to the reference signal terminal of the shift register unit, a second pole connected to the total pull-up node,

a twentieth transistor, a gate of which is connected to the reset signal terminal of the shift register unit, a first pole of which is connected to the reference signal terminal, and a second pole of which is connected to the total pull-up node.

17. The shift register cell of claim 16, wherein the pull-down node comprises a first pull-down node and a second pull-down node, the pull-up circuit further comprising a twenty-first transistor, wherein,

a gate of the nineteenth transistor is connected to the first pull-down node, a gate of the twenty-first transistor is connected to the second pull-down node, a first pole of the twenty-first transistor is connected to the reference signal terminal, and a second pole of the twenty-first transistor is connected to the total pull-up node.

18. The shift register cell of claim 1, wherein the cascade circuit comprises:

a twenty-second transistor, a gate of the twenty-second transistor being connected to the total pull-up node, a first pole of the twenty-second transistor being connected to the control clock signal terminal, a second pole of the twenty-second transistor being connected to the cascade output terminal;

a twenty-third transistor, a gate of the twenty-third transistor being connected to the pull-down node, a first pole of the twenty-third transistor being connected to the reference signal terminal of the shift register unit, and a second pole of the twenty-third transistor being connected to the cascade output terminal;

a second capacitor, a first end of the second capacitor is connected to the gate of the twenty-second transistor, and a second end of the second capacitor is connected to the cascade output terminal.

19. The shift register cell of claim 18, wherein the pull-down node comprises a first pull-down node and a second pull-down node, the cascode circuit further comprising a twenty-fourth transistor, wherein,

a gate of the twenty-fourth transistor is connected to the first pull-down node, a gate of the twenty-fourth transistor is connected to the second pull-down node, a first pole of the twenty-fourth transistor is connected to the reference signal terminal, and a second pole of the twenty-fourth transistor is connected to the cascade output terminal.

20. The shift register cell of claim 1, further comprising an overall reset circuit comprising a twenty-fifth transistor having a gate connected to an overall reset terminal of the shift register cell, a first pole of the twenty-fifth transistor connected to a reference signal terminal of the shift register cell, and a second pole of the twenty-fifth transistor connected to the overall pull-up node.

21. The shift register cell of any one of claims 1-20, wherein 2 ≦ N ≦ 8.

22. A gate drive circuit comprising M cascaded shift register cells, the shift register cells being according to any one of claims 1 to 21,

wherein, the input signal end of the M-th stage shift register unit is connected with the cascade output end of the M-1 th stage shift register unit, the reset signal end of the M-th stage shift register unit is connected with the cascade output end of the M +2 th stage shift register unit, M is an integer larger than 1, M is an integer and 1 < M < M-1, and

the M cascaded shift register units are connected to K clock signal lines, wherein K is an even number greater than or equal to 2N.

23. The gate driving circuit according to claim 22, wherein N is 4, K is 12, the M cascaded shift register units are divided into a plurality of groups, each group includes 3 cascaded first, second, and third shift register units, wherein N output clock signal terminals of the first shift register unit are connected to the first to fourth clock signal lines in a one-to-one correspondence, N output clock signal terminals of the second shift register unit are connected to the fifth to eighth clock signal lines in a one-to-one correspondence, and N output clock signal terminals of the third shift register unit are connected to the ninth to twelfth clock signal lines in a one-to-one correspondence.

24. The gate driving circuit according to claim 22, wherein N is 4, K is 8, the M cascaded shift register units are divided into a plurality of groups, each group includes 2 cascaded first and second shift register units, wherein N output clock signal terminals of the first shift register unit are connected to the first to fourth clock signal lines in a one-to-one correspondence, and N output clock signal terminals of the second shift register unit are connected to the fifth to eighth clock signal lines in a one-to-one correspondence.

25. The gate driving circuit according to claim 23 or 24, wherein a first output clock signal terminal of the N output clock signal terminals of each shift register unit is connected to a control clock signal terminal of the shift register unit.

26. The gate driving circuit of claim 22, wherein N-2, K-6, the K clock signal lines include a first control clock signal line, a second control clock signal line, a first output clock signal line, a second output clock signal line, a third output clock signal line, and a fourth output clock signal line,

the shift register units of the M-level cascade are divided into a plurality of groups, each group comprises a first shift register unit and a second shift register unit of 2-level cascade, N output clock signal ends of the first shift register unit are connected with a first output clock signal line and a second output clock signal line in a one-to-one correspondence mode, a control clock signal end of the first shift register unit is connected with a first control clock signal line, N output clock signal ends of the second shift register unit are connected with a third clock signal line and a fourth clock signal line in a one-to-one correspondence mode, and a control clock signal end of the second shift register unit is connected with a second control clock signal line.

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