KR102160881B1 - Micro light emitting diode - Google Patents

Abstract

Disclosed is a micro light emitting diode comprising: a substrate; a first semiconductor layer positioned on the substrate wherein a nitride is deposited; a second semiconductor layer positioned on the first semiconductor layer and emitting light by depositing the nitride in a plurality of layers; and a passivation layer including an insulating material deposited on a side wall of the second semiconductor layer and having a specific pattern etched on one side thereof. According to the present invention, the reduction in efficiency due to side wall defects can be reduced through side wall passivation.

Description

Micro light emitting diode {MICRO LIGHT EMITTING DIODE}

The present invention relates to a micro light emitting diode, and more particularly, to a micro light emitting diode having a passivation layer by etching a specific pattern.

The content described in this section merely provides background information on the present embodiment and does not constitute the prior art.

Micro-LED display refers to a display using ultra-small light-emitting diodes (LEDs), which is 1/10 the size of conventional mini-LEDs. Say.

Micro-LEDs are attracting attention as a next-generation display because they have excellent characteristics and unique performance, and research is being conducted for the purpose of applying them in various fields.

Representatively, a technology for phototherapy in the medical/bio industry, a technology that applies micro-LEDs to increase the resolution of irradiating the light in front in the automotive industry, and a technology that can deliver large amounts of information in communication As a solution, technologies related to Li-Wi using micro-LEDs are being actively studied.

In particular, display is a field in which micro-LEDs are typically used. As a display, micro-light-emitting diodes (Micro-LEDs) are different from liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs), which have limitations in brightness. Since Display) is an inorganic light emitting diode (LED), it can realize very high luminance because it has characteristics such as improved light extraction, low contact temperature, improved heat distribution, and good current density distribution.

In addition, Micro-LEDs can support a long life span, form factor, and ultra-high resolution based on high efficiency.

Due to these advantages, it can be applied to a smart phone, a smart watch, a head mounted display (HMD), and a near-eye display (NED).

However, micro-LEDs have a problem in that efficiency decreases as the size decreases. Accordingly, there is a need for a method to improve efficiency reduction and improve the uniformity of display pixels in order to use micro-LEDs as micro-displays. This is constantly being raised.

Korean Patent Registration No. 10-2011-0139021 (2014.06.18.) Korean Patent Publication No. 10-2010-7020645 (2011.01.20.) Korean Patent Publication No. 10-2017-0065883 (2008.10.01.)

The technical problem of the present invention was conceived in this respect, and according to one aspect of the present invention, a passivation layer is deposited on the sidewall of the micro light emitting diode 10 to prevent efficiency reduction, and a part of the passivation layer is etched ) To provide a micro light emitting diode 10 (Micro-LED) that improves uniformity.

The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

According to an embodiment of the present invention, a substrate; A first semiconductor layer on the substrate and on which nitride is deposited; A second semiconductor layer positioned on the first semiconductor layer and emitting light by depositing a plurality of nitride layers; And a passivation layer including an insulating material deposited on a sidewall of the second semiconductor layer, and having a specific pattern etched on one side thereof.

In an embodiment, the first semiconductor layer includes: a template layer doped with gallium nitride (GaN) and positioned on the substrate; And an n-type nitride layer disposed on the template layer and on which n-type gallium nitride (n-GaN) doped with silicon (Si) is deposited.

In one embodiment, the second semiconductor layer is positioned on the first semiconductor layer, a superlattice layer doped with silicon of 30 cycles made of gallium nitride (GaN) and indium gallium nitride (AlGaN); An active layer disposed on the superlattice layer and including a plurality of multiple quantum wells including an indium gallium nitride (AlGaN) well and a gallium nitride (GaN) barrier; An electron blocking layer disposed on the active layer and on which aluminum gallium nitride (AlGaN) doped with magnesium (Mg) is deposited; A p-type nitride layer on which a p-type gallium nitride (p-GaN) doped with magnesium (Mg) is deposited on the electron blocking layer; A p+-type nitride layer on which a p+-type gallium nitride (p+-GaN) doped with magnesium (Mg) is deposited on the p-type nitride layer; And a transparent electrode layer positioned on the p+ type nitride layer and on which indium tin oxide (ITO) is deposited.

In one embodiment, the passivation layer may be formed by depositing silicon dioxide (SiO2) on one sidewall of the second semiconductor layer.

In one embodiment, the passivation layer may be formed by depositing silicon dioxide (SiO ₂ ) after disposing an aluminum oxide (Al ₂ O ₃ ) layer.

In one embodiment, the passivation layer may be etched into a vertically connected stripe shape.

In one embodiment, the passivation layer may be etched into at least one stripe shape.

In one embodiment, the passivation layer may be etched by extending from the transparent electrode layer to the superlattice layer.

In an embodiment, the passivation layer may be etched by extending from the transparent electrode layer to the active layer.

In an embodiment, the passivation layer may be etched by extending from the transparent electrode layer to the electron blocking layer.

In an embodiment, the passivation layer may be etched by extending from the transparent electrode layer to the p-type nitride layer.

In an embodiment, the passivation layer may be etched by extending from the transparent electrode layer to the p+ type nitride layer.

In an embodiment, the passivation layer may be etched in the form of an equilateral trapezoid.

According to an aspect of the present invention described above, the effect provided by the micro-LED of the present invention is, first, the reduction in efficiency due to side wall defects is reduced by side wall passivation. Second, by intentionally etching the side wall passivation to create a pattern that induces degradation, there is an advantageous effect of improving uniformity.

The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view showing the structure of a micro light emitting diode according to an embodiment of the present invention.
2 is a side view illustrating a state in which a passivation layer on a sidewall of a second semiconductor layer is etched into a single stripe according to an exemplary embodiment.
3 is a side view illustrating a state in which a passivation layer on a sidewall of a second semiconductor layer is etched with a plurality of stripes according to an exemplary embodiment.
4 is a side view illustrating a state in which only a specific layer is etched from a passivation layer of a sidewall of a second semiconductor layer according to an exemplary embodiment.
5 is a side view illustrating a state in which a passivation layer on a sidewall of a second semiconductor layer is etched in an equilateral trapezoid according to an exemplary embodiment.
6 is a diagram schematically illustrating a process in which a carrier is recombined.
7 is a diagram showing a circumference-to-area ratio according to the size of a micro-light emitting diode (Micro-LED).
FIG. 8 is a diagram showing a change in external quantum efficiency (EQE) over time of thermal annealing.
9 is a diagram showing a change in external quantum efficiency (EQE) according to a size change of a micro light emitting diode (Micro LED).
10 is a diagram showing changes in external quantum efficiency (EQE) of a micro light emitting diode (Micro LED) having a size of 20 μm×20 μm.
11 is a diagram showing the relationship between voltage and current density of a micro light emitting diode (Micro LED) having a size of 20 μm×20 μm.
12 is a diagram showing a relationship between current density and brightness according to the size of a micro-LED.
13 is a diagram illustrating a change in the influence of a defect due to side wall etching.

DETAILED DESCRIPTION OF THE INVENTION The detailed description of the present invention to be described below refers to the accompanying drawings, which illustrate specific embodiments in which the present invention may be practiced. These embodiments are described in detail sufficient to enable a person skilled in the art to practice the present invention. It is to be understood that the various embodiments of the present invention are different from each other, but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention in relation to one embodiment. In addition, it is to be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the present invention. Accordingly, the detailed description to be described below is not intended to be taken in a limiting sense, and the scope of the present invention, if properly described, is limited only by the appended claims, along with all scopes equivalent to those claimed by the claims. Like reference numerals in the drawings refer to the same or similar functions over several aspects.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a cross-sectional view showing the structure of a micro light emitting diode according to an embodiment of the present invention.

Referring to FIG. 1, a micro light emitting diode 10 includes a substrate 110, an n-type metal electrode 130, a p-type metal electrode 150, a reflector 170, a first semiconductor layer 200, and It can be seen that the structure includes the second semiconductor layer 300.

The micro light emitting diode 10 may be a C-plane III-Nitride LED. The structure of a C-plane III-Nitride LED (C-plane III-Nitride LED) can be fabricated by using a chemical vapor deposition (CVD) method on the substrate 110 having a curved pattern formed thereon.

In this case, sapphire is mainly used as a raw material for the substrate 110 on which the curved pattern is formed, and when sapphire is used, it is called patterned sapphire substrates 110 (PSS, patterned sapphire substrates).

The chemical vapor deposition method (CVD) may mainly use metalorganic chemical vapor deposition (MOCVD).

A first semiconductor layer 200 may be deposited on the patterned sapphire substrate 110, and a second semiconductor layer 300 may be deposited on the first semiconductor layer.

The first semiconductor layer 200 is positioned on the substrate 110 and may include a template layer 210 and an n-type nitride layer 230.

The template layer 210 is an unintentionally doped GaN template layer.

The n-type nitride layer 230 is an n-nitride layer (n-GaN layer) doped with silicon (Si), and may have a thickness of 4 μm.

The second semiconductor layer 300 is located on the first semiconductor layer 200 and is a superlattice layer 310, an active layer 320, an electron blocking layer 330, a p-type nitride layer 340, and a p+-type nitride. A layer 350 and a transparent electrode layer 360 may be included.

The super lattice layer 310 is on the n-type nitride layer 230 of the first semiconductor layer 200 and is doped with 30 cycles of silicon (Si) made of gallium nitride (GaN) and indium gallium nitride (AlGaN). May be, and the thickness may be 20 nm.

The active layer 320 is positioned on the superlattice layer 310 and may constitute a plurality of multiple quantum wells including an indium gallium nitride well and a gallium nitride barrier. have.

In this case, the thickness of the indium gallium nitride well (InGaN well) may be 2.4 nm, the thickness of the gallium nitride barrier (GaN barrier) may be 22 nm, and the number of multiple quantum wells may be 6 .

Among the 22 nm gallium nitride barrier (GaN barrier), 3 nm is grown at the same temperature as indium gallium nitride (InGaN), and the remaining 19 nm is grown at 50°C higher temperature. By repeating the growth process, a gallium nitride barrier and an indium gallium nitride well can be made.

Quantum wells are intended to increase efficiency, and direct band gap materials with small band gaps are used between direct band gap materials with large band gaps. It can be made into a recessed structure. In this case, the lattice constant of the direct band gap material with a large band gap and the direct band gap material with a small band gap must be the same as possible. have.

The electron blocking layer 330 is a region having a high bandgap energy located at the confinement layer-active layer interface to reduce the separation of carriers outside the active region.

The electron blocking layer 330 is positioned on the active layer 320, and magnesium-doped aluminum gallium nitride (Mg-doped AlGaN) may be deposited, and may have a thickness of 26 nm.

The p-type nitride layer 340 is positioned on the electron blocking layer 330 and is a p-type nitride layer doped with magnesium (Mg-doped p-GaN layer).

The p+-type nitride layer 350 is positioned on the p-type nitride layer 340 and is a p+-type nitride layer doped with magnesium (Mg) (Mg-doped p+-GaN layer).

The transparent electrode layer 360 is configured for light transmission and ohmic p-contact.

The transparent electrode layer 360 is positioned on the p+ type nitride layer, and indium tin oxide (ITO) may be deposited using electron-beam evaporation, and may have a thickness of 110 nm.

Before depositing the reflector 170, the transparent electrode layer 360 and the n-type nitride layer 230 are etched using reactive-ion etching (RIE), and the reflector 170 is It can be deposited by ion-beam deposition.

The reflector 170 is an omnidirectional reflector (ODR) having a reflectance of 95.5% in blue light in a wavelength range of 430 nm to 450 nm.

In addition, the reflector 170 may separate an n-type contact and a p-contact with a metal isolation dielectric layer, and light in a metal layer Can improve reflection.

The reflector 170 may be formed of silicon dioxide (SiO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), and aluminum oxide (Al ₂ O ₃ ) thereon as a capping layer.

Metal contacts of 700 nm of aluminum (Al), 100 nm of nickel (Ni), and 700 nm of gold (Au) may be deposited by E-beam evaporation.

FIG. 2 is a side view illustrating a state in which a passivation layer on a sidewall of a second semiconductor layer of a micro light emitting diode is etched according to an exemplary embodiment.

Referring to FIG. 2, it can be seen that the passivation layer 400 may be etched into a vertically connected stripe shape.

The passivation layer 400 may be deposited on one side wall of the second semiconductor layer 300, and the deposited passivation layer 400 may be etched into a pattern that induces degradation. have.

The passivation layer 400 may improve efficiency by disposing an insulating material such as silicon dioxide (SiO ₂ ) on the side wall of the micro light emitting diode 10 to reduce the influence of side wall defects.

In addition, the passivation layer 400 may reduce non-radiative recombination by depositing silicon dioxide (SiO ₂ ) after the aluminum oxide (Al2O3) layer is disposed.

A part of the passivation layer 400 may be etched with a pattern that induces degradation of the micro light emitting diode 10 to improve uniformity of light emission.

When a part of the passivation layer 400 is etched, an error of the influence of side wall defects can be reduced, and according to the reduced error, the micro light emitting diode 10 becomes more uniform even at low luminance. Can work.

That is, the efficiency may decrease according to etching, but the uniformity may be improved, so that both are trade off.

Therefore, the degree of degradation that can be used at a low current density and uniformity in the low luminance of each device using a micro-light emitting diode (Micro-LED) in the lateral part (Uniformity) determines the etching area.

In order to uniformly effect defects on the lateral side of the device, the side wall is etched by vertically etching uniformly on the lateral side.

Since the effect of defects is increased through uniform etching on the side wall passivation, the efficiency of the device is degraded, but the uniformity due to defects is small. It is possible to induce uniform light emission with low luminance at a very low current density.

Detailed effects of etching the passivation layer 400 and a part of the passivation layer 400 described above will be described below with reference to FIGS. 6 to 13.

3 is a side view illustrating a state in which a passivation layer of a sidewall of a second semiconductor layer is etched into a plurality of stripes according to an exemplary embodiment.

Referring to FIG. 3A, it can be seen that the passivation layer 400 may be etched into two stripes.

Referring to FIG. 3B, it can be seen that the passivation layer 400 may be etched into three stripes.

4 is a side view illustrating a state in which only a specific layer is etched from a passivation layer of a sidewall of a second semiconductor layer according to an exemplary embodiment.

Referring to FIG. 4A, it can be seen that the passivation layer 400 extends from the transparent electrode layer 360 to the superlattice layer 310 and may be etched.

Referring to FIG. 4B, it can be seen that the passivation layer 400 extends from the transparent electrode layer 360 to the active layer 320 and may be etched.

Referring to FIG. 4C, it can be seen that the passivation layer 400 extends from the transparent electrode layer 360 to the electron blocking layer 330 and may be etched.

Referring to FIG. 4D, it can be seen that the passivation layer 400 extends from the transparent electrode layer 360 to the p-type nitride layer 340 and may be etched.

Referring to FIG. 4E, it can be seen that the passivation layer 400 extends from the transparent electrode layer 360 to the p+ type nitride layer 350 and may be etched.

5 is a side view illustrating a state in which a passivation layer of a sidewall of a second semiconductor layer is etched in an isosceles trapezoid according to an exemplary embodiment.

Referring to FIG. 5A, it can be seen that the passivation layer 400 may be etched in the shape of an isosceles trapezoid having a narrow top.

Referring to FIG. 5B, it can be seen that the passivation layer 400 may be etched in a shape of an isosceles trapezoid having a narrow lower end.

6 is a diagram schematically illustrating a process in which a carrier is recombined.

In general, the efficiency of light-emitting diodes (LEDs) is determined by competition between radiative recombination and non-radiative recombination.Shockley-Lead-Hall (SRH) is a typical non-radiative recombination. , Shockley-Read-Hall) recombination and Auger recombination.

Referring to FIG. 6A, a process of radiative recombination can be seen.

Radiative recombination refers to light having a wavelength determined by energy generated when carriers are recombined from a band to a band (band to band process).

Referring to FIG. 6B, a process of Auger recombination, which is a type of non-radiative recombination, can be seen.

Auger recombination is a process in which electrons and holes are recombined by coulomb interactions in a semiconductor material, and electrons and holes are recombined. The energy of (hole) is used to increase the energy of other electrons or holes.

Referring to FIG. 6C, a shockley-lead-hole recombination process, which is a type of non-radiative recombination, can be seen.

Shockley-lead-hole recombination (SRH recombination) is a process in which electrons and holes are recombined by defects in a semiconductor material, and the energy of electrons and holes is recombination. ) During the process, it is released in the form of heat energy, reducing efficiency.

At this time, in general, a trap layer or the like acts as a non-radiative recombination center.

7 is a diagram showing a circumference-to-area ratio according to the size of a micro-LED.

Referring to FIG. 7, a perimeter, an area, and a ratio of a perimeter to an area can be known according to the size of the micro-LED 10.

The ratio of perimeter to area is calculated by dividing the perimeter by the area, and as the perimeter decreases, the area decreases exponentially, so the perimeter to area ) You can see that the rate increases.

In the case of 100 µm × 100 µm, the ratio is 0.04, but in the case of 10 µm × 10 µm in which the perimeter is reduced to 1/10, the ratio is 0.4.

The meaning of the perimeter-to-area ratio means that the smaller the size of the micro-LEDs 10, the larger the ratio occupied by the perimeter.

The efficiency of the light emitting diode (LED) may be affected by the current density and the size of the light emitting diode (LED).

First, in high current density, the efficiency is constant regardless of the size.

However, at a low current density, the type of non-radiative recombination that reduces efficiency may vary as the size decreases.

The efficiency of a light emitting diode (LED) having a general size is dominated by a decrease in efficiency due to Auger recombination, which is a non-radiative recombination.

However, as the size of the light emitting diode (LED) becomes smaller, the efficiency decreases due to shockley-lead-hole recombination, which is affected by side wall defects.

A small change in the periodicity of the crystal lattice occurs at the edge during the process, resulting in a side-wall defect.

The semiconductor gap caused by the side-wall defect induces electronic states and acts as a non-radiative recombination center, resulting in shockley-lead-hole non-luminescence recombination. (SRH non-radiative recombination) is induced.

Therefore, as the size of the light emitting diode (LED) decreases, the side region increases compared to the Mesa region, and side wall defects increase as the side region increases. This is because shockley-lead-hole non-radiative recombination increases.

Therefore, it is necessary to reduce the shockley-lead-hole recombination (SRH-recombination), which is the main cause of efficiency reduction at low current density.

There are two representative ways to reduce the impact of side wall defects that act as non-radiative recombination centers at the side walls to reduce shockley-lead-hole recombination (SRH-recombination). There is.

The first way to reduce the effect of side wall defects is side wall passivation, an insulating material such as silicon dioxide (SiO ₂ ) on the side wall of a micro-LED. This is a method of reducing the influence of defects by disposing them as the passivation layer 400.

In this case, the passivation layer 400 described above with reference to FIGS. 1 to 4 means side wall passivation.

The side wall passivation process may be added before depositing the metal electrodes 130 and 150 in the fabrication process of the micro-light-emitting diode 10 (Micro-LED).

At this time, the efficiency of the small size Micro-LED may vary according to the etching method and the deposition method of the micro-light-emitting diode (Micro-LED).

Representative methods of depositing side wall passivation include atomic layer deposition (ALD) and double dielectric passivation.

In the case of the atomic layer deposition method (ALD), the deposition rate is very slow, but it can be deposited accurately and uniformly.

The thickness of the side wall passivation layer 400 of the micro-light-emitting diode (10, Micro-LED) is very thin at the level of 50 nm, so the atomic layer deposition method (ALD) for side wall passivation You can use

Another passivation method is a double dielectric passivation method.

The double dielectric passivation method is a non-radiative recombination through more effective passivation by placing an aluminum oxide layer (Al ₂ O ₃ layer) before the silicon dioxide layer (SiO ₂ layer). It can reduce the light emitting diode (LED) itself by reabsorbing light emitted from the etched surface (etched surface) can increase the efficiency.

A representative etching method of a micro-light-emitting diode (Micro-LED) is wet etch.

Wet etching is etching using a liquid chemical that has the property of corrosively dissolving only the target metal, and hydrofluoric acid (HF) is mainly used as a liquid.

Side wall passivation reduces the impact of leakage current and improves external quantum efficiency (EQE) by reducing the shockly-lead-hole recombination (SRH-recombination) caused by defects. I can.

FIG. 8 is a diagram showing a change in external quantum efficiency (EQE) over time of thermal annealing.

A second way to reduce the effects of side wall defects is thermal annealing.

In the case of thermal annealing, as the annealing time increases, some of the side wall defects recover, and the efficiency of the micro-LED at low current density This can be improved.

Referring to FIG. 8A, when the thermal annealing is performed in two weights, the external quantum efficiency (EQE) according to the size of the micro light emitting diode 10 can be known, and referring to FIG. 8B , When the thermal annealing (Thermal Annealing) is performed by 3 minutes, the external quantum efficiency (EQE) according to the size of the micro light emitting diode 10 (Micro-LED) can be known.

It can be seen that the external quantum efficiency (EQE) does not exceed 0.07 when thermal annealing is performed by two weights, but there are cases in which it exceeds 0.075 when thermal annealing is performed for 3 minutes.

In particular, it can be seen that the external quantum efficiency (EQE) reaches 0.1 when the size of the micro light emitting diode 10 (Micro-LED) is 6 μm.

In addition, as a common feature shown in FIGS. 8A and 8B, it can be seen that the smaller the size of the micro light emitting diode 10, the higher the external quantum efficiency (EQE).

A change in the external quantum efficiency (EQE) according to the size will be described below with reference to FIG. 9.

9 is a diagram showing a change in external quantum efficiency (EQE) according to a size change of a micro light-emitting diode 10, and FIG. 10 is an external quantum of a micro light-emitting diode (Micro LED) having a size of 20 μm×20 μm. It is a diagram showing a change in efficiency (EQE).

9 and 10, the external quantum efficiency according to the change in current density ( EQE) changes.

A micro-display using a micro-light-emitting diode (Micro-LED) is driven by voltage.

In other words, it is a principle of controlling luminance by controlling luminance compared to input voltage. The (current density) also changes.

In the case of a small size Micro-LED, the efficiency is drastically reduced by the shockley-lead-hole non-radiative recombination at low current density.

In the case of a very small size Micro-LED, when the current density is small, the influence of the side wall defect is very large, so the injected carrier is not affected by the defect. Since it is lost due to non-radiative recombination, it is impossible to perform radiative recombination, so it hardly emits light.

Therefore, the current density is increased by injecting an input voltage above a certain level. At this time, if the starting point of the linear luminance is different for each element, the uniformity deteriorates and the display becomes a display. It can be a problem to use.

FIG. 11 is a diagram showing the relationship between voltage and current density of a micro light emitting diode 10 (Micro LED) having a size of 20 μm×20 μm, and FIG. 12 is a current density and brightness according to the size of the micro light emitting diode (Micro-LED). It is a diagram showing the relationship of.

Referring to FIGS. 11 and 12, it can be seen the constant of external quantum efficiency (EQE) according to a change in current density in a micro light emitting diode (Micro LED).

Even if passivation is performed, the external quantum efficiency (EQE) is not uniform at a low current density because there is an influence due to a defect.

Due to the influence of non-uniform external quantum efficiency (EQE), it is difficult to control luminance at a low current density.

The difference in efficiency is because the number of carriers that will act as radial recombination is insufficient compared to the loss due to defect when the effect of non-radiative recombination by defect exists. It happens.

Therefore, as the influence of the side wall defect, which is the most important cause of the external quantum efficiency (EQE) drop, on the device is less, the external quantum efficiency (EQE) can be uniform.

If the influence of side wall defects can be controlled, the Micro-LED will be able to operate evenly at low luminance.

13 is a diagram showing a change in the influence of a defect due to side wall etching.

Referring to FIG. 13, it is assumed that an error between defects of a sample by Mesa etching is 1% or 2%, and efficiency reduction due to defects after passivation is uniform. If it is assumed that it is reduced, it can be seen that the non-uniformity due to the error of the defect decreases.

In the case of simply performing side wall passivation, the non-uniformity due to errors occurring in defects in the sample is maintained at 1% or 2%.

However, if a portion etched with a side wall pattern induces uniform degradation due to defects and dangling bonds due to leakage current, non-uniformity is caused. It can be seen that it decreases.

In the case of super low current density, the passivation treatment reduces the defect by 10% from 10000 to 1000, but the error is still maintained at 1% or 2%.

However, it can be seen that when the side wall is etched, the defects increase by 1000, but the error decreases to 0.5% or 1%, which is half of that.

In the case of low current density, the passivation treatment reduces the defect by 50% from 10000 to 5000, but the error is still maintained at 1% or 2%.

However, it can be seen that when the side wall is etched, the defects increase by 1000, but the error slightly decreases to 0.833% or 1.666%.

According to this principle, the error rate can be reduced according to the degree to which the influence of the original defect is reduced by passivation.

Although the above has been described with reference to embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention described in the following claims. I will be able to.

10: micro light emitting diode
110: substrates
130: n-type metal electrode
150: p-type metal electrode
170: reflector
200: first semiconductor layer
210: template layer
230: n-type nitride layer
300: second semiconductor layer
310: super lattice layer
320: active layer
330: electron blocking layer
340: p-type nitride layer
350: p+ type nitride layer
360: transparent electrode layer
400: passivation layer

Claims (13)

Board;
A first semiconductor layer on the substrate and on which nitride is deposited;
A second semiconductor layer positioned on the first semiconductor layer and emitting light by depositing a plurality of nitride layers; And
A passivation layer including an insulating material deposited on a sidewall of the second semiconductor layer and having a specific pattern formed on one side thereof by etching,
The specific pattern formed on the passivation layer is a micro light emitting diode, characterized in that it has a vertical stripe shape.
The method of claim 1, wherein the first semiconductor layer,
A template layer positioned on the substrate and doped with gallium nitride (GaN); And
An n-type nitride layer on which an n-type gallium nitride (n-GaN) doped with silicon (Si) is deposited and disposed on the template layer.
The method of claim 1, wherein the second semiconductor layer,
A superlattice layer doped with silicon of 30 cycles made of gallium nitride (GaN) and indium gallium nitride (AlGaN), positioned on the first semiconductor layer;
An active layer disposed on the superlattice layer and including a plurality of multiple quantum wells including an indium gallium nitride (AlGaN) well and a gallium nitride (GaN) barrier;
An electron blocking layer disposed on the active layer and on which aluminum gallium nitride (AlGaN) doped with magnesium (Mg) is deposited;
A p-type nitride layer on which a p-type gallium nitride (p-GaN) doped with magnesium (Mg) is deposited on the electron blocking layer;
A p+-type nitride layer on which a p+-type gallium nitride (p ⁺ -GaN) doped with magnesium (Mg) is deposited on the p-type nitride layer; And
A micro light emitting diode comprising; a transparent electrode layer positioned on the p+ type nitride layer and on which indium tin oxide (ITO) is deposited.
The method of claim 1, wherein the passivation layer,
A micro light-emitting diode, characterized in that produced by depositing silicon dioxide (SiO ₂ ) on one sidewall of the second semiconductor layer.
The method of claim 1, wherein the passivation layer,
After the aluminum oxide (Al ₂ O ₃ ) layer is disposed, silicon dioxide (SiO ₂ ) is deposited to generate a micro light-emitting diode.
delete The method of claim 1, wherein the specific pattern of the passivation layer,
Micro light-emitting diode, characterized in that at least one stripe shape.
The method of claim 1, wherein the specific pattern of the passivation layer,
Micro light-emitting diode, characterized in that formed by extending from the transparent electrode layer to the super lattice layer.
The method of claim 1, wherein the specific pattern of the passivation layer,
Micro light-emitting diode, characterized in that formed by extending from the transparent electrode layer to the active layer.
The method of claim 1, wherein the specific pattern of the passivation layer,
Micro light-emitting diode, characterized in that formed by extending from the transparent electrode layer to the electron blocking layer.
The method of claim 1, wherein the specific pattern of the passivation layer,
A micro light-emitting diode, characterized in that it is formed by extending from the transparent electrode layer to the p-type nitride layer.
The method of claim 1, wherein the specific pattern of the passivation layer,
A micro light emitting diode, characterized in that it is formed by extending from the transparent electrode layer to the p+ type nitride layer.
The method of claim 1, wherein the specific pattern of the passivation layer,
Micro light-emitting diode, characterized in that formed in the form of an equilateral trapezoid.

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