KR102142345B1 - Liquid Crystal Display - Google Patents

Abstract

The present invention relates to a liquid crystal display device.
The liquid crystal display according to the present invention is connected to the odd common line for supplying the first common voltage or the reference common voltage, the second common voltage or the good common line for supplying the reference common voltage, the odd common line and the first pixel and A third electrode connected to the odd common electrode providing the first common voltage to the fourth pixel positioned diagonally with the first pixel and the even common line, and positioned diagonally with the second pixel and the second pixel And an excellent common electrode that provides the second common voltage to the pixel.

Description

Liquid crystal display device

The present invention relates to a liquid crystal display device.

A liquid crystal display (Liquid Crystal Display) is a liquid crystal panel consisting of a plurality of liquid crystal cells arranged in the form of a mattress and a plurality of control switches for switching a pixel voltage to be supplied to these liquid crystal cells, a backlight unit (Back Light) Unit) controls the amount of light transmitted and displays the desired image on the screen.

In order to prevent the deterioration of the liquid crystal generated when an electric field in one direction is applied to the liquid crystal cell for a long time, such a liquid crystal display device includes a frame inversion method, a line inversion method, and a column inversion method. Various inversion methods such as (Column Inversion) or Dot Inversion are used.

The frame inversion method inverts the polarity of the data signal supplied to the liquid crystal cells whenever the frame is changed. The dot inversion method inverts the polarity of the data signal supplied to the liquid crystal cells in a dot unit and inverts the frame unit. In the line inversion method, the polarity of the data signal supplied to the liquid crystal cells is inverted in units of horizontal lines, and inverted in units of frames. The column inversion method inverts the polarity of the data signal supplied to the liquid crystal cells in units of columns (vertical lines) and inverts each frame.

In general, the dot inversion method is excellent in display quality, but has a problem of high power consumption. Also, when using dot inversion, since the polarities of adjacent pixels are all opposite, light leakage may occur due to a voltage difference between adjacent pixels between the boundary surfaces of the pixels in the horizontal line. In addition, in order to use the dot inversion method, a common voltage of two polarities must be provided in one frame. For this, two common electrodes are required for one pixel, and at this time, a black matrix necessary for shielding the area between the common electrodes is used. As a result, a reduction in openings occurs.

The present invention is to provide a liquid crystal display device capable of implementing a dot inversion method while reducing power consumption.

Also, the present invention is to provide a liquid crystal display device capable of preventing light leakage from occurring in a boundary region between pixels.

In addition, the present invention is to provide a liquid crystal display device capable of implementing a dot inversion method without reducing an opening.

The liquid crystal display according to the present invention is connected to the odd common line for supplying the first common voltage or the reference common voltage, the second common voltage or the good common line for supplying the reference common voltage, the odd common line and the first pixel and A third electrode connected to the odd common electrode providing the first common voltage to the fourth pixel positioned diagonally with the first pixel and the even common line, and positioned diagonally with the second pixel and the second pixel And an excellent common electrode that provides the second common voltage to the pixel.

While the present invention provides a common voltage in a line inversion method, pixels can be driven in the same way as a dot inversion method.

Since the present invention removes the voltage difference between the pixels after charging the data to the pixels, it is possible to improve the light leakage phenomenon occurring in the boundary region of the pixels.

Since the present invention shields the data line using a common electrode, the black matrix can be omitted, and accordingly, the opening can be prevented from being reduced.

1 is a view showing a liquid crystal display device according to the present invention.
2A is a plan view showing a thin film array substrate according to a first embodiment.
Figure 2b is a plan view showing the shape of a common electrode according to the present invention.
3 is a view showing a connection relationship between a common line and a common electrode according to the first embodiment.
4 is a view for explaining the reduction of the aperture ratio by the conventional common electrode structure.
5 is a plan view showing a thin film array substrate according to a second embodiment.
6 is a view showing a connection relationship between a common line and a common electrode according to a second embodiment.
7 is a plan view showing a thin film array substrate according to a second embodiment.
8 is a view showing a connection relationship between a common line and a common electrode according to the second embodiment.
9 and 10 are views showing a driving method according to the first embodiment.
11A and 11B are diagrams illustrating charging and maintenance of a data voltage according to the present invention.
12 and 13 are views showing a driving method according to the second embodiment.
14 is a view showing a driving method according to the third embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description is omitted.

1 is a view showing a liquid crystal display device according to the present invention.

Referring to FIG. 1, the liquid crystal display device according to the present invention includes a liquid crystal panel 10, a timing controller 20, a DC/DC converter 30, a gate signal generator 40, a gate driver 50 and data. It includes a driving unit 60.

The liquid crystal panel 10 includes a thin film transistor array substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter is formed, and a liquid crystal layer is formed between the thin film transistor array substrate and the color filter substrate. In the thin film transistor array substrate of the liquid crystal panel 10, pixels P defined by the gate lines GL and the data lines DL are arranged in a matrix form.

The pixel P includes a thin film transistor T for supplying the data signal provided from the data line DL to the pixel electrode by responding to the gate signal provided through the gate line GL. To this end, the gate electrode of the thin film transistor T is connected to the gate line GL and the drain electrode is connected to the data line DL.

The timing controller 20 reads the data stored in the memory 80, and various signals for driving the operation signal and the liquid crystal panel 10 for the operation of the DC-DC converter (hereinafter, DC-DC converter) 30 Control signal is output. That is, the timing controller 20 uses the synchronization signal (Hsync, Vsync), the data enable signal (Data Enable), and the clock signal (CLK) input through the interface unit 70, the data driver 60 and the data driver The control signal for controlling (60) is output.

The DC/DC converter 30 receives the voltage from the system through the connector to output driving voltages Vcc and Vdd, and outputs gate low voltage and gate high voltage according to the operation signal of the timing controller 20, and gamma The reference voltage Vref and the first and second common voltages Vcom_odd and Vcom_even are output.

The gate signal generator 40 uses the gate low voltage and the gate high voltage provided from the DC/DC converter 30 to generate a gate low signal VGL according to the clock signal CLK received from the timing controller 20. And a gate high signal VGH.

The gate driver 50 receives the gate high signal VGH and the gate low signal VGL to generate scan pulses, and sequentially supplies the scan pulses to each gate line G of the liquid crystal panel 10.

The data driver 60 receives a corrected video signal that is a digital signal from the timing controller 20, converts it into a corrected data signal that is an analog signal, and converts the corrected data signal to each data line D of the liquid crystal panel 10. To supply.

The memory 80 stores the size of the liquid crystal panel 10, resolution conversion information, image data conversion information, driving frequency and driving timing information of the timing controller 20, and the like. In addition, when the input/output control clock is input, the memory 80 supplies stored driving information and image data modulation information to the timing controller 20.

2 is a plan view showing a thin film array substrate according to a first embodiment.

The pixel P is defined as an area where the gate lines GL arranged horizontally and the first or second data lines DL2 arranged vertically intersect each other.

The thin film transistor TFT faces the gate electrode G branched from the gate line GL, the yaw-shaped drain electrode D branched from the second data line DL, and the drain electrode D. It includes a source electrode (S).

In particular, the position of the thin film transistor T formed in the data line DL varies for each horizontal line. For example, the thin film transistor T connected to the first data line DL1 is formed in the odd-numbered pixels in the first horizontal line and in the even-numbered pixels in the second horizontal line. In addition, the thin film transistor T connected to the second data line DL2 is formed in the even-numbered pixel in the first horizontal line and in the odd-numbered pixel in the second horizontal line.

The pixel electrode 7 is formed in a plurality of branched forms crossing the common branch electrodes 112 and 122, and is connected to the source electrode 15b to receive a data voltage. The pixel electrode 7 may be formed by using a transparent conductive metal having excellent light transmittance as a material, such as indium-tin-oxide (ITO).

The common line includes an odd common line (Vcom_o) and an excellent common line (Vcom_e). The odd common line Vcom_o is formed on the horizontal line of the odd row, and the superior common line Vcom_e is formed on the horizontal line of the even row. The odd common line Vcom_o provides the first common voltage Vcom_odd and the reference common voltage Vcom_ref, and the good common line Vcom_e provides the second common voltage Vcom_even and the reference common voltage Vcom_ref. The first common voltage Vcom_odd and the second common voltage Vcom_even may be voltages having different polarities or voltages having the same polarity, but may have different voltage levels. The reference common voltage Vcom_ref may have a magnitude corresponding to an intermediate value between the first common voltage Vcom_odd and the second common voltage Vcom_even. The common lines Vcom_o and Vcom_e may be integrally formed using the same material as the gate lines GL1 and GL2 and the gate electrode G.

The odd common electrode 100a provides a common voltage received from the odd common line Vcom_o to two pixels formed in different columns. To this end, the odd common electrode 100a includes an odd vertical common electrode 101a, first and second odd horizontal common electrodes 110a and 120a, and first and second odd odd branch common electrodes 112a and 122a.

The odd vertical common electrode 101a is formed on the boundary surface of pixels formed on two adjacent horizontal lines. The first odd horizontal common electrode 110a extends in one direction from the odd vertical common electrode 101a, and the second odd horizontal common electrode 120a is the first odd horizontal common electrode 110a from the odd vertical common electrode 101a. ). Therefore, the common voltage supplied from the odd common line Vcom_o is simultaneously supplied to pixels located in diagonal directions with each other in adjacent horizontal lines.

The first and second odd-numbered common electrodes 112a and 122a branch from the first and second odd-numbered horizontal common electrodes 110a and 120a, respectively, to the pixel region.

Likewise, the superior common electrode 100b provides the common voltage received from the superior common line Vcom_e to two pixels formed in different columns. To this end, the superior common electrode 100b includes a superior vertical common electrode 101b, first and second superior vertical common electrodes 110b and 120b, and first and second superior branch common electrodes 112b and 122b. The first and second superior horizontal common electrodes 110b and 120b may be formed in opposite directions to the first and second odd horizontal common electrodes 110a and 120a.

The odd common electrode 100a is connected to the odd common line Vcom_o through the first contact hole 3a, and the superior common electrode 100b is connected to the superior common line Vcom_e through the second contact hole 3b. do.

As a result, in the first embodiment, the connection structure between the odd common line and the odd common electrode and the connection structure between the superior common line and the superior common electrode are the same as the schematic diagram of FIG. 3.

The odd common electrode 100a connected to the i(i is a natural number) odd common line Vcom_o is the (j-1) of the (2i-1) horizontal line (j is a natural number of 2 or more) th pixel and the 2i horizontal It is connected to the j-th pixel of the line. The even common electrode 100b connected to the i-th common line is connected to the (j+1)th pixel of the 2i horizontal line and the j-th pixel of the second (2i+1) horizontal line.

Due to the above structure, the odd common electrode 100a provides a common voltage to two pixels formed on different horizontal lines. At this time, the pixels connected to the odd common electrode 100a are positioned in the diagonal direction. For example, the (j-1)th pixel of the first horizontal line and the jth pixel of the second horizontal line are simultaneously provided with a common voltage using the same common electrode. That is, when the first common voltage Vcom_odd is provided as the first odd common line Vcom_o1, the first common voltage Vcom_odd is provided to pixels positioned diagonally to each other among the pixels of the two horizontal lines.

Similarly, the rainwater common electrode 100b is formed on different horizontal lines, and provides a common voltage to pixels located in diagonal directions with each other. Therefore, when the second common voltage Vcom_even is provided as the first good common line Vcom_e1, the pixels located in the diagonal direction of each other among the pixels of the two horizontal lines are provided at the second common voltage Vcom_even. A second common voltage Vcom_even is provided to pixels other than the pixels connected to the odd-numbered common line Vcom_o1.

The first and second common voltages Vcom_odd and Vcom_even may be voltages of different polarities. That is, pixels in adjacent columns and adjacent rows are all driven in dot inversion, which are provided with common voltages of different polarities.

At this time, since one odd common line Vcom_o or a superior common line Vcom_e is formed in one horizontal line, only one type of common voltage is provided to each horizontal line. That is, the present invention can reduce the number of transitions since it is not necessary to change the polarity of the common voltage for each horizontal period in order to implement dot inversion. Therefore, power consumption can be reduced as compared to the conventional dot inversion driving.

The odd vertical common electrode 101a and the superior vertical common electrode 101b are formed at positions overlapping the first data line DL1 or the second data line DL2, thereby improving the aperture ratio by acting as a black matrix. Can.

In the conventional pixel structure for driving the dot inversion, as shown in FIG. 4, the first common electrode Vcom_p and the second common electrode Vcom_n are separated. The first common electrode Vcom_p provides a common voltage of positive polarity, and the second common electrode Vcom_n provides a common voltage of negative polarity. In order to use the dot inversion method, since a common voltage of two polarities must be provided in one frame, the common electrode is physically separated. At this time, in order to improve the light leakage phenomenon, a black matrix (BM) is formed. Since the black matrix (BM) is formed to a certain size or more due to a process margin, it may also cause a decrease in the aperture ratio of the pixel.

On the other hand, since the present invention does not separate the common electrode within one pixel, the black matrix BM is omitted, and the vertical common electrodes 101a and 101b can be used to replace the role of the black matrix BM. . Accordingly, it is possible to swing the common voltage while preventing the aperture ratio from being lowered due to the conventional black matrix (BM).

5 is a view showing a thin film array substrate according to a second embodiment, and FIG. 6 is a schematic diagram showing a connection relationship between a common line and a common electrode shown in FIG. 5.

In the thin film array substrate according to the second embodiment, the odd common electrode 100a is connected to the odd common line Vcom_o through the contact hole 3a at the central position of the vertical common electrode 101a. In addition, the superior common electrode 100b is connected to the superior common line Vcom_e through the contact hole 3b at the central position of the vertical common electrode 101b.

Accordingly, in the second embodiment, the odd common electrode Vcom_oi connected to the i-th common line is the (2i-2) (i is a natural number of 2 or more) horizontal line (j-1) (j is a natural number of 2 or more) )Th pixel and the jth pixel of the (2i-1)th horizontal line. The even common electrode 100b connected to the i-th common line Vcom_ei is connected to the (j+1) th pixel of the (2i-1) horizontal line and the j-th pixel of the 2i horizontal line.

7 is a view showing a thin film array substrate according to a third embodiment, and FIG. 8 is a schematic view showing a connection relationship between a common line and a common electrode shown in FIG. 7.

In the third embodiment, the odd common electrode 100a is connected to the odd common line Vcom_o through the contact hole 3a in the horizontal common electrode 110a. In addition, the superior common electrode 100b is connected to the superior common line Vcom_e through the contact hole 3b at the central position of the vertical common electrode 101b. Accordingly, pixels connected to the odd common line and the superior common line of the same sequence are formed on the same horizontal line.

That is, in the third embodiment, the odd common electrode 100a connected to the i-th odd common line Vcom_oi includes the (j-1)th pixel of the (2i-1) horizontal line and the jth pixel of the 2i horizontal line. Is connected to. The even common electrode 100b connected to the i-th common line Vcom_ei is connected to the j-th pixel of the (2i-1) horizontal line and the j+1-th pixel of the 2i horizontal line.

Looking at the driving method of the liquid crystal display device including the above embodiment is as follows.

9 is a schematic diagram of a thin film array substrate according to a second embodiment, and FIG. 10 shows an operation timing of signals driving the thin film array substrate shown in FIG. 8.

Referring to FIGS. 9 and 10, the process of charging the data voltage to the pixels will be described as follows.

The first to fifth gate pulses G1 to G5 indicate the order of the gate pulses, and the first to third odd common lines Vcom_o1 to Vcom_o3 and the first to third excellent common lines Vcom_e1 to Vcom_e3 are respectively. The order of the odd common line (Vcom_o) and the excellent common line (Vcom_e) is shown. The first to tenth pixels P1 to P10 represent pixels of any two columns in the first to fifth horizontal lines.

During the first horizontal period t1, the first pixel P1 is turned on by receiving the first gate pulse G1 from the first gate line GL. At the same time, the first pixel P1 receives the second common voltage Vcom_even from the first even common line Vcom_e1, and receives the high potential data voltage from the first data line DL1. Accordingly, the first pixel P1 is charged with a potential corresponding to the difference between the high potential data voltage and the second common voltage Vcom_even.

During the second horizontal period t2, the third and fourth pixels P3 and P4 are turned on by receiving the second gate pulse G2 from the second gate line GL.

The third pixel P3 is charged by receiving the first common voltage Vcom_odd from the second odd common line Vcom_o2 and receiving the low potential data voltage from the second data line DL2. The fourth pixel P4 is charged by receiving the second common voltage Vcom_even from the first even common line Vcom_e1 and receiving the high potential data voltage from the first data line DL1.

During the third horizontal period t3, the fifth and sixth pixels P5 and P6 are turned on by receiving the third gate pulse G3 from the third gate line GL3.

The fifth pixel P5 is charged by receiving the second common voltage Vcom_even from the second even common line Vcom_e2 and receiving the high potential data voltage from the first data line DL1. The sixth pixel P6 is charged by receiving the first common voltage Vcom_odd from the second odd common line Vcom_o2 and receiving the low potential data voltage from the second data line DL2.

At this time, the first good common line Vcom_e1 provides the reference common voltage Vcom_ref. In addition, the second odd common line Vcom_o2 provides the reference common voltage Vcom_ref from the first common voltage Vcom_odd when the third horizontal period t3 ends.

As such, each odd common line Vcom_o and the superior common line Vcom_e provide a first common voltage Vcom_odd or a second common voltage Vcom_even during a horizontal period in which a data voltage is provided to connected pixels, The reference common voltage Vcom_ref is provided outside the period in which the data voltage is provided. The process of charging and maintaining data in the pixel using the reference common voltage Vcom_ref is as follows.

11A is a diagram illustrating an electric field formed in the fourth pixel P4 of the second horizontal period t2. If the second common voltage Vcom_even is 0V and the data voltage provided to the fourth pixel P4 is 2V, the ideal electric field inside the fourth pixel P4 is 2V. However, while the second common voltage Vcom_even is provided to the fourth pixel P4, since the first common voltage Vcom_odd is provided to the adjacent third pixel P3, the fourth common voltage Vcom_odd is applied to the fourth pixel P4. In the boundary region of the three pixels P3, an electric field of 8V is formed. As such, an abnormal electric field due to the influence of the electric field of adjacent pixels may induce light leakage in the boundary region between pixels.

To improve this, after providing the first common voltage Vcom_odd or the second common voltage Vcom_even to each pixel of each horizontal line, a reference common voltage Vcom_ref is provided.

For example, as shown in FIG. 11B, the fourth pixel P4 is provided with a reference common voltage Vcom_ref of 5V after the second horizontal period t2 ends, and the third pixel P3 is After the fourth horizontal period t4 ends, a reference common voltage Vcom_ref is provided. Accordingly, since the same electric field is formed over the entire area of the fourth pixel P4, the light leakage phenomenon occurring at the boundary between the pixels can be improved.

12 and 13 are diagrams for describing charging of a data voltage to pixels according to a second embodiment. At this time, FIG. 12 has the same pixel structure as the above-described embodiment. In the second embodiment, a detailed description of the same operation as the above-described embodiment will be omitted.

The first gate pulse G1 is provided during the first and second horizontal periods t1 and t2. The first gate pulse G1 is for turning on the pixels of the first horizontal line during the second horizontal period t2, but is supplied for two horizontal periods to ensure stable scan timing.

The first even common line Vcom_e1 is connected to the first and fourth pixels P1 and P4, and the first and fourth pixels P1 and P4 are data in the second and third horizontal periods t2 and t3. Voltage is provided. The second common voltage supplied to the first good common line Vcom_e1 is provided in the second and third horizontal periods t2 and t3, but the second common voltage Vcom_even is provided to provide a stable second common voltage Vcom_even. ) Can increase the delivery timing.

For example, the second common voltage supplied to the first even common line Vcom_e1 may be maintained for the first to third horizontal periods t1 to t3 as shown in the drawing.

Similarly, the first common voltage Vcom_odd supplied to the second odd common line Vcom_o2 may be maintained for the second to fourth horizontal periods t2 to t4.

14 is a timing diagram showing waveforms showing a method of driving the thin film array substrate of the third embodiment shown in FIG. 7. In the third embodiment, a detailed description of the same operation as the above-described embodiments will be omitted.

In the thin film array substrate of the third embodiment shown in FIG. 7, pixels connecting to the odd common line and the superior common line of the same sequence are formed on the same horizontal line.

Therefore, the embodiment shown in FIG. 7 is the same sequence number, for example, the first common voltage Vcom_odd and the second common voltage Vcom_even applied to the i-th odd common line Vcom_oi and the i-th excellent common line Vcom_ei, respectively. You can set the timing of the same.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

Claims (15)

An odd common line that supplies a first common voltage or a reference common voltage;
A good common line supplying a second common voltage or the reference common voltage;
An odd common electrode connected to the odd common line and providing the first common voltage to a first pixel and a fourth pixel positioned diagonally with the first pixel; And
And an excellent common electrode connected to the excellent common line and providing the second common voltage to a second pixel and a third pixel positioned diagonally with the second pixel.
The odd common electrode connected to the i-th (i is a natural number equal to or greater than 1) odd-numbered common line includes: Provides common voltage,
The even common electrode connected to the i-th common line provides the second common voltage to the j-th pixel of the (2i-1) horizontal line and the j+1-th pixel of the 2i horizontal line,
And the timing at which the first common voltage is applied to the i-th common line and the timing at which the second common voltage is applied to the i-th common line is synchronized.
delete delete delete According to claim 1,
A first data line providing a first data voltage to the second and third pixels; And
And a second data line providing a second data voltage to the first and fourth pixels.
The method of claim 5
The odd (excellent) common electrode,
An odd (excellent) vertical common electrode positioned between the first (second) pixel and the fourth (third) pixel and formed in a vertical direction;
A first odd (excellent) horizontal common electrode extending in the direction of the first (second) pixel from the vertical common electrode; And
And a second odd (excellent) horizontal common electrode extending in the direction of the fourth (third) pixel from the vertical common electrode.


The method of claim 6,
The horizontal common electrode is spaced apart from the adjacent vertical common electrode, a liquid crystal display device.
The method of claim 6,
And the odd (excellent) common line and the odd (excellent) horizontal common electrode are connected through a contact hole.
The method of claim 6,
And the odd (excellent) common line and the odd (excellent) vertical common electrode are connected through a contact hole.
According to claim 1,
The first common voltage and the second common voltage have a different potential.
The method of claim 10,
The reference common voltage is an average voltage level of the first and second common voltages.
According to claim 1,
The odd (excellent) common line is characterized in that the first common voltage (second common voltage) is provided while turning on the thin film transistors of the first and fourth pixels (second and third pixels). Liquid crystal display device.
The method of claim 12,
The second and third pixels receive a first data voltage through a first data line while the second common voltage is provided,
The first and fourth pixels are provided with a second data voltage through a second data line while the first common voltage is provided.
The method of claim 12,
The odd (excellent) common line is a liquid crystal display device characterized in that the reference common voltage is provided while turning off the thin film transistors of the first and fourth pixels (second and third pixels). According to claim 1,
During the i-th horizontal period, the first and second pixels are turned on by receiving the i-th gate pulse,
During the i+1 horizontal period following the i-th horizontal period, the third and fourth pixels are turned on by receiving the i+1 gate pulse,
The timing at which the first common voltage is applied to the i-th odd common line and the timing at which the second common voltage is applied to the i-th common common line is a sum of the i-th horizontal period and the i+1 horizontal period. A liquid crystal display device, characterized in that.

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