KR102148486B1 - Thin film transistor array substrate for display device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate for a display device and a method of manufacturing the same. The disclosed invention comprises an active layer formed on the substrate and comprising a source region, a channel region, and a drain region; A gate insulating layer and a gate electrode stacked on the channel region of the active layer; An interlayer insulating film formed on the entire surface of the substrate including the gate electrode and exposing the source region and the drain region of the active layer; A source electrode formed on the interlayer insulating layer, overlapping the gate electrode, and in contact with the source region or a drain electrode in contact with the drain region; And a pixel electrode formed on the interlayer insulating layer including the drain electrode and electrically connected to the drain electrode.

Description

A thin film transistor array substrate for a display device, and a manufacturing method thereof {THIN FILM TRANSISTOR ARRAY SUBSTRATE FOR DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a thin film transistor for a display device, and more particularly, to a thin film transistor array substrate for a display device capable of improving the reliability of an oxide thin film transistor having an optical reliability problem in a display device, and a method of manufacturing the same.

TV (Television) products are the biggest application target in the rapidly growing flat panel display market. Currently, a liquid crystal display (LCD) is the main focus as a TV panel, and many studies are being conducted for an organic light emitting display to be applied to a TV.

The direction of the current TV display technology is focused on the main items required by the market. The requirements in the market include large-sized TV or DID (Digital Information Display), low price, high quality (video expression, high resolution, brightness, contrast ratio). , New re-enactment).

In order to meet these requirements, a thin film transistor (TFT) is required to be applied as a display switching and driving device having excellent performance without increasing cost while increasing the size of a substrate such as glass.

Therefore, future technology development should focus on securing a TFT manufacturing technology capable of manufacturing a display panel with excellent performance at a low price to meet this trend.

A typical amorphous silicon thin film transistor (a-Si TFT) as a driving and switching device of a display is a device that is widely used as a device that can be uniformly formed on a large substrate exceeding 2m at low cost.

However, according to the trend of increasing the size and high quality of displays, the device performance is also required to have high performance, so the existing amorphous silicon thin film transistor (a-Si TFT) with a mobility of 0.5 cm ² /Vs is expected to reach its limit.

Therefore, there is a need for a high-performance TFT and a manufacturing technology having a higher mobility than a-Si TFT. In addition, as the a-Si TFT continues to operate as its greatest weakness, the device characteristics continue to deteriorate, resulting in a reliability problem in which initial performance cannot be maintained.

This is the main reason why a-Si TFT is difficult to be applied as an Organic Luminescene Emitted Diode (OLED) that operates by continuously passing current rather than an AC driven LCD.

Poly-Si TFT, which has much higher performance than a-Si TFT, has a high mobility of tens to hundreds of cm ² /Vs, so it can be applied to high-definition displays that were difficult to realize in conventional a-Si TFTs. In addition to having the performance that can be achieved, there is very little problem of deterioration of device characteristics due to operation compared to a-Si TFT. However, in order to manufacture a poly-Si TFT, a larger number of processes are required than that of a-Si TFT, and other additional equipment investments must also be preceded.

Therefore, p-Si TFT is suitable to be applied to products such as high-definition display or OLED, but in terms of cost, it is inferior to existing a-Si TFT, so its application is bound to be limited.

In particular, in the case of p-Si TFT, it is difficult to apply it to TV products because the manufacturing process using large substrates exceeding 1m has not been realized until now due to technical problems such as manufacturing equipment limitations or poor uniformity. It is becoming a factor that makes it difficult for p-Si TFT to be easily established in the market.

Therefore, there is a greater demand than ever for a new TFT technology that can take advantage of both the advantages of a-Si TFT (large size, low price, and uniformity) and the advantages of poly-Si TFT (high performance, reliability). There is progress, and an oxide semiconductor is a representative example of this.

In the case of such an oxide semiconductor, the mobility is higher than that of an amorphous silicon (a-Si) TFT, and the manufacturing process is simple and the manufacturing cost is lower than that of a poly-Si TFT. It has high value for use as (LCD) and organic electroluminescent devices (OLED).

From this point of view, a structure of a thin film transistor array substrate according to the prior art using an oxide semiconductor will be described with reference to FIGS. 1 and 2 as follows.

1 is a schematic plan view of a thin film transistor array substrate having a TFT on color filter (TFT) structure according to the prior art.

2 is a plan view showing an enlarged portion A of FIG. 1.

As shown in Figs. 1 and 2, a TFT array substrate 10 having a TFT-on-color filter structure according to the prior art has a gate wiring 23 formed in one direction on one surface of a substrate (not shown). and; A data line 29 crossing the gate line 23 to define a pixel area; An oxide thin film transistor (T) formed at an intersection of the gate line (23) and the data line (29); A large-area common electrode 35 formed in the pixel area of the substrate; It is formed in the pixel region, and includes a plurality of pixel electrodes 41 electrically connected to the drain electrode 29b of the thin film transistor T.

Here, the source electrode 29a extends from the data line 29 and is spaced apart from the source electrode 29a based on the gate electrode 23a to form a drain electrode 29b.

At this time, the source electrode 29a and the drain electrode 29b do not overlap with the gate electrode 23a and are spaced apart by a predetermined width w.

External light is transmitted between the source electrode 29a and the drain electrode 29b and the gate electrode 23a spaced apart by a predetermined width w to penetrate the channel region (not shown) of the active layer 19.

A thin film transistor array substrate 10 having a TFT on color filter structure according to the prior art will be described in detail with reference to FIG. 3.

3 is a cross-sectional view taken along line II-II of FIG. 1 and is a schematic cross-sectional view of a thin film transistor array substrate according to the prior art.

Referring to FIG. 3, in a thin film transistor array substrate 10 having a TFT on color filter structure, a black matrix 13 is formed on a substrate 11, and the entire substrate including the black matrix 13 is Red, green, and blue color filter layers 15 are formed, and a buffer layer 17 is formed on the color filter layer 15.

In addition, on the buffer layer 17 above the black matrix 13, an active layer 19 comprising a channel region 19c and a source region 19a and a drain region 19b formed on both sides of the channel region 19c is formed. Has been.

In addition, a gate insulating film 21 and a gate electrode 23a are stacked on the channel region 19c of the active layer 19, and an interlayer insulating film 25 is formed on the entire surface of the substrate including the gate electrode 23a. .

Further, a source region contact hole (not shown) and a drain region contact hole (not shown) exposing the source region 19a and the drain region 19b, respectively, are formed in the interlayer insulating layer 25.

A source electrode 29a and a drain electrode in contact with the source region 19a and the drain region 19b through the source region contact hole (not shown) and the drain region contact hole (not shown) on the interlayer insulating layer 25 (29b) is formed. At this time, the source electrode 29a and the drain electrode 29b do not overlap with the gate electrode 23a and are spaced apart by a predetermined width w. In this way, external light is transmitted between the source electrode 29a and the drain electrode 29b and the gate electrode 23a spaced apart by a predetermined width w to penetrate into the channel region (not shown) of the active layer 19. A phenomenon occurs.

Further, a passivation film 31 exposing the drain electrode 29b is formed on the interlayer insulating film 25 including the source electrode 29a and the drain electrode 29b.

Further, a large-area common electrode 35 is formed on the passivation layer 31, and a planarization layer 37 is formed on the passivation layer 31 including the common electrode 35.

A drain contact hole (not shown) exposing the drain electrode 29b is formed in the planarization layer 37, and is electrically connected to the drain electrode 29b on the planarization layer 37, and the common electrode A plurality of pixel electrodes 41 spaced apart from each other by a predetermined interval to face 35 are formed.

4 is a cross-sectional view schematically illustrating a state in which external light is transmitted to a channel region of an active layer through a gap between a source electrode, a drain electrode, and a gate electrode through a thin film transistor array substrate according to the prior art.

Referring to FIG. 4, the source electrode 29a and the drain electrode 29b do not overlap with the gate electrode 23a and are spaced apart by a predetermined width w.

When external light is transmitted between the source electrode 29a and the drain electrode 29b and the gate electrode 23a spaced apart by a predetermined width w, external light is transmitted through the channel region of the active layer 19 ( (Not shown) occurs.

As described above, according to the conventional thin film transistor array substrate having a TOC structure, most of the external light is reflected by the gate electrode 23a, but some of the source electrode 29a and the source electrode 29a spaced apart by a predetermined width w A phenomenon occurs that penetrates between the drain electrode 29b and the gate electrode 23a and penetrates into the channel region (not shown) of the active layer 19.

Accordingly, since light penetration between the source electrode 29a and the drain electrode 29b and the gate electrode 23a is not completely blocked, reliability is adversely affected. In particular, in the case of an oxide semiconductor thin film transistor, since it is very sensitive to light, the problem of blocking the penetration of light is very important.

The present invention is to solve the problems of the prior art, and an object of the present invention is to form a source electrode extending from a data line or a drain electrode connected to the pixel electrode on the gate electrode so as to completely overlap the gate electrode, thereby forming a channel of the active layer. A thin film transistor array substrate for a display device capable of securing light reliability by completely blocking light transmitted through a region, and a method of manufacturing the same.

In order to achieve the above object, a thin film transistor array substrate for a display device according to the present invention is formed on a substrate and includes an active layer including a source region, a channel region, and a drain region; A gate insulating layer and a gate electrode stacked on the channel region of the active layer; An interlayer insulating film formed on the entire surface of the substrate including the gate electrode and exposing the source region and the drain region of the active layer; A source electrode formed on the interlayer insulating layer, overlapping the gate electrode, and in contact with the source region or a drain electrode in contact with the drain region; And a pixel electrode formed on the interlayer insulating layer including the drain electrode and electrically connected to the drain electrode.

A method of manufacturing a thin film transistor array substrate for a display device according to the present invention for achieving the above object comprises: forming an active layer comprising a source region, a channel region, and a drain region on the substrate; Stacking a gate insulating layer and a gate electrode on the channel region of the active layer; Forming an interlayer insulating film exposing the source region and the drain region of the active layer on the entire surface of the substrate including the gate electrode; Forming a source electrode and a drain electrode on the interlayer insulating layer to contact the source region and the drain region, and forming the source electrode or the drain electrode to overlap the gate electrode; And forming a pixel electrode electrically connected to the drain electrode on the interlayer insulating layer including the drain electrode.

A thin film transistor array substrate for a display device according to the present invention and a method of manufacturing the same include a source electrode extending from a data line or a drain electrode connected to the pixel electrode on the gate electrode to be completely overlapped on the gate electrode, thereby forming a channel region of the active layer. Light reliability can be secured by completely blocking the transmitted light.

In addition, the thin film transistor array substrate for a display device and the method of manufacturing the same according to the present invention improves light reliability by completely blocking light transmitted to the channel region of the active layer, thereby providing a high-resolution organic light emitting diode TV and a liquid crystal having a TOC structure. Applicable to display device products including display devices.

1 is a schematic plan view of a thin film transistor array substrate having a TFT on color filter (TFT) structure according to the prior art.
2 is a plan view showing an enlarged portion A of FIG.
3 is a cross-sectional view taken along line II-II of FIG. 1 and is a schematic cross-sectional view of a thin film transistor array substrate according to the prior art.
4 is a cross-sectional view schematically illustrating a state in which external light is transmitted to a channel region of an active layer through a gap between a source electrode, a drain electrode, and a gate electrode through a thin film transistor array substrate according to the prior art.
5 is a schematic plan view of a thin film transistor array substrate having a TFT on color filter structure according to an embodiment of the present invention.
6 is a plan view showing an enlarged portion B of FIG.
FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 5, and is a schematic cross-sectional view of a thin film transistor array substrate having a TFT on color filter structure according to the present invention.
8A to 8N are cross-sectional views illustrating a manufacturing process of a thin film transistor array substrate having a TFT on color filter.
9 is a schematic plan view of a thin film transistor array substrate having a TFT on color filter structure according to another embodiment of the present invention.
10 is a plan view showing an enlarged portion C of FIG.
FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 9 and is a schematic cross-sectional view of a thin film transistor array substrate having a TFT on color filter structure according to another embodiment of the present invention.
12 is a schematic cross-sectional view of a liquid crystal display device using a thin film transistor array substrate according to another embodiment of the present invention.
13 is a schematic cross-sectional view of an organic light emitting display device using a thin film transistor array substrate according to another embodiment of the present invention.
14 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention.

Hereinafter, a thin film transistor array substrate having a TFT on color filter structure according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a schematic plan view of a thin film transistor array substrate having a TFT on color filter structure according to an embodiment of the present invention.

6 is a plan view showing an enlarged portion B of FIG. 5.

5 and 6, a TFT array substrate 100 having a TFT on color filter structure according to the present invention includes a gate wiring 113 formed in one direction on one surface of the substrate 101 and the gate wiring. A gate electrode 113a extending from 113; A data line 121 crossing the gate line 113 to define a pixel area; A thin film transistor (T) formed at the intersection of the gate line 113 and the data line 121; A large-area common electrode 127 formed in the pixel area of the substrate; It is formed in the pixel region and includes a plurality of pixel electrodes 133 electrically connected to the drain electrode 121b of the thin film transistor T.

Here, a source electrode 121a extends from the data line 121 and is spaced apart from the source electrode 121a to form a drain electrode 121b. In this case, the drain electrode 121b overlaps the gate electrode 113a by a predetermined width X1. In addition, the width X1 of the drain electrode 121b overlapping the gate electrode 113a is formed to be equal to or greater than the line width of the gate electrode 113a.

In addition, one end of the source electrode 121a is formed so as not to coincide with or overlap with the edge portion of the gate electrode 113a.

Further, although not shown in the drawing, a black matrix (not shown) is formed under the gate electrode 113a, so that light incident from the lower portion is prevented from being transmitted to the channel region of the active layer 109.

Therefore, since the drain electrode 121b is completely overlapped with the gate electrode 113, light is not transmitted between the source electrode 121a and the drain electrode 121b and the gate electrode 113a, but is blocked. Since it cannot penetrate into the channel region (not shown) of the active layer 109, optical reliability is ensured.

The thin film transistor array substrate 100 having a TFT on color filter structure according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 7.

FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 5, and is a schematic cross-sectional view of a thin film transistor array substrate having a TFT on color filter structure according to the present invention.

Here, the thin film transistor array substrate 100 according to the exemplary embodiment of the present invention includes all of a driveable thin film transistor structure including a top gate and a bottom gate method.

The thin film transistor array substrate 100 according to the present invention is a driving element or a switching element of a flat panel display such as a liquid crystal display (LCD), an organic light emitting diode (OLED), or the like. , It can be applied to various electronic devices such as devices for configuring peripheral circuits of memory devices.

The substrate 101 may be made of silicon, glass, plastic or other suitable material.

Referring to FIG. 7, a thin film transistor array substrate 100 having a TFT on color filter structure is a black matrix 103 for blocking light from being transmitted to an area other than a pixel area on the substrate 101. Is formed, and a color filter layer 105 of red, green, and blue color is formed on the entire surface of the substrate including the black matrix 103, and a buffer layer 105 is formed on the color filter layer 105. 107) is formed. At this time, since the black matrix 103 is formed under the gate electrode 113a, light incident from the lower portion is prevented from being transmitted to the channel region of the active layer 109.

In addition, an active layer 109 comprising a channel region 109c and a source region 109a and a drain region 109b formed on both sides of the channel region 109c is formed on the buffer layer 107 above the black matrix 103 Has been. At this time, the active layer 109a is a layer for forming a channel through which electrons move between the source electrode 121a and the drain electrode 121b, and is a low temperature polysilicon (LTPS) or amorphous silicon. Instead of the (a-Si) material, a silicon (Si)-based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nano tube, and graphene are used.

At this time, as the oxide semiconductor, at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) And a material in which silicon (Si) is added to an oxide semiconductor including zinc (Zn). For example, the active layer 109 may be formed of indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to an indium zinc composite oxide (InZnO).

When the active layer 109 is made of SIZO, the composition ratio of the silicon (Si) atom content to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer is about 0.001% by weight (wt%) to It may be about 30 wt%. As the content of silicon (Si) atoms increases, the role of controlling electron generation becomes stronger, and the mobility may decrease, but the stability of the device may be improved.

Meanwhile, as the active layer 109, in addition to the above-described materials, a group I element such as lithium (Li) or potassium (K), a group II element such as magnet?? (Mg), calcium (Ca), or strontium (Sr) , Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group IV elements such as, tantalum (Ta), vanadium (V), niobium (Nb), or group V elements such as antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium ( Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolithium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ether A lanthanum (Ln)-based element such as bium (Yb) or rutedium (Lu) may be further included.

In addition, a gate insulating layer 111 and a gate electrode 113a are stacked on the channel region 109c of the active layer 109, and an interlayer insulating layer 115 is formed on the entire surface of the substrate including the gate electrode 113a. . At this time, as the gate electrode 103a, aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), Molytungsten (MoW), Molytitanium (MoTi), copper/molitanium (Cu /MoTi) may include at least one selected from the group of conductive metals, a combination of two or more thereof, or other suitable materials.

Further, a source region contact hole (not shown) and a drain region contact hole (not shown) exposing the source region 109a and the drain region 109b, respectively, are formed in the interlayer insulating layer 115.

A source electrode 121a and a drain electrode in contact with the source region 109a and the drain region 109b through the source region contact hole (not shown) and the drain region contact hole (not shown) on the interlayer insulating layer 115 (121b) is formed. At this time, the source electrode 121a and the drain electrode 121b include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), and silver (Ag). , Ag alloy, Gold (Au), Au alloy, Chrome (Cr), Titanium (Ti), Titanium alloy, Molytungsten (MoW), Molytitanium (MoTi), Copper It may include at least one selected from the group of conductive metals containing / molitanium (Cu/MoTi), a combination of two or more thereof, or other suitable materials.

Here, the source electrode 121a extends from the data line 121 and is spaced apart from the source electrode 121a to form a drain electrode 121b. In this case, the drain electrode 121b overlaps the gate electrode 113a by a predetermined width X1. The width X1 of the drain electrode 121b overlapping the gate electrode 113a is formed equal to or greater than the line width of the gate electrode 113a.

In addition, one end of the source electrode 121a may be formed to coincide with an edge portion of the gate electrode 113a or may be formed so as not to overlap.

Therefore, since the drain electrode 121b is completely overlapped with the gate electrode 113, light is not transmitted between the source electrode 121a and the drain electrode 121b and the gate electrode 113a, but is blocked. Since it cannot penetrate into the channel region (not shown) of the active layer 109, optical reliability is ensured.

Further, a passivation layer 123 exposing the drain electrode 121b is formed on the interlayer insulating layer 115 including the source electrode 121a and the drain electrode 121b.

Furthermore, a large-area common electrode 127 is formed on the passivation layer 123, and a planarization layer 129 is formed on the passivation layer 123 including the common electrode 127.

A drain contact hole (not shown) exposing the drain electrode 121b is formed in the planarization layer 129, and is electrically connected to the drain electrode 121b on the planarization layer 129, and the common electrode A plurality of pixel electrodes 133 spaced apart from each other by a predetermined interval to face 127 are formed.

In this way, the reference voltage for driving the liquid crystal, that is, the common voltage, is supplied to each pixel through the large-area common electrode 127. The common electrode 127 overlaps the plurality of pixel electrodes 133 with the planarization layer 129 interposed therebetween to form a fringe field.

As described above, the oxide thin film transistor array substrate for a display device according to the present invention completely blocks light transmitted to the channel region of the active layer by forming the drain electrode connected to the pixel electrode on the gate electrode to completely overlap the gate electrode. Optical reliability can be ensured.

In addition, the thin film transistor array substrate for a display device according to the present invention improves light reliability by completely blocking the light transmitted through the channel region of the active layer, and thus includes a high-resolution organic EL device TV and a liquid crystal display having a TOC structure. Applicable to display device products.

A thin film transistor array substrate for a display device having a TOC structure according to the present invention having the above configuration will be described with reference to FIGS. 8A to 8N.

8A to 8N are cross-sectional views illustrating a manufacturing process of a thin film transistor array substrate having a TFT on color filter.

As shown in FIG. 8A, a black matrix (BM) 103 is formed on the substrate 101 to block light from being transmitted to regions other than the pixel region.

Then, as shown in FIG. 8B, a color filter layer 105 of red, green, and blue colors is formed in the pixel area of the substrate 101. In this case, the black matrix 103 is positioned between the color filter layers 105 of the red, green, and blue colors.

The black matrix 143 is disposed to overlap with an area other than the pixel area of the substrate 101, for example, a thin film transistor T, a gate line (not shown), and an upper portion of a data line (not shown).

Next, as shown in FIG. 8C, a buffer layer 107 made of an inorganic insulating material is formed on the color filter layer 105.

Next, as shown in FIG. 8D, an active layer 109 made of an oxide semiconductor is formed on the buffer layer 107. At this time, the active layer 109a is a layer for forming a channel through which electrons move between the source electrode 121a and the drain electrode 121b, and is formed of low temperature polysilicon (LTPS) or amorphous silicon. Instead of the (a-Si) material, a silicon (Si)-based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nano tube, and graphene are used.

At this time, as the oxide semiconductor, at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) And a material in which silicon (Si) is added to an oxide semiconductor including zinc (Zn). For example, the active layer 109a may be formed of indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to an indium zinc composite oxide (InZnO).

When the active layer 109 is made of SIZO, the composition ratio of the silicon (Si) atom content to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer is about 0.001% by weight (wt%) to It may be about 30 wt%. As the content of silicon (Si) atoms increases, the role of controlling electron generation becomes stronger, and the mobility may decrease, but the stability of the device may be improved.

Meanwhile, as the active layer 109, in addition to the above-described materials, a group I element such as lithium (Li) or potassium (K), a group II element such as magnet?? (Mg), calcium (Ca), or strontium (Sr) , Group III elements such as gallium (Ga), aluminum (Al), indium (In) or yttrium (Y), titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Group IV elements such as, tantalum (Ta), vanadium (V), niobium (Nb), or group V elements such as antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium ( Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolithium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ether A lanthanum (Ln)-based element such as bium (Yb) or rutedium (Lu) may be further included.

Next, as shown in FIG. 8E, a gate insulating layer 111 and a gate electrode 113a are formed on the active layer 109. In this case, the gate insulating layer 111 includes a silicon (Si)-based oxide layer, a nitride layer, or a compound including the same, a metal oxide layer including Al ₂ O ₃ , an organic insulating layer, and a low dielectric constant (low- Includes materials with k) values. For example, as the gate insulating layer 107, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), any one selected from the group consisting of barium-strontium-titanium-oxygen compounds (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compounds (Bi-Zn-Nb-O) Or a combination of two or more thereof or other suitable materials may be included.

In addition, as the gate electrode 113a, aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), Molytungsten (MoW), Molytitanium (MoTi), Copper/Molytitanium (Cu) /MoTi) may include at least one selected from the group of conductive metals, a combination of two or more thereof, or other suitable materials.

Next, impurities are implanted into the active layer 109 under both sides of the gate electrode 113a to define a source region 109a and a drain region 109b, and a channel region 109c between them.

Subsequently, as shown in FIG. 8F, an interlayer insulating layer 115 is formed by depositing an inorganic insulating material on the entire surface of the substrate including the gate electrode 113a.

Next, as shown in FIG. 8G, the interlayer insulating layer 115 is selectively patterned through a mask process, so that the source region contact hole 117b exposes the source region 109a and the drain region 109b, respectively. And a drain region contact hole 117b.

Subsequently, as shown in FIG. 8H, after depositing a second metal layer (not shown) on the interlayer insulating layer 115, the source region 109a and the drain region 109b are selectively patterned through a mask process. A source electrode 121a and a drain electrode 121b in contact are formed. At this time, as the second metal layer for the source electrode 121a and the drain electrode 121b, aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), Silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, Molytungsten (MoW), molitanium ( MoTi), at least one selected from a conductive metal group including copper/molitanium (Cu/MoTi), a combination of two or more thereof, or other suitable materials may be included.

Here, the source electrode 121a extends from a data line (not shown) and is spaced apart from the source electrode 121a to form a drain electrode 121b. In this case, the drain electrode 121b overlaps the gate electrode 113a by a predetermined width X1. The width X1 of the drain electrode 121b overlapping the gate electrode 113a is formed equal to or greater than the line width of the gate electrode 113a.

In addition, one end of the source electrode 121a may be formed to coincide with an edge portion of the gate electrode 113a or may be formed so as not to overlap.

Therefore, since the drain electrode 121b is completely overlapped with the gate electrode 113, light is not transmitted between the source electrode 121a and the drain electrode 121b and the gate electrode 113a, but is blocked. Since it cannot penetrate into the channel region (not shown) of the active layer 109, optical reliability is ensured.

Next, as shown in FIG. 8I, a passivation layer 123 made of an inorganic insulating material is formed on the interlayer insulating layer 115 including the source electrode 121a and the drain electrode 121b.

Subsequently, as shown in FIG. 8J, the passivation layer 123 is selectively patterned through a mask process to form a drain contact hole 125 exposing a portion of the drain electrode 121b.

Next, as shown in FIG. 8K, after depositing a transparent conductive material layer (not shown) such as ITO and IZO on the passivation layer 123, the transparent conductive material layer is selectively patterned through a mask process. A large area common electrode 127 is formed.

Subsequently, as shown in FIG. 8K, an inorganic insulating material or an organic insulating material is deposited on the passivation layer 123 including the common electrode 127 to form a planarization layer 129.

Next, as shown in FIG. 8M, the planarization layer 129 is selectively patterned through a mask process to form a pixel electrode contact hole 131 exposing a portion of the drain electrode 121b.

Next, as shown in FIG. 8N, after depositing a transparent conductive material layer (not shown) such as ITO and IZO on the planarization layer 129 including the pixel electrode contact hole 131, the transparent material layer (not shown) is deposited. An oxide thin film transistor having a TFT on color filter structure according to the present invention by selectively patterning a layer of a conductive material to form a plurality of pixel electrodes 133 spaced apart from a common electrode 127 of a large area. Complete the array substrate manufacturing process.

In this way, the reference voltage for driving the liquid crystal, that is, the common voltage, is supplied to each pixel through the large-area common electrode 127. The common electrode 127 overlaps the plurality of pixel electrodes 133 with the planarization layer 129 interposed therebetween to form a fringe field.

As described above, the method of manufacturing a thin film transistor array substrate for a display device according to the present invention completely blocks light transmitted to the channel region of the active layer by forming the drain electrode connected to the pixel electrode to completely overlap the gate electrode, thereby improving optical reliability. Can be secured.

In addition, the method of manufacturing a thin film transistor array substrate for a display device according to the present invention improves light reliability by completely blocking light transmitted through the channel region of the active layer, thereby providing a high-resolution organic light emitting diode TV and a TOC structure. Applicable to display device products including liquid crystal display devices.

Meanwhile, a thin film transistor array substrate having a TOC structure for a display device according to another exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

9 is a schematic plan view of a thin film transistor array substrate having a TFT on color filter structure according to another embodiment of the present invention.

10 is a plan view showing an enlarged portion C of FIG. 9.

FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 9 and is a schematic cross-sectional view of a thin film transistor array substrate having a TFT on color filter structure according to another embodiment of the present invention.

In the case of the thin film transistor array substrate 200 having a TFT on color filter structure according to another embodiment of the present invention, the drain electrode electrically connected to the pixel electrode is above the gate electrode, as in an embodiment of the present invention. The example is a structure in which the source electrode extending from the data line completely overlaps the gate electrode rather than the structure overlapping with each other.

9 and 10, a TFT array substrate 200 having a TFT on color filter structure according to another embodiment of the present invention includes a gate wiring 213 formed on one surface of the substrate 201 in one direction. And a gate electrode 213a extending from the gate wiring 213; A data line 221 crossing the gate line 213 to define a pixel area; A thin film transistor T formed at an intersection of the gate line 213 and the data line 221; A large-area common electrode 227 formed in the pixel area of the substrate; It is formed in the pixel region, and includes a plurality of pixel electrodes 233 electrically connected to the drain electrode 221b of the thin film transistor T.

Here, a source electrode 221a extends from the data line 221 and is spaced apart from the source electrode 221a to form a drain electrode 221b. In this case, the source electrode 221a overlaps the gate electrode 213a by a predetermined width X2. The width X2 of the source electrode 121a overlapping the gate electrode 113a is formed equal to or greater than the line width of the gate electrode 113a.

In addition, one end of the drain electrode 221b may be formed so as not to coincide with or overlap with the edge of the gate electrode 213a.

In addition, although not shown in the drawing, a black matrix (not shown; see 203 in FIG. 11) is formed under the gate electrode 213a, so that light incident from the lower portion is transmitted to the channel region of the active layer 209. Is prevented.

Therefore, since the source electrode 221a is completely overlapped with the gate electrode 213, light is not transmitted between the source electrode 221a and the drain electrode 221b and the gate electrode 213a, but is blocked. Optical reliability is ensured because it cannot penetrate into the channel region (not shown) of the active layer 209.

The TFT array substrate 200 having a TFT on color filter structure according to another embodiment of the present invention will be described in detail with reference to FIG. 11.

FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 9 and is a schematic cross-sectional view of a thin film transistor array substrate having a TFT on color filter structure according to another embodiment of the present invention.

Here, the thin film transistor array substrate 100 according to another embodiment of the present invention includes all of a driveable thin film transistor structure including a top gate and a bottom gate method.

The thin film transistor array substrate 200 according to the present invention is a driving element or a switching element of a flat panel display such as a liquid crystal display (LCD), an organic light emitting diode (OLED), etc. , It can be applied to various electronic devices such as devices for configuring peripheral circuits of memory devices.

The substrate 201 may be made of silicon, glass, plastic or other suitable material.

Referring to FIG. 11, a thin film transistor array substrate 200 having a TFT on color filter structure is a black matrix 203 for blocking light from being transmitted to an area other than a pixel area on the substrate 201. Is formed, and a color filter layer 105 of red, green, and blue color is formed on the entire surface of the substrate including the black matrix 203, and on the color filter layer 205, a buffer layer ( 207) is formed. At this time, since the black matrix 203 is formed under the gate electrode 213a, light incident from the lower portion is prevented from being transmitted to the channel region of the active layer 209.

In addition, on the buffer layer 207 above the black matrix 203, an active layer 209 comprising a channel region 209c and a source region 209a and a drain region 209b formed on both sides of the channel region 209c is formed. Has been. At this time, the active layer 209a is a layer for forming a channel through which electrons move between the source electrode 221a and the drain electrode 221b, and is a low temperature polysilicon (LTPS) or amorphous silicon. Instead of the (a-Si) material, a silicon (Si)-based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nano tube, and graphene are used.

At this time, as the oxide semiconductor, at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) And a material in which silicon (Si) is added to an oxide semiconductor including zinc (Zn). For example, the active layer 209 may be formed of indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to an indium zinc composite oxide (InZnO).

When the active layer 209 is made of SIZO, the composition ratio of the content of silicon (Si) atoms to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer is about 0.001% by weight (wt%) to It may be about 30 wt%. As the content of silicon (Si) atoms increases, the role of controlling electron generation becomes stronger, and the mobility may decrease, but the stability of the device may be improved.

In addition, a gate insulating layer 211 and a gate electrode 213a are stacked on the channel region 209c of the active layer 209, and an interlayer insulating layer 215 is formed on the entire substrate including the gate electrode 213a. . At this time, as the gate electrode 203a, aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), Molytungsten (MoW), Molytitanium (MoTi), Copper/Molytitanium (Cu) /MoTi) may include at least one selected from the group of conductive metals, a combination of two or more thereof, or other suitable materials.

Furthermore, a source region contact hole (not shown) and a drain region contact hole (not shown) exposing the source region 209a and the drain region 209b, respectively, are formed in the interlayer insulating layer 215.

A source electrode 221a and a drain electrode in contact with the source region 209a and the drain region 209b through the source region contact hole (not shown) and the drain region contact hole (not shown) on the interlayer insulating layer 215 (221b) is formed. At this time, the source electrode 221a and the drain electrode 221b include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), and silver (Ag). , Ag alloy, Gold (Au), Au alloy, Chrome (Cr), Titanium (Ti), Titanium alloy, Molytungsten (MoW), Molytitanium (MoTi), Copper It may include at least one selected from the group of conductive metals containing / molitanium (Cu/MoTi), a combination of two or more thereof, or other suitable materials.

Here, a source electrode 221a extends from the data line 221 and is spaced apart from the source electrode 221a to form a drain electrode 221b. In this case, the source electrode 221a overlaps the gate electrode 213a by a predetermined width X2. The width X2 of the source electrode 221a overlapping the gate electrode 213a is formed to be equal to or larger than the line width of the gate electrode 213a.

In addition, one end of the drain electrode 221b may be formed to coincide with the edge portion of the gate electrode 213a or may be formed not to overlap.

Therefore, since the source electrode 221a is completely overlapped with the gate electrode 213a, light is not transmitted between the source electrode 221a and the drain electrode 221b and the gate electrode 213a, but is blocked. Optical reliability is ensured because it cannot penetrate into the channel region (not shown) of the active layer 209.

In addition, a passivation layer 223 exposing the drain electrode 221b is formed on the interlayer insulating layer 215 including the source electrode 221a and the drain electrode 221b.

Furthermore, a large-area common electrode 227 is formed on the passivation layer 223, and a planarization layer 229 is formed on the passivation layer 223 including the common electrode 227.

A drain contact hole (not shown) exposing the drain electrode 221b is formed in the planarization layer 229, and is electrically connected to the drain electrode 221b on the planarization layer 229, and the common electrode A plurality of pixel electrodes 233 are formed to face 227 and spaced at a predetermined interval.

In this way, a reference voltage for driving a liquid crystal, that is, a common voltage, is supplied to each pixel through the large-area common electrode 227. The common electrode 227 overlaps the plurality of pixel electrodes 233 with the planarization layer 229 therebetween to form a fringe field in each pixel area.

As described above, in the thin film transistor array substrate for a display device having a TOC structure according to another exemplary embodiment of the present invention, the source electrode extending from the data line is formed on the gate electrode so as to completely overlap the gate electrode. It is possible to secure light reliability by completely blocking the light transmitted to the region.

In addition, the thin film transistor array substrate for a display device according to the present invention improves light reliability by completely blocking the light transmitted through the channel region of the active layer, and thus includes a high-resolution organic EL device TV and a liquid crystal display having a TOC structure. Applicable to display device products.

On the other hand, a liquid crystal display device to which a semiconductor thin film transistor array substrate according to another embodiment of the present invention is applied will be described with reference to FIG. 12 as follows.

In the case of a liquid crystal display to which a thin film transistor array substrate according to another embodiment of the present invention is applied, a source electrode extending from a data line or a drain electrode connected to a pixel electrode overlaps the gate electrode, but here A structure in which the drain electrode overlaps the gate electrode will be described.

12 is a schematic cross-sectional view of a liquid crystal display device using a thin film transistor array substrate according to another embodiment of the present invention.

13 is a schematic cross-sectional view of an organic light emitting display device using a thin film transistor array substrate according to another embodiment of the present invention.

14 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention.

The thin film transistor array substrate 300 according to another exemplary embodiment of the present invention includes all of a driveable thin film transistor structure including a top gate and a bottom gate method.

In addition to the liquid crystal display (LCD), the thin film transistor array substrate according to the present invention is a driving element or switching element of a flat panel display such as an organic light emitting diode (OLED), or a memory. It can be applied to various electronic devices, such as devices for configuring peripheral circuits of devices.

The substrate 301 may be made of silicon, glass, plastic or other suitable material.

Referring to FIG. 12, a TFT array substrate 300 having a TFT on color filter structure includes a channel region 309c on the substrate 301 and a source region 309a formed on both sides of the channel region 309c. And an active layer 209 composed of a drain region 209b is formed. At this time, the active layer 309a is a layer for forming a channel through which electrons move between the source electrode 321a and the drain electrode 321b, and is a low temperature polysilicon (LTPS) or amorphous silicon. Instead of the (a-Si) material, a silicon (Si)-based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nano tube, and graphene are used.

At this time, as the oxide semiconductor, at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) And a material in which silicon (Si) is added to an oxide semiconductor including zinc (Zn). For example, the active layer 309 may be formed of indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to an indium zinc composite oxide (InZnO).

When the active layer 309 is made of SIZO, the composition ratio of the content of silicon (Si) atoms to the total content of zinc (Zn), indium (In), and silicon (Si) atoms in the active layer is about 0.001% by weight (wt%) to It may be about 30 wt%. As the content of silicon (Si) atoms increases, the role of controlling electron generation becomes stronger, and the mobility may decrease, but the stability of the device may be improved.

In addition, a gate insulating layer 311 and a gate electrode 313a are stacked on the channel region 309c of the active layer 309, and an interlayer insulating layer 315 is formed on the entire surface of the substrate including the gate electrode 313a. . At this time, as the gate electrode 313a, aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), Molytungsten (MoW), Molytitanium (MoTi), copper/molitanium (Cu) /MoTi) may include at least one selected from the group of conductive metals, a combination of two or more thereof, or other suitable materials.

Further, a source region contact hole (not shown) and a drain region contact hole (not shown) exposing the source region 309a and the drain region 309b, respectively, are formed in the interlayer insulating layer 315.

A source electrode 321a and a drain electrode contacting the source region 309a and the drain region 309b through the source region contact hole (not shown) and the drain region contact hole (not shown) on the interlayer insulating layer 315 321b is formed. In this case, the source electrode 321a and the drain electrode 321b include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), and silver (Ag). , Ag alloy, Gold (Au), Au alloy, Chrome (Cr), Titanium (Ti), Titanium alloy, Molytungsten (MoW), Molytitanium (MoTi), Copper It may include at least one selected from the group of conductive metals containing / molitanium (Cu/MoTi), a combination of two or more thereof, or other suitable materials.

Here, the source electrode 321a extends from the data line (not shown) and is spaced apart from the source electrode 321a to form a drain electrode 321b. In this case, the drain electrode 321b overlaps the gate electrode 313a by a predetermined width X3. The width X3 of the drain electrode 221b overlapping the gate electrode 313a is formed to be equal to or larger than the line width of the gate electrode 313a.

In addition, one end of the source electrode 321a may be formed to coincide with an edge portion of the gate electrode 313a or may be formed not to overlap.

Therefore, since the drain electrode 321b is completely overlapped with the gate electrode 313a, light is not transmitted between the source electrode 321a and the drain electrode 321b and the gate electrode 313a. Optical reliability is ensured since it cannot penetrate into the channel region (not shown) of the active layer 309.

In addition, a passivation layer 323 exposing the drain electrode 321b is formed on the interlayer insulating layer 315 including the source electrode 321a and the drain electrode 321b.

In addition, a large-area common electrode 327 is formed on the passivation layer 323, and a planarization layer 329 is formed on the passivation layer 323 including the common electrode 327.

A drain contact hole (not shown) exposing the drain electrode 321b is formed in the planarization layer 329, and is electrically connected to the drain electrode 321b on the planarization layer 329, and the common electrode A plurality of pixel electrodes 333 spaced at a predetermined interval to face 327 are formed.

In this way, a reference voltage for driving a liquid crystal, that is, a common voltage, is supplied to each pixel through the large-area common electrode 327. The common electrode 327 overlaps the plurality of pixel electrodes 333 with the planarization layer 329 therebetween to form a fringe field in each pixel area.

As described above, in the liquid crystal display to which the thin film transistor array substrate for a display device according to another embodiment of the present invention is applied, the drain electrode is formed on the gate electrode so as to completely overlap the gate electrode, thereby completely preventing light transmitted to the channel region of the active layer. It can be blocked to secure optical reliability.

In addition, the liquid crystal display to which the thin film transistor array substrate for a display device according to the present invention is applied completely blocks light transmitted through the channel region of the active layer, thereby improving light reliability, and thus has a high-resolution organic EL device TV and a TOC structure. Applicable to display device products including liquid crystal display devices.

On the other hand, an organic light emitting device to which a semiconductor thin film transistor array substrate according to another embodiment of the present invention is applied will be described with reference to FIG. 13 as follows.

In the case of the organic electroluminescent device to which the thin film transistor array substrate according to another embodiment of the present invention is applied, the source electrode extending from the data line or the drain electrode connected to the pixel electrode completely overlaps the gate electrode. , Here, a structure in which the drain electrode completely overlaps the gate electrode will be described as an example.

13 is a schematic cross-sectional view of an organic light emitting display device using a thin film transistor array substrate according to another embodiment of the present invention.

A thin film transistor array substrate according to another embodiment of the present invention includes all of a driveable thin film transistor structure including a top gate and a bottom gate method.

In addition to the liquid crystal display (LCD), the thin film transistor array substrate according to the present invention is a driving element or switching element of a flat panel display such as an organic light emitting diode (OLED), or a memory. It can be applied to various electronic devices, such as devices for configuring peripheral circuits of devices.

The substrate 401 may be made of silicon, glass, plastic or other suitable material.

Referring to FIG. 13, an organic light emitting device 400 to which a thin film transistor array substrate is applied includes a channel region 409c on a substrate 401 and a source region 409a and a drain region formed on both sides of the channel region 409c. An active layer 409 composed of 409b) is formed. At this time, the active layer 409a is a layer for forming a channel through which electrons move between the source electrode 421a and the drain electrode 421b, and is formed of low temperature polysilicon (LTPS) or amorphous silicon. Instead of the (a-Si) material, a silicon (Si)-based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nano tube, and graphene are used.

At this time, as the oxide semiconductor, at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) And a material in which silicon (Si) is added to an oxide semiconductor including zinc (Zn). For example, the active layer 409 may be formed of indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to an indium zinc composite oxide (InZnO).

When the active layer 409 is made of SIZO, the composition ratio of the silicon (Si) atom content to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer is about 0.001% by weight (wt%) to It may be about 30 wt%. As the content of silicon (Si) atoms increases, the role of controlling electron generation becomes stronger, and the mobility may decrease, but the stability of the device may be improved.

In addition, a gate insulating layer 411 and a gate electrode 413a are stacked on the channel region 409c of the active layer 409, and an interlayer insulating layer 415 is formed on the entire surface of the substrate including the gate electrode 413a. . At this time, as the gate electrode 413a, aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), Molytungsten (MoW), Molytitanium (MoTi), Copper/Molytitanium (Cu) /MoTi) may include at least one selected from the group of conductive metals, a combination of two or more thereof, or other suitable materials.

Further, a source region contact hole (not shown) and a drain region contact hole (not shown) exposing the source region 409a and the drain region 409b, respectively, are formed in the interlayer insulating layer 415.

A source electrode 421a and a drain electrode contacting the source region 409a and the drain region 409b through the source region contact hole (not shown) and the drain region contact hole (not shown) on the interlayer insulating layer 415 (421b) is formed. In this case, the source electrode 421a and the drain electrode 321b include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), and silver (Ag). , Silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum (MoW), molitanium (MoTi), copper It may include at least one selected from the group of conductive metals containing / molitanium (Cu/MoTi), a combination of two or more thereof, or other suitable materials.

Here, a source electrode 421a extends from the data line (not shown), and a drain electrode 421b is formed to be spaced apart from the source electrode 421a. In this case, the drain electrode 421b overlaps the gate electrode 413a by a predetermined width X4. The width X4 of the drain electrode 421b overlapping the gate electrode 413a is formed equal to or greater than the line width of the gate electrode 413a.

Further, one end of the source electrode 421a may be formed to coincide with the edge portion of the gate electrode 413a or may be formed so as not to overlap.

Therefore, since the drain electrode 421b is completely overlapped with the gate electrode 413a, light is not transmitted between the source electrode 421a and the drain electrode 421b and the gate electrode 413a but is blocked. Optical reliability is ensured since it cannot penetrate into the channel region (not shown) of the active layer 409.

In addition, a planarization layer 423 exposing the drain electrode 421b is stacked on the interlayer insulating layer 415 including the source electrode 421a and the drain electrode 421b. In this case, the planarization layer 423 is used by selecting from a group of organic materials including photo acryl.

Above the planarization layer 423, a first electrode 431, which is in contact with the drain electrode 421b of the thin film transistor T and through the drain contact hole (not shown), has a shape separated for each pixel region. Is formed. At this time, the first electrode 431 may be provided as a transparent electrode or a reflective electrode. When used as a transparent electrode, it may be provided with ITO, IZO, ZnO, or In ₂ O ₃ , and used as a reflective electrode. In this case, after forming a reflective film with Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, ITO, IZO, ZnO, or In ₂ O ₃ may be formed thereon. have.

And, above the first electrode 431, in the boundary region of each pixel region, a pixel definition made of an insulating material, particularly, for example, bensocyclobutene (BCB), polyimide, or photo acryl. A film 433 is formed. In this case, the pixel defining layer 433 is formed to surround each pixel area (not shown) and overlap the edge of the first electrode 431, and the display area AA as a whole has a plurality of openings. It has a grid shape.

An organic emission layer 435 made of an organic material emitting red, green, and blue light is formed on the first electrode 431 in each pixel area surrounded by the pixel defining layer 433. The organic light-emitting layer 435 may be composed of a single layer made of an organic light-emitting material, or although not shown in the drawing, in order to increase luminous efficiency, a hole injection layer, a hole transporting layer, and a light emitting layer material layer), an electron transporting layer, and an electron injection layer.

In addition, a second electrode 437 is formed on the entire surface of the display area AA including the organic emission layer 435 and the pixel defining layer 433. In this case, the first electrode 431 and the second electrode 437 and the organic emission layer 435 interposed between the two electrodes 431 and 437 constitute the organic electroluminescent device E.

Accordingly, when a predetermined voltage is applied to the first electrode 431 and the second electrode 437 according to the selected color signal, the organic electroluminescent device E may generate holes and second holes injected from the first electrode 431. Electrons provided from the electrode 437 are transported to the organic emission layer 435 to form excitons, and when these excitons transition from an excited state to a ground state, light is generated and emitted in the form of visible light. At this time, since the emitted light passes through the transparent second electrode 437 and goes out to the outside, the organic light emitting device 400 to which the display oxide thin film transistor array substrate according to another embodiment of the present invention is applied can display an arbitrary image. Will be implemented.

Although not shown in the drawings, a protective film, an organic film, and a barrier film (not shown) are stacked on the front surface of the second electrode 437 to achieve a panel state, thereby forming a display oxide thin film according to another embodiment of the present invention. An organic light emitting device 400 to which a transistor array substrate is applied is configured.

As described above, in the organic electroluminescent device to which the thin film transistor array substrate according to another embodiment of the present invention is applied, the drain electrode is formed on the gate electrode to completely overlap the gate electrode, thereby completely preventing light transmitted to the channel region of the active layer. By blocking, optical reliability can be secured.

In addition, the organic light emitting device to which the thin film transistor array substrate according to another embodiment of the present invention is applied completely blocks light transmitted through the channel region of the active layer to improve light reliability, It can be applied to display device products including seed structure liquid crystal display devices.

Meanwhile, a structure of a semiconductor thin film transistor for a display device according to another embodiment of the present invention will be described with reference to FIG. 14 as follows.

In the case of the thin film transistor for a display device according to another embodiment of the present invention, the source electrode extending from the data line or the drain electrode connected to the pixel electrode completely overlaps the gate electrode, but in this case, the drain electrode is A structure that is completely overlapped on the gate electrode will be described as an example.

14 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention.

A thin film transistor according to another embodiment of the present invention includes all of a driveable thin film transistor structure including a top gate and a bottom gate method.

In addition to a liquid crystal display (LCD), the oxide thin film transistor 500 according to the present invention is a driving element or a switching element of a flat panel display such as an organic light emitting diode (OLED), or , It can be applied to various electronic devices such as devices for configuring peripheral circuits of memory devices.

The substrate 501 may be made of silicon, glass, plastic or other suitable material.

Referring to FIG. 14, an organic light emitting device 500 to which a thin film transistor array substrate is applied includes a channel region 509c on a substrate 501 and a source region 509a and a drain region formed on both sides of the channel region 509c. An active layer 509 composed of 509b) is formed. In this case, the active layer 509a is a layer for forming a channel through which electrons move between the source electrode 521a and the drain electrode 521b, and is formed of low temperature polysilicon (LTPS) or amorphous silicon. Instead of the (a-Si) material, a silicon (Si)-based semiconductor film, an IGZO-based oxide semiconductor film, a compound semiconductor, a carbon nano tube, and graphene are used.

At this time, as the oxide semiconductor, at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga), and aluminum (Al) And a material in which silicon (Si) is added to an oxide semiconductor including zinc (Zn). For example, the active layer 409 may be formed of indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to an indium zinc composite oxide (InZnO).

When the active layer 509 is made of SIZO, the composition ratio of the silicon (Si) atom content to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer is about 0.001% by weight (wt%) to It may be about 30 wt%. As the content of silicon (Si) atoms increases, the role of controlling electron generation becomes stronger, and the mobility may decrease, but the stability of the device may be improved.

In addition, a gate insulating layer 511 and a gate electrode 513 are stacked on the channel region 509c of the active layer 509, and an interlayer insulating layer 515 is formed on the entire surface of the substrate including the gate electrode 513. . At this time, as the gate electrode 513, aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), Molytungsten (MoW), Molytitanium (MoTi), Copper/Molytitanium (Cu) /MoTi) may include at least one selected from the group of conductive metals, a combination of two or more thereof, or other suitable materials.

Further, a source region contact hole (not shown) and a drain region contact hole (not shown) exposing the source region 509a and the drain region 509b, respectively, are formed in the interlayer insulating layer 515.

A source electrode 521 and a drain electrode in contact with the source region 509a and the drain region 509b through the source region contact hole (not shown) and the drain region contact hole (not shown) on the interlayer insulating layer 515 523 is formed. At this time, the source electrode 521 and the drain electrode 523 include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), and silver (Ag). , Ag alloy, Gold (Au), Au alloy, Chrome (Cr), Titanium (Ti), Titanium alloy, Molytungsten (MoW), Molytitanium (MoTi), Copper It may include at least one selected from the group of conductive metals containing / molitanium (Cu/MoTi), a combination of two or more thereof, or other suitable materials.

Here, the drain electrode 523 overlaps the gate electrode 513 by a predetermined width X5. The width X5 of the drain electrode 523 overlapping the gate electrode 513 is formed equal to or greater than the line width of the gate electrode 513.

In addition, one end of the source electrode 521 may be formed to coincide with an edge portion of the gate electrode 513 or may be formed so as not to overlap.

Therefore, since the drain electrode 523 overlaps with the gate electrode 513, light is not transmitted between the source electrode 521 and the drain electrode 523 and the gate electrode 513, but is blocked, so that the active layer Since it is impossible to penetrate into the channel region (not shown) of 509, optical reliability is ensured.

As described above, in the thin film transistor according to another embodiment of the present invention, by forming the drain electrode on the gate electrode to completely overlap the gate electrode, light transmitted to the channel region of the active layer is completely blocked, thereby securing optical reliability. have.

In addition, the thin film transistor according to the present invention improves light reliability by completely blocking the light transmitted through the channel region of the active layer, and thus is applied to display device products including high-resolution organic light emitting diode TVs and liquid crystal displays having a TOC structure. This is possible.

Although many items are specifically described in the above description, they should be interpreted as examples of preferred embodiments rather than limiting the scope of the invention. For example, those of ordinary skill in the art to which the present invention pertains will be able to diversify the constituent elements of the thin film transistor of the present invention, and to change the structure into various forms.

It will be appreciated that the oxide thin film transistor array substrate for a display device of the present invention can be applied not only to a liquid crystal display device or an organic light emitting display device, but also to a memory device and a logic device field. Therefore, the scope of the present invention should not be determined by the described embodiments, but should be determined by the technical idea described in the claims.

100: oxide thin film transistor array substrate 103: black matrix
1035: color filter layer 107: buffer layer
109: active layer 111: gate insulating film
113a: gate electrode 115: interlayer insulating film
121a: source electrode 121b: drain electrode
123: passivation film 127: common electrode
129: planarization film 133: pixel electrode

Claims (12)

A black matrix positioned on the substrate;
Red, green, and blue color filter layers formed on the entire surface of the substrate including the black matrix;
A buffer layer on the color filter layer;
An active layer positioned on the buffer layer above the black matrix and including a source region, a channel region, and a drain region;
A gate insulating layer formed to be positioned only on the active layer and including a side surface positioned on the active layer;
A gate electrode on the gate insulating layer and overlapping the channel region of the active layer;
An interlayer insulating film formed on the entire surface of the substrate including the gate electrode and exposing the source region and the drain region of the active layer;
A source electrode formed on the interlayer insulating layer, overlapping with the gate electrode, in contact with the source region, or a drain electrode overlapping with the gate electrode and in contact with the drain region; And
A pixel electrode formed on the interlayer insulating layer including the drain electrode and electrically connected to the drain electrode,
The channel region of the active layer is located between the black matrix and the gate electrode,
The width of the black matrix is formed larger than the width of the active layer,
The source electrode or the drain electrode completely overlaps with the gate electrode and is formed to be equal to or larger than a line width of the gate electrode. delete The thin film transistor array substrate according to claim 1, wherein when one of the source electrode and the drain electrode overlaps the gate electrode, the other end is spaced apart from the edge of the gate electrode. . The thin film transistor array substrate of claim 1, wherein an interface of the red, green, and blue color filter layers overlaps the black matrix. delete The thin film transistor array substrate according to claim 1, wherein the thin film transistor array substrate is applied to a display device including a liquid crystal display (LCD) and an organic light emitting display device. delete delete delete delete delete delete

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