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KR101901218B1 - Stub minimization for assemblies without wirebonds to package substrate - Google Patents

Stub minimization for assemblies without wirebonds to package substrate Download PDF

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Publication number
KR101901218B1
KR101901218B1 KR1020147012162A KR20147012162A KR101901218B1 KR 101901218 B1 KR101901218 B1 KR 101901218B1 KR 1020147012162 A KR1020147012162 A KR 1020147012162A KR 20147012162 A KR20147012162 A KR 20147012162A KR 101901218 B1 KR101901218 B1 KR 101901218B1
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KR
South Korea
Prior art keywords
microelectronic
package
terminals
terminal
contacts
Prior art date
Application number
KR1020147012162A
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Korean (ko)
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KR20140081857A (en
Inventor
리차드 드윗 크리스프
와엘 조니
벨가셈 하바
프랭크 람브레히트
Original Assignee
인벤사스 코포레이션
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Priority claimed from US13/439,354 external-priority patent/US8629545B2/en
Application filed by 인벤사스 코포레이션 filed Critical 인벤사스 코포레이션
Publication of KR20140081857A publication Critical patent/KR20140081857A/en
Application granted granted Critical
Publication of KR101901218B1 publication Critical patent/KR101901218B1/en

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    • G11—INFORMATION STORAGE
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    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
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Abstract

The system 1500 or microelectronic assembly 300 may include one or more microelectronic packages 100 each having a substrate 102 and a microelectronic element 130, Having a surface 134 and at least one column 138,141 of the contact 132 exposed at this surface such that the contact 132 is facing a corresponding contact on the surface 120 of the substrate, . The axial surface 140 intersects the plane along the line in the first direction 142 and can be centered relative to the column of element contacts. The package terminals columns 104A and 104B may extend in a first direction. The first terminal exposed in the central region 112 of the second surface can be configured to convey usable address information to determine an addressable memory location in the microelectronic element. The central region 112 may have a width 152 that is no greater than 3.5 times the minimum pitch 150 between the columns of the package terminals. The axes can intersect the central area.

Description

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE FOR ASSEMBLY WITHOUT A WIRE BOND TO A PACKAGE SUBSTRATE

Cross-reference to related application

The present application is a continuation-in-part of U.S. Patent Application No. 13 / 439,354, filed April 4, 2012, which is filed on February 7, 2012 in U.S. Patent Application No. 61 / 600,361, U.S. Provisional Patent Application No. 61 / 542,488 filed on March 3, and U.S. Provisional Patent Application Serial No. 61 / 542,553, filed on October 3, 2011. The disclosures of both of these applications are hereby incorporated by reference.

TECHNICAL FIELD [0002] The subject-matter of the present application relates to an assembly that integrates a microelectronic package and a microelectronic package.

Semiconductor chips are often provided as individual packaged units. The standard chip has a flat rectangular body portion having a large front surface with a contact connected to the internal circuitry of the chip. Each individual chip is typically included in a package having external terminals, which are electrically connected to a circuit panel, such as a printed circuit board, and connect the contacts of the chip to the conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. When used herein with reference to a planar chip having a front surface, the expression " area of the chip " should be understood to refer to the area of the front surface.

In a " flip chip " design, the front face of the chip sees the face of the package dielectric element, the face of the substrate of the package, and the contacts on the chip are bonded directly to the contacts of the substrate by solder bumps or other connection elements. The substrate may then be bonded to the circuit panel through a terminal that rests on the side of the substrate. The " flip chip " design provides a relatively compact arrangement. In some cases, each package may be a " chip-scale package " occupying the area of the circuit panel that is equal to or slightly larger than the area of the front surface of the chip, as described in commonly assigned U.S. Patents 5,148,265, 5,148,266 , And 5,679, 977, the disclosures of which are incorporated herein by reference in their entirety. Any innovative mounting technique achieves compactness of conventional flip-chip bonding or provides the same compactness. Size is an important consideration in any physical arrangement of chips. With the rapid advancement of portable electronic devices, there is a growing demand for a more compact physical arrangement of chips. By way of example only, a device, often referred to as a " smartphone ", may be coupled to the functionality of a cellular phone with a powerful data processor, memory and ancillary devices such as a GPS receiver, an electronic camera, (LAN) connection. These devices can provide all pocket-sized devices with features such as full Internet connectivity, entertainment, navigation, electronic banking, etc., including full-resolution video. Complex portable devices require packing a number of chips into a small space. Moreover, some of these chips have many input and output connections, often referred to as " I / O ". These I / Os must be interconnected with the I / O of the other chip. The interconnect must be short to minimize signal propagation delay. The components forming such an interconnect should not significantly increase the size of the assembly. Similar requirements are occurring in other applications, such as in data servers such as those used in Internet search engines that require improved performance and size reduction.

Semiconductor chips, particularly dynamic random access memory chips (DRAM) and flash memory chips, including memory storage arrays are often packaged in multi-chip packages and assemblies. Each package has many electrical connections for transferring signals, power and grounding between terminals, i.e., the external connection points of the package and the chips therein. Such electrical connections include horizontal conductors (e.g., traces, beam leads, etc.) extending in a horizontal direction relative to the contact support surface of the chip, vertical conductors (e.g., vias) extending in a direction perpendicular to the surface of the chip, And may include different types of conductors, such as wire bonds extending both horizontally and vertically with respect to the surface.

Conventional microelectronic packages can incorporate microelectronic elements that have a memory storage array function, i. E., Microelectronic elements that implement a larger number of active elements to provide memory storage array functionality than any other function. These microelectronic elements may be or include DRAM chips, or stacked electrical interconnect assemblies of such semiconductor chips. Typically, all terminals of such a package are arranged in a set of columns adjacent to one or more peripheral edges of the package substrate on which the microelectronic elements are mounted. For example, in one conventional microelectronic package 12 shown in FIG. 1, three columns 14 of terminals may be disposed adjacent the first peripheral edge 16 of the package substrate 20, Adjacent to the second peripheral edge 22 of the package substrate 20, three different columns 18 of terminals may be disposed. In the conventional package, the central region 24 of the package substrate 20 does not have any column of terminals. Figure 1 also shows a semiconductor chip 11 in a package having an element contact 26 on one side 28 and the element contact 26 has an aperture 22 in the central region 24 of the package substrate 20, 18 of the package 12 via a wire bond 30 that extends through a bond window, for example a bond window. In some cases, an adhesive layer 32 may be disposed between the surface 28 of the microelectronic element 11 and the substrate 20 to enhance the mechanical connection between the microelectronic elements and the substrate, Lt; / RTI >

In view of the above description, particularly in those microelectronic packages and assemblies comprising circuit panels in which these microelectronic packages can be mounted and electrically interconnected with one another, terminals are provided on the microelectronic package to improve electrical performance An improvement in arrangement can be achieved.

A microelectronic assembly according to an embodiment of the present invention may include a circuit panel having first and second opposing surfaces and panel contacts exposed at each of the first and second opposing surfaces. The first and second microelectronic packages may have terminals respectively electrically connected to the panel contacts at the first and second surfaces. The circuit panel may electrically interconnect at least some of the terminals of the first microelectronic package with at least some of the corresponding terminals of the second microelectronic package.

In one example, each of said first and second microelectronic packages may comprise a microelectronic element having a memory storage array function. In one example, the microelectronic element can implement a greater number of active elements to provide memory storage array functionality than any other function. Wherein the microelectronic element can have one or more columns of element contacts exposed in a plane of the microelectronic element and each of the columns extends in a first direction along the face of the microelectronic element do. An axial plane perpendicular to the plane of the microelectronic element may intersect the face of the microelectronic element along a line extending in the first direction and be centered relative to one or more columns of the elementic contact. The microelectronic package can include a substrate having first and second opposing surfaces and a plurality of substrate contacts exposed at the first surface facing the element contact and connected to the element contact. A plurality of parallel columns of terminals exposed at the second surface may extend in a first direction along a second surface of the substrate. The terminal is electrically connected to the substrate contact, and the microelectronic package is connected to a component external to the microelectronic package.

The terminal may include a first terminal exposed in a central region of the second surface of the substrate. Said first terminal transferring address information usable by a circuit in said package to determine an addressable memory location among all of the available addressable memory locations of a memory storage array in said microelectronic element. . In one example, the central region has a width in a second direction along a second surface of the substrate across the first direction, and the width of the central region is greater than the width of any two adjacent columns Lt; RTI ID = 0.0 > 3.5 < / RTI > In this example, the axes may intersect the central region.

In one example, at least some of the first terminals of each of the first and second microelectronic packages may be disposed at a location within a respective grid on the microelectronic package, Can be aligned within one ball pitch of each other in x and y orthogonal directions parallel to the circuit panel surface.

In one example, the grid may be aligned with each other in the x and y orthogonal directions such that at least some of the first terminals of the grids of each of the first and second microelectronic packages coincide with each other.

In one example, the position of each of each of the grids may be occupied by one of the terminals.

In one example, at least one position of at least one of the grids is not occupied by the terminals.

In one example, at least half of the locations of the grid in the first and second microelectronic packages may be aligned with one another in x and y orthogonal directions parallel to the first surface of the circuit panel.

In one example, a first terminal disposed at a location within the grid of each microelectronic package may be configured to deliver all of the address information available by circuitry in each microelectronic package to determine an addressable memory location have.

In one example, a first terminal disposed at a location within a grid of each micro-package may be configured to convey information controlling an operating mode of the micro-electronic component of each micro-electronic package.

In one example, a first terminal disposed at a location within the grid of each of the microelectronic packages may be configured to carry all of the command signals transmitted to each of the microelectronic packages, wherein the command signals are programmable A row address strobe signal, and a column address strobe signal.

In one example, a first terminal disposed at a location within the grid of each of the microelectronic packages may be configured to transmit a clock signal that is transmitted to the microelectronic package. Each of the microelectronic packages may be configured to use the clock signal to sample a signal received at a terminal that carries address information.

In one example, a first terminal disposed at a location within the grid of each of the microelectronic packages may be configured to convey all of the bank address signals transmitted to each of the microelectronic packages.

In one example, the length of the stub of at least one of the electrical connections between one of the first terminals of the first microelectronic package and a corresponding one of the first terminals of the second microelectronic package, May be less than seven times the minimum pitch of the first terminal on the first microelectronic package.

In one example, at least some of the electrical connections through the circuit panel between the first terminal of the first microelectronic package and the first terminal of the second microelectronic package may have an electrical length of approximately the thickness of the circuit panel have.

In one example, the total length of the conductive elements connecting each pair of electrically connected first and second panel contacts exposed at the first and second surfaces of the circuit panel is greater than seven times the minimum pitch of the panel contacts Can be small.

In one example, the circuit panel may include a bus having a plurality of conductors configured to communicate at least some of the address information transmitted to each of the microelectronic packages, the conductors being parallel to the first and second surfaces And extend in a first direction.

In one example, a first terminal of each of the microelectronic packages may be disposed at a location within one column of each microelectronic package. In one example, the circuit panel includes a connection site on the circuit panel to which the terminals of the first and second microelectronic packages can be electrically connected, and a different connection site on which the terminals of the at least one third microelectronic package can be electrically connected Lt; RTI ID = 0.0 > routing layer. ≪ / RTI >

In one example, the only routing layer provides routing for a command signal, an address signal, a bank address signal, and a clock signal on the command-address bus of the circuit panel between the connection sites.

In one example, the circuit panel comprises an element having a coefficient of thermal expansion (CTE) less than 12 parts per million per degree Celsius, wherein panel contacts at the first and second surfaces extend through the element As shown in FIG.

In one example, the element may comprise essentially a semiconductor, glass, ceramic or liquid crystal polymer material.

A module according to an embodiment of the present invention includes a circuit panel and a plurality of microelectronic packages mounted on the circuit panel, wherein the microelectronic package is configured to transmit a signal to each of the microelectronic packages, And is electrically connected to the circuit panel through a terminal of each microelectronic package to transmit a signal from the electronic package. In this module, each of the microelectronic packages may comprise a microelectronic element having a memory storage array function. In one example, each of the microelectronic elements may implement a greater number of active elements to provide memory storage array functionality than any other function. The microelectronic element may have one or more columns of element contacts exposed in a plane of the microelectronic element, and each of the columns extends in a first direction along a face of the microelectronic element. An axis plane perpendicular to the plane of the microelectronic element intersects the plane of the microelectronic element along a line extending in the first direction and may be centered relative to one or more columns of the elementic contact. The module may also include a substrate having first and second opposing surfaces and a plurality of substrate contacts exposed at the first surface facing the element contact and connected to the element contact.

A plurality of parallel columns of terminals exposed at the second surface may extend in a first direction along a second surface of the substrate. The terminal is electrically connected to the substrate contact, and the microelectronic package is connected to a component external to the microelectronic package. Wherein the terminal comprises a first terminal exposed in a central region of a second surface of the substrate and the first terminal is an available addressable memory location of a memory storage array in the microelectronic element. And to pass available address information by circuitry within the package to determine an addressable memory location among all of the addressable memory locations. In this embodiment, the central region has a width in a second direction along a second surface of the substrate across the first direction, and the width of the central region is any two of the parallel columns of the terminals Is not greater than 3.5 times the minimum pitch between adjacent columns, and the axial plane intersects the central region.

A microelectronic assembly according to an embodiment of the present invention includes a circuit panel having first and second opposing surfaces and panel contacts exposed at each of the first and second opposing surfaces; And first and second microelectronic packages each having a terminal mounted to the panel contact at the first and second surfaces, respectively. The circuit panel may electrically interconnect at least some of the terminals of the first microelectronic package with at least some of the corresponding terminals of the second microelectronic package. In this example, each of the first and second microelectronic packages may comprise a microelectronic element having a memory storage array function. In one example, each of the microelectronic packages may implement a greater number of active elements to provide memory storage array functionality than any other function. Wherein the microelectronic element has at least one column of element contacts, each of the columns extending in a first direction along a face of the microelectronic element, and an axial face extending in a direction perpendicular to the face of the microelectronic element, Intersect the face of the microelectronic element along a line extending in a first direction, and may be centered relative to one or more columns of the element contact. The microelectronic package may further include a packaging structure, such as a dielectric layer, overlying a surface of the microelectronic component and having a surface facing away from the surface of the microelectronic component, and a plurality of terminals exposed at a surface of the dielectric layer have. At least some of the terminals may be electrically connected with traces extending along the dielectric layer and through the metallized vias extending from the traces and in contact with the element contacts. Wherein the terminal is disposed at a location in a plurality of parallel columns and can be configured to connect the microelectronic package to at least one component external to the microelectronic package, And a second terminal disposed at a position within the second terminal. Wherein said first terminal is configured to receive address information available by circuitry in the microelectronic package to determine an addressable memory location among all available addressable memory locations of a memory storage array of the microelectronic element. . ≪ / RTI > In one example, the central region is not wider than 3.5 times the minimum pitch between any two adjacent columns of the terminal, and the axial plane may intersect the central region.

In one example, at least some of the first terminals of each of the first and second microelectronic packages are disposed at a location within a grid on a respective microelectronic package, and the grid is disposed parallel to the first and second circuit panel surfaces can be aligned within one ball pitch of each other in the x and y directions. In one example, a first terminal disposed at a location within the grid of each of the microelectronic packages may be configured to convey information controlling an operating mode of the microelectronic element of each microelectronic package.

In one example, a first terminal disposed at a location within the grid of each of the microelectronic packages may be configured to carry all of the command signals transmitted to each of the microelectronic packages, wherein the command signals are programmable A row address strobe signal, and a column address strobe signal.

In one example, at least some of the electrical connections through the circuit panel between the first terminals of the first microelectronic package and the second microelectronic package may have an electrical length that is approximately the thickness of the circuit panel.

In one example, the total length of the conductive elements connecting each pair of electrically connected first and second panel contacts exposed at the first and second surfaces of the circuit panel is greater than seven times the minimum pitch of the panel contacts Can be small.

A system according to an embodiment of the present invention may include a microelectronic package and one or more other electronic components electrically connected to the microelectronic package. In one example, the microelectronic package may comprise a microelectronic element having a memory storage array function. In one example, the microelectronic element may implement a greater number of active elements to provide memory storage array functionality than any other function. Wherein the microelectronic element has at least one column of element contacts exposed at a surface of the microelectronic element, each column extending in a first direction along a face of the microelectronic element. An axis plane perpendicular to the plane of the microelectronic element intersects the plane of the microelectronic element along a line extending in the first direction and may be centered relative to one or more columns of the elementic contact. The microelectronic package can include a substrate having first and second opposing surfaces and a plurality of substrate contacts exposed at the first surface facing the element contact and connected to the element contact. A plurality of parallel columns of terminals exposed at a second surface of the substrate may extend in a first direction at a second surface of the substrate. The terminal is electrically connected to the substrate contact, and the microelectronic package is connected to a component external to the microelectronic package.

The terminal may include a first terminal exposed in a central region of the second surface of the substrate. The first terminal forwards address information available by the circuitry in the package to determine an addressable memory location among all available addressable memory locations of the memory storage array in the microelectronic element. . In one example, the central region has a width in a second direction along a second surface of the substrate across the first direction, and the width of the central region is greater than the width of any two adjacent columns Lt; RTI ID = 0.0 > 3.5 < / RTI > In this example, the axes may intersect the central region.

In one example, the microelectronic package and one or more other electronic components may be mounted in the housing.

In one example, the microelectronic package is a first microelectronic package, and the system further comprises a second microelectronic package.

1 is a cross-sectional view illustrating a conventional microelectronic package including a DRAM chip.
2 is a schematic diagram illustrating a microelectronic assembly, such as, for example, a DIMM module, incorporating a plurality of microelectronic packages mounted oppositely on first and second opposing surfaces of a circuit panel and a circuit panel.
3 is a cross-sectional view illustrating electrical interconnection between the first and second microelectronic packages and the circuit panel in an assembly such as that shown in FIG. 2;
4 is a top plan view illustrating electrical interconnection between a first microelectronic package and a second microelectronic package in an assembly such as that shown in FIG.
5 is a plan view illustrating terminal arrangement and signal allocation in a microelectronic package according to an embodiment of the invention.
FIG. 6A is a cross-sectional view taken along line 6A-6A of FIG. 5, illustrating the microelectronic package shown in FIG. 5. FIG.
6B is a top view illustrating a possible arrangement of element contacts and types of contacts on a microelectronic element in a microelectronic package according to any one of the embodiments disclosed herein, including the embodiment shown in FIGS. 5 and 6A. to be.
6C is a top view illustrating a possible arrangement of element contacts and types of contacts on a microelectronic element in a microelectronic package according to any one of the embodiments disclosed herein, including the embodiment shown in FIGS. 5 and 6A. to be.
7A is a top plan view illustrating another possible arrangement of element contacts on a microelectronic element in a microelectronic package according to the embodiment shown in FIGS. 5 and 6A.
7B is a plan view illustrating an arrangement of terminals according to the embodiment shown in Figs. 5 and 6A.
7C is a cross-sectional view illustrating a microelectronic assembly in accordance with an embodiment of the present invention and first and second microelectronic packages electrically interconnected with the microelectronic assembly.
7D is a schematic diagram illustrating a microelectronic assembly including a circuit panel according to an embodiment of the present invention and a microelectronic package electrically connected to the circuit panel among others.
8 is a top view illustrating another arrangement of terminals on a microelectronic package according to a variation of the embodiment shown in Figs. 5 and 6A.
FIG. 9A is a top view illustrating a microelectronic package according to a modification of the embodiment shown in FIGS. 5 and 6A.
9B is a corresponding cross-sectional view taken along line 9B-9B of Fig. 9A illustrating a microelectronic package according to a modification of the embodiment shown in Figs. 5 and 6A.
9C is a top plan view illustrating the electrical interconnection between the microelectronic elements and the substrate and the arrangement of the element contacts in the embodiment of the microelectronic package as shown in Figs. 9A and 9B.
10 is a cross-sectional view illustrating a microelectronic package including a stacked and electrically connected assembly of semiconductor chips, in accordance with an embodiment of the present invention.
11A is a cross-sectional view illustrating a microelectronic package including a stacked and electrically connected assembly of semiconductor chips, in accordance with an embodiment of the present invention.
11B is a cross-sectional view illustrating a microelectronic package including a stacked and electrically connected assembly of semiconductor chips, in accordance with an embodiment of the present invention.
12 is a cross-sectional view illustrating a microelectronic package including a stacked and electrically connected assembly of semiconductor chips, in accordance with an embodiment of the present invention.
13A is a cross-sectional view illustrating a microelectronic package including a stacked and electrically connected assembly of semiconductor chips, in accordance with an embodiment of the present invention.
13B is a cross-sectional view illustrating a microelectronic package including a stacked and electrically connected assembly of semiconductor chips, in accordance with an embodiment of the present invention.
14 is a cross-sectional view illustrating an embodiment of a microelectronic package including first and second microelectronic elements each having an element contact facing a corresponding substrate contact and connected to the substrate contact.
15A is a plan view illustrating signal assignment of a terminal on a microelectronic package according to the embodiment shown in FIG. 14, wherein FIG. 14 is a cross-sectional view taken along line 14-14 of FIG. 15A.
15B is a top view illustrating a possible placement of terminals on the packages of Figs. 14 and 15A for element contacts on the first and second microelectronic elements.
16A is a plan view illustrating another embodiment of a microelectronic package having first, second, third and fourth microelectronic elements spaced apart from one another on a substrate.
16B is a top view illustrating a possible arrangement and signal assignment of terminals on a microelectronic package according to the embodiment shown in FIG. 16A.
17A is a top plan view illustrating another embodiment of a microelectronic package having first, second, third, and fourth microelectronic elements spaced apart from each other in a pinwheel arrangement on a substrate.
17B is a top plan view illustrating a possible arrangement and signal assignment of terminals on a microelectronic package according to the embodiment shown in FIG. 17A.
18A is a cross-sectional view illustrating a wafer-level microelectronic package according to a modification of the embodiment shown in Figs. 5 and 6A.
18B is a cross-sectional view illustrating a fan-out wafer-level microelectronic package according to a variation of the embodiment shown in FIG. 18A.
19 is a cross-sectional view illustrating a system according to an embodiment of the present invention.

In light of the exemplary microelectronic package 12 of the example described with reference to FIG. 1, the inventors of the present invention can help improve the electrical performance of packages incorporating memory storage array chips and assemblies incorporating such packages Recognizing that there is a realizable improvement.

This improvement is particularly applicable to an assembly such as that shown in Figs. 2 to 4, in which the package 12A is mounted on the surface of the circuit panel and another similar package 12B is mounted on the opposite surface of the circuit panel, Lt; RTI ID = 0.0 > microelectronic < / RTI > The packages 12A and 12B are typically functionally and mechanically equivalent to each other. Typically, the other pair of functional and mechanically equivalent packages 12C and 12D (12E and 12F) are also mounted on the same circuit panel 34. The circuit panel and the package assembled to the circuit panel may form part of an assembly commonly referred to as a dual in-line memory module (DIMM). The packages 12A and 12B in each pair of oppositely mounted packages, such as packages 12A and 12B, may be mounted on opposite mutually facing surfaces of the circuit panel such that the packages in each pair typically lie on top of each other by more than 90% Connect to the contact. Local wiring in the circuit panel 34 connects terminals such as terminals labeled with reference numerals " 1 " and " 5 " on each package to global wiring on the circuit panel. Global wiring includes signal conductors on bus 36 that are used to connect some signals to connection sites on circuit panel 34, such as connection sites I, II, and III. For example, the packages 12A and 12B are electrically connected to the bus 36 by local wiring connected to the connection site I, the packages 12C and 12D are electrically connected to the bus by local wiring connected to the connection site II, 12F are electrically connected to the bus by local wiring connected to connection site III.

The circuit panel 34 includes terminals labeled with the reference numeral " 1 " near one edge 16 of the package 12A via the circuit panel 34 at the reference numeral " 1 " of the package 12B near the same edge 16 of the package 12B. 12B are electrically interconnected using local interconnect wiring that looks similar to a thermal cross or " shoelace " pattern that connects to a terminal labeled " shoelace " However, the edge 16 of the package 12B when assembled to the circuit panel 34 is located away from the edge 16 of the package 12A. 2 through 4 also show that a terminal indicated by the reference numeral " 5 " near the edge 22 of the package 12A is shown at 5 of the package 12B near the same edge 22 of the package 12B through the circuit panel 34. [ Lt; RTI ID = 0.0 > terminal. ≪ / RTI > In the assembly 38, the edge 22 of the package 12A is located away from the edge 22 of the package 12B.

The connection through the circuit panel between the terminals on each package such as package 12A and the corresponding terminals on the package mounted on the opposite side, such as package 12B, is considerably longer. 3, in such an assembly of similar microelectronic packages 12A, 12B, the circuit panel 34 is configured such that when the same signal from the bus is sent to each package, The conductor can be electrically interconnected with a terminal labeled "1" in package 12A and a corresponding terminal labeled "1" in package 12B. Similarly, circuit panel 34 may electrically interconnect another signal conductor of bus 36 with a terminal labeled 2 in package 12A and a corresponding terminal labeled 2 in package 12B . The same connection arrangement may be applied to the other signal conductors of the bus and corresponding terminals of each package. Local wiring between the bus 36 on the circuit panel 34 and each package of each package pair, such as packages 12A and 12B (Fig. 2) at the connection site I of the circuit panel, unterminated stubs. This local wiring may affect the performance of the assembly 38, as will be discussed in some cases, for relatively long periods of time. Furthermore, the circuit panel 34 may also be used to electrically couple specific terminals of other packages, e.g., pairs 12C and 12D of packages, and pairs 12E and 12F of packages to the global wiring of bus 36, , And such wiring can also affect the performance of the assembly in the same way.

4 shows a microelectronic package for each pair of terminals " 1 ", " 2 ", " 3 ", " 4 ", " 5 ", " 6 ", ≪ RTI ID = 0.0 > 12A < / RTI > As shown in Figure 4, since the columns 14, 18 of the terminals are respectively in the vicinity of the edges 16, 22 of the respective packages 12A, 12B, The wiring required to traverse the circuit panel 34 in the direction 40 across the first and second ends 42 may be quite long. The length of the DRAM chip can be set to any of the dimensions shown in FIGS. 2-4, which are required to route the same signal to the corresponding terminals of two oppositely mounted packages 12A, 12B, in the sense that each side can be in the range of 10 millimeters The length of the local wiring of the circuit panel 34 in the assembly 38 shown in FIG. 2 may range between 5 and 10 millimeters, and may typically be about 7 millimeters.

In some cases, the length of circuit panel wiring required to connect the terminals of such an oppositely mounted microelectronic package may not significantly affect the electrical performance of the assembly. However, since the signal transmitted by the connected pair of terminals on the package 12A, 12B includes clock information for sampling the address information common in the operation of the memory storage array function of a plurality of packages connected to the address information or the circuit panel The inventors of the present invention have found that the wiring length of the stub extending from the bus 36 to the terminals on each package can have a significant impact on performance . When interconnection wiring is relatively long, more severe effects occur and the settling time, ringing, jitter or intersymbol interference for the transmitted signal is increased to an unacceptable degree .

In a particular embodiment, the bus 36 used for conveying the address information may be a command-address bus 36 configured to carry command information, address information, bank address information, and clock information. In a specific implementation, the command information may be transmitted as a command signal through each signal conductor on the circuit panel. It is also possible that address information may be transmitted as an address signal through each signal conductor and that the bank address information may be transmitted as a bank address signal through each signal conductor, Signal. In a specific implementation of a microelectronic element having a memory storage array such as a DRAM chip, the command signal that may be transmitted by the bus 36 is a write enable, a row address strobe, and a column address strobe and a clock signal that may be communicated by bus 36 may be a clock signal that is used to at least sample the address signal carried by bus 36. [

Thus, certain embodiments of the invention described herein provide that the first and second microelectronic packages can be mounted on opposite surfaces of a circuit panel, such as a circuit board, a module substrate or a card, or a flexible circuit panel, A microelectronic package configured to reduce the length of a stub on a circuit panel when mounted. The assembly incorporating the first and second microelectronic packages electrically connected to the circuit panel at points of opposing circuit panels may have a significantly reduced stub length between each package. Reducing the stub length in such an assembly can improve electrical performance, among other things, by reducing one or more of settling time, ringing, jitter, or intersymbol interference. Furthermore, it may be possible to obtain other advantages such as simplifying the structure of the circuit panel, or reducing the complexity and cost of both designing or manufacturing the circuit panel or designing and manufacturing the circuit panel.

Therefore, a microelectronic package 100 according to an embodiment of the present invention is illustrated in Figs. 5 and 6A. As shown herein, the package 100 may include a microelectronic element 130 having a memory storage array function. In one example, in that microelectronic elements may have a greater number of active elements, such as, for example, transistors configured to provide memory storage array functionality than any other function, the microelectronic elements are mostly configured to provide memory storage array functionality .

As further shown, the package includes a substrate 102 having first and second opposing surfaces 120,110. The first and second surfaces are referred to as " opposing surfaces " because they are facing in opposite directions and are therefore opposite to each other. A plurality of first terminals 104 and a plurality of second terminals 106 are exposed at the second surface 110 of the substrate 102. As used herein, the expression that an electrically conductive element is " exposed " to a surface of a structure is available for contact with a theoretical point where the electrically conductive element moves in a direction perpendicular to the surface from the outside of the structure to the surface . Thus, a terminal or other conductive element exposed at the surface of the structure may protrude from such a surface, or may be recessed against such a surface and exposed through a hole or depression of the structure.

The substrate may comprise a sheet-like dielectric element, which in some cases may basically comprise polymeric materials such as resin or polyimide, among others. Alternatively, the substrate may comprise dielectric elements having a composite construction, such as, for example, BT resin or glass reinforced epoxy in FR-4 construction. In yet another example, the substrate may include a support element of a material having a coefficient of thermal expansion (CTE) of less than 12 parts per million (ppm), on which terminals and other conductive structures are disposed. For example, such a low thermal expansion coefficient (CTE) element may basically comprise a glass, ceramic or semiconductor material, or a liquid crystal polymer material, or a combination of such materials.

The first terminal 104 may be disposed at a location within a plurality of parallel columns 104A and 104B extending in a first direction and the second terminal 106 may be disposed at a location within a plurality of columns Lt; RTI ID = 0.0 > 106A < / RTI > In the example shown in Figure 5, the columns 104A and 104B may include several first terminals disposed in a central region 112 of the surface 110, respectively, and the columns 106A and 106B may each include a first And may include several terminals in each of the peripheral regions 114A, 114B disposed beyond the region. The central region has a width in a second direction transverse to the first direction. The central region is not wider than three and one-half times (3.5 times) the minimum pitch between adjacent columns in the parallel columns of terminals as shown below in relation to Figure 7b and further described. As indicated above, the first terminal may be configured to deliver address information that is sent to the microelectronic package. In a particular embodiment, the location information may be received by a first terminal from a bus 36 on the circuit panel, e.g., a command-address bus. The address information may be received as a separate address signal, e.g., as signals A0 through A15, through each first terminal, or some or all of the address information may be a combination of voltage levels received via more than one first terminal, For example, as information in the form of an encoding when it is received. In a particular embodiment, the rising transitions of the clocks used to sample the information, some or all of the address information, may be used as the clock transition from the higher voltage of the first state to the lower voltage of the second state Or some or all of the address information may be received by a falling transition of the clock, that is, a clock from the lower voltage of the second state to the higher voltage of the first state, Lt; / RTI > may be received via one or more of the first terminals. In another example, some of the address information may be received via one or more of the first terminals at a rising transition of the clock while some of the address information is received through one or more of the first terminals at a falling transition of the clock .

As described above, the second terminal 106 may be disposed at a location within one or more of the first and second peripheral regions 114A, 114B of the substrate surface 110, and the columns 106A, 106B. ≪ / RTI > The first and second perimeter regions may be adjacent to the first and second opposite edges 116, 118 of the surface 110, as shown in Figure 5 in some cases. The central region 112 is disposed between the first and second peripheral regions 114A, 114B. In one example, the second terminal may be located at a point in one or more columns 106A, 106B, each having a plurality of terminals.

In a particular example, when the microelectronic element comprises a DRAM semiconductor chip or a DRAM semiconductor chip, the first terminal in the central region is selected from all of the available addressable memory locations of the memory storage array in the microelectronic element May be configured by circuitry in the package to determine the addressable memory location, e.g., to deliver address information that is sent to the available microelectronic package, e.g., by the row address and column address decoder and bank selection circuitry (if present) have. Typically, when a microelectronic element comprises a DRAM chip, the address information in one embodiment is a random access address in a memory storage array in a microelectronic package for either read access, or read access and write access. And may include all address information that is used to determine a possible memory location, such as a circuit panel, that is sent to the package from a component external to the package.

In a specific implementation, such as when the microelectronic element is of a type that receives an address signal from a command-address bus on a circuit panel, the first terminal is configured to sample an address signal, a bank address signal, a specific command signal, Which is the clock used for the < / RTI > Although the clock signal may be of various types, in one embodiment, the clock signal delivered by these terminals is either a differentail or true clock signal and one of the received differential clock signals as a complement clock signal Or more. The " command signal " in this case may be a write enable signal, a row address strobe signal, and a column address strobe signal used by the microelectronic elements in the microelectronic package. For example, in a particular example, as shown in FIG. 5, the first terminal may receive clock signals CK and CKB, row address strobe RAS, column address strobe CAS, and write And may include an enable signal WE.

6A, the microelectronic element 130 in the microelectronic package 100 has the element contact 132 exposed at the surface 134 of the microelectronic element 130. As shown in FIG. The element contact 132 is facing the corresponding substrate contact 136 exposed to the surface 120 of the substrate 102. For example, the contact of the microelectronic element may be connected to the contacts of the substrate in a flip-chip manner using a bond metal, such as solder, tin, indium, gold, eutectic or other electrically conductive bond metal, . Alternatively, another suitable metal-to-metal connection, such as a copper-copper bonding process using a copper bump on one or both of the element contacts 132 and the corresponding substrate contacts 136, Technology can be used.

5 and 6A, the microelectronic package 100 includes a first terminal 104 exposed at a surface 110 of a substrate in a central region 112 of a surface 110 of the substrate 102 Lt; RTI ID = 0.0 > 104A < / RTI > The element contacts 132 exposed on the face 134 of the microelectronic element 130 are positioned on the surface 134 of the microelectronic element in a first direction 142 extending in a first direction 142, And the second column (138, 139). The columns of the contacts on the microelectronic elements may be entirely as in the case of column 138, or the columns of the contacts may have contacts only at some location in the column, as in the example of column 139. [ 6A and 6B, the axial plane 140 of the microelectronic element 130 is parallel to the plane 134 of the microelectronic element 130 along a line extending in the first direction 142 And this axial surface 140 also extends in a second direction perpendicular to the surface 134 of the microelectronic element. In the case of the microelectronic element 130 shown in FIG. 6B, the facet 140 has a surface 134 of microelectronic elements at a centered point, such as a point of equidistance between the columns 138 and 139 of the element contact, ). ≪ / RTI > As further shown in Figure 6B, as the columns 138, 139 of the element contacts are not precisely centered between opposite edges 146, 148 of the microelectronic element, And may be displaced in a direction perpendicular to the plane 134 from the center line 144 extending in the direction 142 and precisely centered between the opposite edges 146 and 148 and is typically so . However, in certain embodiments, when the position of the column 138, 139 is centered such that the center line 144 is centered between the columns, the axial surface 140 may coincide with the center line 144.

As further shown in FIG. 6B, the microelectronic element 130 may further include a plurality of peripheral contacts adjacent one or more of the peripheral edges 146, 148. These peripheral contacts may be used for connection to a contact available for contact with a probing device, such as may be used for power, ground, or testing. In this case, the intersection points of the facets 140 with the surface 134 of the microelectronic element may be centered only on the columns 138, 139 of the contacts disposed adjacent to each other near the center of the microelectronic element. Another contact 192 positioned adjacent one of the edges 146 or 148 of the microelectronic element and configured for connection to power, ground or probing is located at an intersection of the axis 140 with the microelectronic element 130 Which is ignored in determining the position of < RTI ID =

Thus, the contacts of the microelectronic elements may comprise one or more columns 138,139 comprising a plurality of contacts while being made of a first contact. The contact of the microelectronic element may further include a second contact 192 that is exposed at the face of the microelectronic element and disposed adjacent one or more edges of the face of the microelectronic element. The second contact 192 is less than the number of first contacts in any one column of that face. In a particular example, each of the second contacts may be configured to connect to one of the power source or ground, or may be configured for connection to the probing device. In the completed package 100, these contacts may be free of electrical connection to the substrate 102, or, in some cases, only electrically connected to corresponding power or ground conductors on the substrate. In this example, the point of intersection of the facet 140 with the face 134 of the microelectronic element 130 is aligned with the position of the second contact 192, for example, as shown in FIG. 6B, Can be centered for the same first contact column.

Figure 6c illustrates one or two columns 338 and 339 proximate the center of the microelectronic element 330, e.g., the center axis 140 of the microelectronic element, and the contact pad 332 of the microelectronic element 330, As shown in FIG. In this example, the element contact that is coupled to the corresponding contact 136 (Fig. 6A) of the substrate may be a redistribution contact 145, 147 on the microelectronic element. Some or all of the redistribution contacts 145 and 147 that are electrically connected to the contact pad 332 may be displaced from the contact pad 332 in one or more directions 142 and 143 along the surface of the microelectronic element. In one example, the redistribution contact may be disposed in a plurality of columns 135, 137 closer to the edges 146, 148 of the microelectronic element than the columns 338, 339 of the contact pads 332. In a particular example, redistribution contacts may be distributed in an array of regions exposed at the surface of the microelectronic element. In another particular example, the redistribution contact may be distributed along one or more peripheral edges 146, 148 of a microelectronic element that extends in a first direction 142, or may be distributed along a second May be distributed along one or more peripheral edges 151, 153 of the microelectronic elements extending in a direction 143. In another example, the redistribution contact may be distributed along the peripheral edges 146, 148, 151, 153 of the microelectronic element. In any of these examples, the redistribution contacts 145 and 147 may be disposed on the same side of the microelectronic element as the contact pad 332, or on the side of the microelectronic element opposite the contact pad . In one example, each contact pad may be connected to a redistribution contact. In another example, a redistribution contact may not be connected to one or more contact pads. Such one or more contact pads 332 that are not connected to the redistribution contact may or may not be electrically connected to one or more corresponding terminals of the package.

6A, the facet 140 intersects the central region 112 of the surface 110 of the substrate 102 of the microelectronic package 100. As shown in FIG. Thus, the axial surface includes columns 104A, 104B, 104C, and 104D that include terminals configured to carry a first terminal 104 configured to carry the address information described above, or in certain embodiments, command-address bus information or command- 104B intersect the central region 112 of the exposed substrate surface 110. Hereinafter, it will be understood that reference to the first terminal refers to the exposed terminal in the central region 112 of the substrate surface, and such terminal as a whole is available for use in the memory storage array in the microelectronic component of the microelectronic package Wherein the first terminal is configured to transfer address information available by circuitry in the microelectronic package to determine an addressable memory location among all of the memory locations, At least all, or at least three, or more, of the address information used by the circuit. In some embodiments, the first terminal also receives additional information or signals, such as command information or command signals, bank address information, and clock information for the write enable, row address strobe and column address strobe functions as described above . ≪ / RTI >

A bond metal such as a solder, tin, indium or eutectic mixture, which may be used to couple the terminals of the package 100 to a component external to the package, such as a corresponding contact of the circuit panel, Coupling elements 154A and 154B of other electrically conductive bond materials may be coupled to terminals 104A and 104B.

As shown further in Figure 7A, in some cases, the microelectronic element 230 may have only one column 238 containing a plurality of contacts exposed at the face 134, (240) extends through the column (238) of the contacts. 7B, when integrated into the microelectronic package 200, the facet 240 may intersect the central region 112 of the substrate surface at a point between the columns 104A, 104B of the terminals, The axis 240 and each of the columns 104A and 104B extend in a first direction 142 in which a column 238 of contacts of the microelectronic element extends. Alternatively, in another example (not shown), the axial surface 240 may intersect the central region 112 along a line extending in a first direction, where the line is connected to the columns 104A, 104B of the terminals, ≪ / RTI >

As further shown in FIG. 7B, the minimum pitch 150 is represented as the shortest distance between any two adjacent columns of terminals on the substrate. The minimum pitch is defined as the minimum distance between the center lines extending in the direction 162 through each adjacent column.

The minimum pitch is determined in a direction 143 that is perpendicular to the direction 142 in which the terminals in a particular column, such as column 104A, are arranged. In the example shown in FIG. 7B, the minimum pitch occurs between the columns 104A and 104B closest to each other between the edges 116 and 118 of the substrate 110. Referring to Figure 7B, the central region 112 has a maximum width 152 along the substrate surface 110 in a second direction transverse to the direction 143 of the pitch, i.e., the first direction 142, 152 are not greater than 3.5 times the minimum pitch between any two adjacent columns of terminals, such as columns 104A, 104B of the terminals.

7C illustrates the microelectronic assembly 300 of the first and second microelectronic packages 100A and 100B as mounted on the first and second opposing surfaces 350 and 352 of the circuit panel 354, Each microelectronic package is a microelectronic package 100 as described with reference to Figs. 5 to 6B. The circuit panel may be of various types, among other things, a dual inline memory module (DIMM) module, a circuit board or circuit panel to be connected to other components in the system, or a motherboard. The circuit panel has a contact configured to electrically connect to the microelectronic package. In certain embodiments, the circuit panel may include an element having a coefficient of thermal expansion (CTE) that is less than 12 parts per million per degree Celsius, and panel contacts at the first and second surfaces Lt; RTI ID = 0.0 > through < / RTI > For example, the element may basically comprise a semiconductor, glass, ceramic, or liquid crystal polymer material.

The first and second microelectronic packages 100A and 100B may be mounted on the corresponding panel contacts 360 and 362 exposed at the first and second surfaces 350 and 352 of the circuit panel 354. In the example shown in Fig. 7C, the first terminals 104-1 and 104-2 may be disposed at a point in the grid 105 on the first package 100A. The first terminals 104-1 and 104-2 of the second package 100B may also be disposed at points in the grid 105 on the second package. Each grid of terminals may be present as a whole. That is, there is a terminal occupying each position of each grid. Alternatively, one or more locations of each grid may not be occupied by the terminals. 7c, the grid may be aligned within one ball pitch of each other in the x and y orthogonal directions parallel to the surface 350 of the circuit panel, and the ball pitch may be on one of the two packages < RTI ID = 0.0 > Is not greater than the minimum pitch between any two adjacent parallel columns of the terminal. In a particular example, at least half of the locations of the grids of the first and second packages may be aligned with one another in the x and y orthogonal directions parallel to the first surface of the circuit panel.

In a particular example, the grids may be aligned with one another in the x and y directions such that at least some of the first terminals on the first and second microelectronic packages coincident. As used herein, when the first terminals of the packages on opposite surfaces of the circuit panel " match " one another, the alignment may be within a customary manufacturing tolerance, or the first and second May be within a tolerance of less than half of one ball pitch of each other in the x and y orthogonal directions parallel to the circuit panel surface, and the ball pitch is as described above.

The wiring in the circuit panel 354 is connected to the terminal 104-1 in the column 104A of the terminals of the package 100A by the terminal 104-1 in the column 104A of the terminals of the package 100B, Respectively. The wiring forming the electrical connection is shown by dashed line 320 in Figure 7c because this wiring may be obscured in the particular illustration provided in Figure 7c. Similarly, the wiring in the circuit panel 354 is accomplished by connecting the terminal 104-2 of the column 104B of the terminals of the package 100A to the terminal 104-2 of the column 104B of the terminals of the package 100B And the electrical interconnection between these terminals is shown by dashed line 322 in Figure 7c.

Further, in the particular example as shown in Fig. 7C, if there are two columns 104A, 104B with first terminals in each grid and the grid is aligned within at least one ball pitch with respect to each other, The wiring on the circuit panel 354 required to connect a terminal labeled " A " in the first terminals of the package 100B with a terminal labeled " A " in the first terminals of the package 100B may be relatively short. Specifically, when each grid 104 on each package has two columns 104A, 104B and the grid 104 is aligned in the manner described above, the first column 104A of the first package 100A Are aligned in one ball pitch of the second column 104B of the second package in the x and y orthogonal directions parallel to the first surface 350 of the circuit panel and the second column 104B of the first package 100A Are aligned in one ball pitch of the first column 104A of the second package in the x and y orthogonal directions parallel to the first surface 350 of the circuit panel.

The electrical length of the stub on the circuit panel 354 that electrically connects the first terminal 104-1 of the first package 100A to the corresponding first terminal 104-1 on the second package 100B is May be less than seven times the minimum pitch of the first terminals on each package, e.g., seven times the pitch 150 between the columns 104A and 104B of the first terminals in Fig. 7B. In other words, the first and second panel contacts, which are exposed to the first and second surfaces of the circuit panel to electrically interconnect the first and second panel contacts with corresponding conductors of the bus on the circuit panel, The total length of the conductive elements connecting the pair may be, for example, less than seven times the minimum pitch of the panel contacts. Moreover, the length of the stub of the connection of at least one of the electrical connections between one of the first terminals of the first microelectronic package and a corresponding one of the first terminals of the second microelectronic package, May be less than seven times the minimum pitch of the first terminals on the package. In a particular embodiment in which the first terminal is configured to carry the command-address bus signal described above, the first and second panel contacts are electrically interconnected with one of the corresponding one of the command-address bus signals on the circuit panel The total length of the conductive elements connecting the pair of electrically connected first and second panel contacts exposed at the first and second surfaces of the circuit panel may be less than seven times the minimum pitch of the panel contacts . In another example, the electrical length of the connection between the first terminal 104-1 of the first package 100A and the corresponding first terminal 104-1 on the second package 100B is less than the electrical length of the first and second May be approximately equal to the thickness 356 of the circuit panel 354 between the surfaces 350, 352.

The reduction of the length of these electrical connections can reduce the stub length in the circuit panel and assembly, which is advantageous because the aforementioned signals transmitted by the first terminal and transmitted to the microelectronic elements in both the first and second packages Such as reducing the settling time, ringing, jitter, or inter-symbol interference for the device.

Moreover, it may be possible to achieve other advantages such as simplifying the structure of the circuit panel or reducing the complexity and cost of designing or manufacturing the circuit panel. That is, the connection on the circuit panel may require fewer layers of wiring to interconnect the first terminal of each package to the bus on the circuit panel, such as the bus or command-address bus described above, which carry address information.

In addition to this, it is also possible to provide a circuit board which extends in at least one direction generally parallel to the surface of the circuit panel, which is required to route signals from the aforementioned signals delivered by the first terminal, such as address information or command- In some cases the number of global routing layers of a conductor, such as wiring, may be reduced. For example, between the connection sites to which the first pair of microelectronic packages 100A, 100B are connected and the different connection sites to which one or more other microelectronic packages are connected, for example, between the connection sites II and III The number of such overall routing layers can be reduced when the microelectronic package attached thereon is constructed in accordance with the principles of the present disclosure. In particular, the total number of routing layers required to route such signals along the circuit panel can be reduced to two or less routing layers. In a particular example, all of the address or command-address bus signals described above between the connection site to which the first and second microelectronic packages are connected and the different connection sites to which at least the third microelectronic package 100A or 100B is electrically connected At most one routing layer may exist for overall routing. However, a greater number of overall routing layers may be used on the circuit panel to carry signals other than the address signals or command-address bus signals described above. FIG. 7d illustrates a microelectronic assembly, such as a DIMM, incorporating a circuit panel and a plurality of microelectronic packages mounted opposite to the first and second opposing surfaces, among others. 7D, the above-described address signal or command-address bus signal is supplied to at least one of connection sites I, II, or III to which each pair of microelectronic packages 100A, 100B is connected on the opposite side of the circuit panel May be routed through bus 36, such as an address bus or a command-address bus, on circuit pads or circuit board 354 in one direction 143. The signal of this bus 36 reaches each pair of packages at each connection site I, II or III at slightly different times. At least one direction 143 may be perpendicular to or perpendicular to the direction 142 in which at least one column 138 of a plurality of contacts on at least one microelectronic element in each package 100A, have. In this manner, the signal conductor of the bus 36 on the circuit panel 354 (i. E. On the circuit panel or in the circuit panel) may in some cases be connected to a contact on the microelectronic element in the package 100A, (142) parallel to at least one column (138). This arrangement allows the signal on the bus 36 to be routed, especially when the first terminals 104-1 and 104-2 of each microelectronic package are exposed in a position in one or more columns extending in this direction 142 May help to simplify the routing of signal conductors of one or more overall routing layers on the circuit panel used to do so. For example, it may be possible to simplify the routing of the command-address bus signal on the circuit panel when relatively few first terminals are placed in the same vertical layout position on each package. 5, only two first terminals 104, such as a first terminal 104 configured to receive address signals A3 and A1, are placed in the same vertical layout position on each package .

In one example embodiment, the microelectronic assembly 354 includes a second microelectronic package 342 that may include a semiconductor chip configured to perform buffering of at least some of the signals transmitted to the microelectronic packages 100A, Element 358. < RTI ID = 0.0 > In a particular embodiment, the first microelectronic element may be configured to perform a logic function, such as a solid state drive controller, and one or more of the microelectronic elements 358 in the microelectronic packages 100A, And a memory storage element such as a flash memory. In one example, the second microelectronic element 358 is coupled to the system 1500 (see FIG. 19) from supervising the transfer of data to and from the memory storage element contained in the microelectronic element 130, For example, a central processing unit of a system such as a microprocessor. Such a microelectronic component 358, including a solid state drive controller, is intended to provide direct memory access to a data bus on a motherboard (e.g., circuit panel 1502 shown in FIG. 19) of a system such as system 1500, It is possible to provide direct memory access from the bus. In certain embodiments, the microelectronic element 358 may have a buffering function. These microelectronic components 358 may be used to provide impedance isolation for each of the microelectronic components 130 in the microelectronic packages 100A and 100B for the components external to the microelectronic assembly 354 or the system 1500 To provide assistance.

In a particular embodiment, the first terminal 104 of the microelectronic package may be configured to convey information that controls the mode of operation of the microelectronic element 101. More specifically, the first terminal may be configured to deliver all of a particular set of command and / or clock signals to be sent to the microelectronic package 100. In one embodiment, the first terminal 104 may be configured to carry all of the command signal, the address signal, the bank address signal, and the clock signal transferred from the external component to the microelectronic package 100, A row address strobe signal, a column address strobe signal, and a write enable signal. In this embodiment, the first chip may be configured to regenerate information that controls the operating mode. Alternatively or additionally, the first chip may be configured to partially or fully decode information that controls the operating mode of the microelectronic element. In this embodiment, each second chip may be configured to decode at least one of the address information, command information, or information that controls the mode of operation of the microelectronic element, and may not be configured to decode.

A microelectronic package having another array of terminals thereon may be provided. For example, in the microelectronic package 400 illustrated in FIG. 8, four columns 404A, 404B, 404C, 404D of terminals are located in the central region 112 of the substrate surface, And a first terminal configured to transfer all of the command signal, the address signal, the bank address signal, and the clock signal used for the address signal. In another example (not shown), it is also possible for the first terminals of the microelectronic package to be placed in positions within the three columns.

In the microelectronic package 500 illustrated in Figures 9A and 9B, the first terminals 504 are disposed at locations within a single column 505 disposed in a central region 512 of the substrate surface, 505 extend in a direction parallel to the edges 516, 518 of the microelectronic package. Although shown in Fig. 9A, the second terminal is omitted in Fig. 9B for clarity of illustration.

9A, the minimum pitch between any two columns of terminals on the substrate is equal to the pitch 552 between adjacent columns 506B, 506C of the second terminal disposed in the peripheral region 514B of the substrate surface )to be. The width 554 of the central region is not greater than 3.5 times the minimum pitch 552 between the columns 506B and 506C of the terminals.

9B, the microelectronic element 530 of the microelectronic package 500 may have a single column of element contacts 538 on the side 534 of the microelectronic element. In this case, the internal electrical connection between the element contact 538 and the first terminal 504 of the microelectronic package 500 may be particularly short. For example, in the microelectronic package 500 shown in FIG. 9C, the connection between the element contact 538A and the first terminal 504 is such that in either case, the column 538A of element contacts is connected to the microelectronic element 530 Extend only in a first direction 524 that extends over the surface 534, or may extend primarily in this first direction. The connection between the element contact 538B and the first terminal 504 can extend only in the vertical direction over the contact 538B in either case so that at least some of the first terminals The contact 508 can be at least partially placed on the element contact 538 to which the contact 538B is electrically connected.

10 illustrates a microelectronic package 600 according to a particular example in which the microelectronic element 630 includes a plurality of vertically stacked electrically interconnected semiconductor chips 632 and 634. FIG. In this case, the microelectronic element 630 is configured such that the element contact 636 on the face 638 of the first semiconductor chip 632 faces the exposed substrate contact 640 at the first surface 610 of the substrate, And a first semiconductor chip 632 coupled to the first semiconductor chip 640. The microelectronic element also includes at least one second semiconductor chip 634 overlying a face 642 of the first semiconductor chip 632 opposite the face 638 of the first semiconductor chip, Away from the first surface 610 of the substrate 602. One or more second semiconductor chips 634 are electrically interconnected with the first semiconductor chip 632. For example, as shown in Fig. 10, there are three vertically stacked second semiconductor chips 634 on which the faces of the second semiconductor chip 634 lie on top of each other.

In the microelectronic package 600 shown in FIG. 10, each of the first and second semiconductor chips 632 and 634 may have a memory storage array function. In one example, each of the first and second semiconductor chips may be configured such that each such semiconductor chip implements a plurality of active elements to provide memory storage array functionality rather than any other function. For example, each of the first and second semiconductor chips may include a memory storage array and all of the circuitry required to input data to and output data from the memory storage array. For example, when a memory storage array in each semiconductor chip is writable, each semiconductor chip is configured to transmit data output from such semiconductor chip to terminals of the package as well as circuits configured to receive external data inputs from the terminals of the package Circuit. Thus, each first semiconductor chip 632 and each second semiconductor chip 634 can be a dynamic random access memory (DRAM) chip or a memory storage array within such a semiconductor chip, to input data and output data therefrom, Or other memory chip capable of receiving data and transmitting the data to a component outside the microelectronic package. In other words, in this case, the signals to and from the memory storage array in each DRAM chip or other memory chip do not require buffering by additional semiconductor chips in the microelectronic package.

Alternatively, in another example, one or more second semiconductor chips 634 may implement a number of active devices to provide memory storage array functionality rather than any other function, but the first semiconductor chip 632 may be of a different type Chip. In this case, the first semiconductor chip 632 may be, for example, a semiconductor chip for reproducing a signal received at a terminal for buffering signals, that is, for transferring to one or more second semiconductor chips 634, Or from a terminal to one or more second semiconductor chips 634 and from one or more semiconductor chips to a terminal of the microelectronic package, For example, be designed, built or set up, and so on.

Alternatively or in addition to reproducing the signal as described above, in one example, the first chip in such a composite microelectronic element can be configured to partially or fully decode information controlling the mode of operation of the microelectronic element . In a particular example, the first semiconductor chip in such a composite microelectronic element may be configured to partially or fully decode at least one of address information or command information received at a same terminal as the first terminal. The first chip may then output the result of this partial decoding or the overall decoding for transmission to the one or more second semiconductor chips 634.

In a particular example, the first semiconductor chip may be configured to buffer address information, or in one example, a command signal, an address signal, and a clock signal that are transmitted to one or more second semiconductor chips. For example, the first semiconductor chip 632 may include a buffer that implements a plurality of active elements to provide a buffering function in transmitting signals to another device, such as one or more second semiconductor chips 634, Chip. Thus, the one or more second semiconductor chips may be a reduced function chip that has a memory storage array, but among other things can bypass circuits common to DRAMs such as buffer circuits, decoders or predecoders, or word line drivers. In that case, the first chip 632 can function as a " master " chip in the stack and can control the operation in each second semiconductor chip 634. In a particular example, the second semiconductor chip may be configured not to perform the buffering function. In that case, the stacking arrangement of the first and second semiconductor chips may be such that the buffering function required in the microelectronic package can be performed by the first semiconductor chip and can not be performed by any of the second semiconductor chips in the stacked arrangement .

In any of the embodiments described herein, one or more semiconductor chips may be implemented in one or more of the following technologies: DRAM, NAND flash memory, RRAM (resistive RAM or resistive random access memory), static random access memory (SRAM), phase-change memory (PCM), magnetoresistive random access memory, such as those capable of implementing a tunnel junction device, spin-torque RAM, or Content-addressable memory, and the like.

Figure 10 shows that one or more second semiconductor chips 634 are positioned in the direction of the thickness 652 of the first semiconductor chip 632 between the first and second opposing surfaces 638 and 642 of the first semiconductor chip 632 6 illustrates a microelectronic package 600 according to a particular example, which is electrically connected to a first semiconductor chip 632 by an extended through silicon via (TSV) 10, in one example, the TSV 650 is positioned between the element contacts (not shown) of the first semiconductor chip 632, such as by traces 654 extending along the surface 638 of the first semiconductor chip 632 636. < / RTI > Although any electrical connection between the first semiconductor chip and the second semiconductor chip can be made in this way, this connection is well suited for power and ground redistribution to the first and second semiconductor chips.

A signal, which is then reproduced by a first semiconductor chip 632 acting as a buffer element, and then transmitted to one or more second semiconductor chips, may be routed, for example, via a TSV connected to an internal circuit. As further shown in FIG. 10, the microelectronic package may also include a spinneret silicon via 650 that extends partially or wholly through one or more of the second semiconductor chips 634. TSV 650 does not directly connect to substrate 602, but instead may be terminated on a circuit included in semiconductor chip 632. [

11A shows a microelectronic package 700 according to a modification of the embodiment shown in FIG. In this case, the first semiconductor chip 732 is interconnected with the substrate 702 in the same manner as described above with reference to Fig. However, one or more second semiconductor chips 734 are electrically interconnected with the first semiconductor chip 732 through wire bonds.

In the example shown in FIG. 11A, the second semiconductor chip 734 is positioned so that its front side and contacts 731 thereon face upward, i.e., away from the first semiconductor chip 732. However, in another variation shown in FIG. 11B, another way in which the first and second semiconductor chips 832 and 834 are mounted together in the microelectronic package is that each of the second semiconductor chips 834 has its front side And the contact 831 are directed downward, that is, toward the substrate 602. The contacts 831 may be electrically connected to the corresponding contacts 841 on the front surface 838 of the first semiconductor chip 832 through the wire bonds 836. [ In this case, the contact 841 may be electrically connected to the element contact 636 on the first semiconductor chip 832, such as by a trace 838 extending along the front surface 838 of the first semiconductor chip 832 And the connection between the element contact 636 and the substrate contact 640 is made as described in connection with FIG.

12 illustrates a microelectronic package according to a further variation of the embodiment described above with reference to FIG. 10, wherein the connection between the contacts of one or more second semiconductor chips 934 and the first semiconductor chip 932 is a micro- May include traces 936 that extend along one or more edges of the electronic component 930, that is, along the edges of the semiconductor chips 932 and 934 in the microelectronic component. The electrical connection between the semiconductor chips 932 and 934 may further include traces 938 and 940 extending along the entire surface of the first semiconductor chip 932 and the second semiconductor chip 934, respectively. As shown further in Fig. 12, the front side 942 of the second semiconductor chip may be directed upwardly away from the substrate 602, or may be directed downward toward the substrate 602. 10 and 11A), the TSV in the first semiconductor chip 932 may extend partially or entirely through the thickness of the first semiconductor chip 932 or may extend through the first semiconductor chip 932, Some of the TSVs in the semiconductor chip 932 may partially extend through the thickness of the semiconductor chip while another TSV may extend through the entire thickness of the first semiconductor chip 932. [

13A shows a second semiconductor chip 954 having a contact 946 that faces a corresponding contact 948 on a face 950 of a first semiconductor chip 952 and contacts 946 and 948 are metal, To form a flip chip connection between the first and second semiconductor chips 952 and 954 to form a flip chip connection between the first and second semiconductor chips 952 and 954, such as through a bond metal or other electrically conductive material, in accordance with another variant of the embodiment described above with respect to FIG. Lt; / RTI > package.

13B illustrates a modification of the microelectronic package shown in FIG. 13A. Unlike the package shown in FIG. 13A, a semiconductor chip 964, which may be configured to reproduce or at least partially decode address information or other information, such as to reproduce a signal for transmission to another semiconductor chip in a package, Is not located adjacent to the first surface 108 of the first portion 902 of the first housing. Rather, in this case, the semiconductor chip 964 may be placed in a position in the package that is placed over one or more other semiconductor chips. 13B, the semiconductor chip 964 is at least partially placed on the semiconductor chip 962 disposed adjacent to the first surface 108 of the substrate 902, and is disposed on the semiconductor chip 962 Or at least partially over semiconductor chips 963A, 963B that are placed over semiconductor chip 962 at least partially.

In one example, semiconductor chips 962, 963A, 963B may include a memory storage array. As in the above example, these semiconductor chips 962, 963A, 963B can be used to store data to be written to such semiconductor chips, data read from such semiconductor chips, or both such data to be written and data to be read, Each of the circuits configured to buffer, such as storing, can be integrated. Alternatively, the semiconductor chips 962, 963A, 963B may be further limited in functionality, and may be configured to temporarily store both data to be written and data to be read from such semiconductor chips, It may be necessary to use it with other chips.

The semiconductor chip 964 is electrically connected to the first surface 108 of the substrate 902 via an electrically conductive structure such as TSVs 972a and 972b (collectively TSV 972) Lt; RTI ID = 0.0 > 904 < / RTI > and a second terminal 906 are disposed. An electrically conductive structure such as TSV 972 may be formed on semiconductor chip 964 through contact 938 on semiconductor chip 964 and along face 943 of semiconductor chip 964 or on opposite face 931 of semiconductor chip 963A Or electrically connected to the semiconductor chip 964 via a conductor (not shown) extending along both the surface 943 of the semiconductor chip 964 and the opposing face 931 of the semiconductor chip 963A . As indicated above, the semiconductor chip 964 may be configured to reproduce or at least partially decode the signal or information received via the conductive structure, e.g., TSV 972, such as TSV 972a, 972b, Or at least partially decoded signals or information to other chips in a package, such as semiconductor chips 962, 963A, 963B.

13B, the semiconductor chips 962, 963A, 963B may include a plurality of through silicon vias (TSVs) 972, 974, 976 that can extend one, two, three or more such semiconductor chips To the semiconductor chip 964 and can be electrically connected to each other. Each such TSV may be electrically connected to wiring in a package, such as a conductive pad or trace of two or more semiconductor chips, for example, semiconductor chips 962, 963A, 963B, and 964. In a particular example, a signal or information may be transmitted from the substrate 902 to the semiconductor chip 964 along a first subset 972A of the TSV and the signal or information may be transmitted along a second subset 972B of the TSV And transferred from the semiconductor chip 964 to the substrate. In one embodiment, at least a portion of the TSV 972 may be configured to cause signals or information to be transmitted in either direction between the semiconductor chip 964 and the substrate 902, depending on the particular signal or information. In one example (not shown), the through silicon vias may be electrically connected to each of these semiconductor chips extending through the respective through silicon vias, but the thickness of all the semiconductor chips 962, 963A, 963B Lt; / RTI >

13B, a heat sink or heat spreader 968, which may include a plurality of fins 971, may be formed through a thermally conductive material 969, such as a thermal adhesive, thermally conductive grease, or solder, Such as the backside 933 of the semiconductor chip 964, as shown in FIG.

The microelectronic assembly 995 shown in Figure 13B is a memory module capable of transferring a specified number of data bits per cycle onto or from the microelectronic package via the first and second terminals provided on the substrate Lt; / RTI > For example, the microelectronic assembly may include 32 data bits, 64 data bits, or 96 data bits from an external component, such as a circuit panel, which may be electrically connected to the first terminal 904 and the second terminal 906, And the like. In another example, the number of bits transmitted per cycle to or from a package may be different, such as 36 bits, 74 bits, or 108 bits, for example, when the bits transmitted and transferred from the package include error correction code bits Bit number. Other data widths than those specifically described herein are also possible.

14, 15A, and 15B illustrate a microelectronic package 1100 according to another variation of one or more of the embodiments described above. 14, package 1100 includes first and second microelectronic elements 1130 and 1131, each microelectronic element having a first surface 1120 and a second surface 1120 on a first surface 1120 of substrate 1102, And has contacts 1138 that are facing and joined to contacts 1140. Several of the substrate contacts 1140 are then electrically connected to the first terminals 1142 in the central region 1112 of the second surface 1110, such as through the electrically conductive traces 1144. In some embodiments, some of the substrate contacts 1138 may instead be electrically connected to the second terminal 1162 in one or more peripheral regions 1164 of the second surface.

This and other embodiments incorporate more than one microelectronic element herein, as described above. A plurality of chip packages may be fabricated by placing the chips therein electrically and mechanically through an array of terminals, such as a ball grid array, a land grid array, or a pin grid array, It is possible to reduce the amount of area or space required for connection to a circuit panel, such as a printed wiring board, which can be connected. Such a connection space is typically particularly limited in a small or portable computing device such as a " smart phone " or a handheld device such as a tablet that combines the functionality of a personal computer with, for example, a wireless connection to a wider world. The multi-chip package is particularly useful for mass production of relatively inexpensive memories available for the system, such as, for example, advanced high performance dynamic random access memory (DRAM) chips on DDR3 type DRAM chips or subsequent chips .

In certain cases, the amount of area of the circuit panel required to connect the multi-chip package to the circuit panel may be such that at least some signals are moved along two or more of the chips in the package along their course, Lt; RTI ID = 0.0 > a < / RTI > Therefore, in the example illustrated in Figs. 14, 15A, and 15B, the corresponding contacts of a plurality of chips in the package may include a component external to the package, such as a printed circuit board, an external microelectronic element, A single common electrode of the package configured to be connected to the first electrode.

The central region 1112 of the substrate surface 1110 has a width 1154 that is no greater than 3.5 times the minimum pitch 1152 between any two adjacent columns of terminals 1142 on the package, , And each of the two adjacent columns has a plurality of terminals therein.

An axial surface 1150 extending in a direction orthogonal to the plane of the microelectronic element extends in each column that includes a plurality of element contacts and extends in the direction of the element contacts of the first and second microelectronic elements 1130, Extends in the same first direction that is centered among all the columns 1138. The axial plane intersects the central region of the substrate in a direction perpendicular to the surface 1110 (extends through the central region). In one example, the facet can intersect the substrate along a line centered between adjacent edges 1134, 1135 of the microelectronic elements 1130, 1131. 15A and 15B, one or more columns of the first terminal 1142 are aligned with areas of the package between adjacent edges 1134 and 1135 of the first and second microelectronic elements, as shown in the figure. One or more of the columns of the first terminal 1142 may be disposed at a portion of the central region or at least one of the faces 1136 of the first and second microelectronic elements 1130 and 1131, It can be placed on the surface. It does not need to be more than one column 1142 of the terminals in the central region, as in the above embodiment. Typically, there will be only four columns 1142 of terminals in the central region. 14, the surfaces 1136 of the first and second microelectronic elements may extend within a single plane 1146 parallel to the first surface 1120 of the substrate 1102.

16A and 16B are diagrams showing a microelectronic package 1200 according to a modification to the embodiment shown in Figs. 14, 15A and 15B, in which microelectronic package 1100 (Fig. 14 In addition to the first and second microelectronic elements 1230 and 1231 having an arrangement and electrical interconnection in the same package 1200 as described above with respect to the first and second microelectronic elements 1230,125, (1233, 1235). The third and fourth microelectronic elements may each employ a greater number of active elements to provide memory storage array functionality than any other function. Similar to the first and second microelectronic elements, the third and fourth microelectronic elements 1233 and 1235 may be disposed on the first surface 1120 of the substrate (also shown in FIG. 14 and is electrically interconnected with a terminal 1242 of the package via an element contact 1238 associated therewith.

The first terminal 1243 of the microelectronic package may be disposed in the columns 1242 in the central region 1254 having a width not greater than 3.5 times the minimum pitch between the columns of the terminals as described above. As further shown in Figure 16A, the facet 1250 is mounted on all of the columns 1238 of the element contacts on the faces 1236 of the first, second, third and fourth microelectronic elements in the package 1200 Parallel and centered therebetween. In the example as shown in FIG. 16A, the axial surface 1250 extends in a first direction parallel to the direction in which the column 1242 including the first terminal extends.

The surfaces 1236 of the microelectronic elements 1230, 1231, 1233 and 1235 are arranged such that all of the surfaces 1236 are in a common plane, that is, May be arranged in the package 1200 to extend within a single plane, such as a single plane 1146 as shown in Fig.

16B illustrates a possible signal assignment of a terminal on package 1200 where the first terminal is located in one or more columns 1242 of the central region and the second terminal 1244 is located on the peripheral edges 1260, 1261, 1262, and 1263, respectively. In this case, some of the second terminals may be placed in the same grid as the grid 1270, and some of the second terminals may be placed in the same grid as the grid 1272. In addition, some second terminals may be located at a location within the grid, such as grid 1274, and some second terminals may be located at a location within grid 1276.

16B, the signal class assignment of the second terminal in the grid 1274 may be symmetric with respect to the vertical axis 1250, and the signal of the second terminal in the grid 1276, The class assignments may be symmetric with respect to the vertical axis 1250. As used herein, the two signal class assignments may be symmetric with respect to each other, even if the numerical indices in the class are different if the signal assignments are of the same class assignment. An exemplary signal class assignment may include a data signal, a data strobe signal, a data strobe complement signal, and a data mask signal. In a particular example, at grid 1274, a second terminal with signal assignments DQSH # and DQSL # is connected to a vertical axis (" DQSH # ") for its signal class assignment, which is the date strobe complement, even if these second terminals have different signal assignments 1250).

As shown in Figure 16B, the assignment of the data signal to the spatial location of the second terminal on the microelectronic package, such as for the data signals DQ0, DQ1, ... is modulo-X symmetric with respect to the vertical axis 1250 -X symmetry). The modulo-X symmetry is such that one or more pairs of the first and second packages are mounted opposite to the circuit panel and the circuit panels are mounted on the second terminals of the first and second packages in each oppositely packaged package pair Can help maintain signal integrity in the assembly 300 or 354 as shown in Figures 7C and 7D, which electrically connect the corresponding pairs. When the signal assignment of the terminals has a " modulo-X symmetry " with respect to the axis, the terminals carrying signals with the same number " modulo-X " are arranged at symmetrical positions with respect to the axis. Thus, in this assembly 300 or 354 as in Figures 7c and 7d, the modulo-X symmetry is such that the terminal DQ0 of the first package is the second number with the same number module X (X is 8 in this case) So that the electrical connection can be made through the circuit panel so that it can be electrically connected to the terminal DQ8 of the package via the circuit panel so that the electrical connection is essentially made through the thickness in a straight line direction, Lt; / RTI > direction.

In one example, " X " may be a number 2n (n squared of 2), where n may be greater than or equal to 2, or X may be 8 x N, Thus, in one example, X is equal to the number of bits in a half-byte (4 bits), bytes (8 bits), multiple bytes (8 x N, N is 2 or more), words (32 bits) You may. In this manner, in one example, when there is a modulo-8 symmetry as shown in Fig. 16B, the signal assignment of the package terminal DQ0 in the grid 1274 configured to carry the data signal DQ0, Lt; RTI ID = 0.0 > DQ8 < / RTI > The same is true for the signal assignments of the package terminals DQ0 and DQ8 in the grid 1276. [ 16B, the signal assignments of the package terminals DQ2 and DQ10 in the grid 1274 have a modulo-8 symmetry with respect to the vertical axis, and the same applies to package terminals in the grid 1276. [ A modulo-8 symmetry as described herein may appear at grids 1274 and 1276 for each signal assignment of package terminals DQ0 through DQ15.

Although not shown, the modulo number " X " may be a number other than 2n (the nth power of 2) and may be any number greater than two. Thus, the module number X on which the symmetry is based may depend on how many bits are present in the data size at which the package is to be constructed or configured for which data size. For example, when the data size is 10 bits instead of 8, the signal assignment may have a -10 symmetry with the module. When the data size has an odd number of bits, the module number X may have this number.

17A and 17B illustrate a microelectronic package 1300 according to a variation of the embodiment 1200 described above with reference to FIGS. 16A and 16B, which package includes a column (not shown) Includes a substrate surface 1310 having a central region 1312 in which a plurality of spacers 1341 are disposed. As can be seen in these figures, the first and second microelectronic elements 1330 and 1331 are arranged in a position in the column 1338 in which element contacts on the microelectronic elements extend in the same first direction 1342 Are arranged on the substrate 1302 in a manner similar to the arrangement of the microelectronic elements 1130 and 1131 of the microelectronic package 1100 (Figs. 14, 15A and 15B). However, as shown in FIG. 17A, the third and fourth microelectronic elements 1332 and 1333 are arranged in a different direction 1344 across the first direction 1342 than the sides of the microelectronic elements 1332 and 1333, Which is located at a position in the column 1340 that extends along the column.

As further shown in Figures 17A and 17B, each of the microelectronic elements 1330, 1331, 1332, 1333 typically includes two elements extending in the same direction as one or more columns of contacts on each microelectronic element One parallel edge 1360 and two second parallel edges 1362 extending in a direction transverse to the direction in which the first edge extends. In some cases, the first edge 1360 of each microelectronic element may have a length greater than the second edge 1362 of such microelectronic element. However, in other cases, the second edge 1362 may have a length greater than the first edge 1360. In the particular package shown in FIG. 17A, a first edge 1360 of any one of the microelectronic elements of the microelectronic elements 1330, 1331, 1332, 1333, Plane 1370 intersects edge 1360 of another microelectronic element in package 1300. 17A, a plane 1370 including an edge 1360 of the microelectronic element 1333 extends in the direction of reference numeral 1344 and intersects the edge 1360 of the microelectronic element 1330 in the package do. In the example shown in Figure 17A, the plane 1370 intersects the edge 1360 of only one other microelectronic element in the package. The microelectronic element includes a first edge 1360 of any microelectronic element of the microelectronic elements 1330,1331,1332,1333 and a plane 1370 perpendicular to the plane of the microelectronic element is disposed in the package & 1300) of the microelectronic element (1300).

In addition, as further shown in Fig. 17A, the central region 1312 may be further limited. 17A shows a minimum rectangular region 1372 on the surface 1310 of the substrate 1302 that will receive the microelectronic elements 1330, 1331, 1332, 13333 as disposed on the substrate surface 1310. In particular, , And none of the first, second, third and fourth microelectronic elements 1330, 1331, 1332, 1333 extend beyond the rectangular region. In the microelectronic package 1300 shown in FIGS. 17A and 17B, the central region 1312 does not extend beyond any edge of its rectangular region 1372. 17B shows a possible arrangement of the terminals in the microelectronic package 1300 in which the first terminals 1341 are disposed in a central region 1312 and the central region 1312 is located at an opposite, 1316, and 1318, that is, in a direction orthogonal to the mutually opposite edges, spans no more than 3.5 times the minimum pitch between the two closest adjacent columns of the terminals on the package. The perimeter area occupies the remaining area of the surface 1310 of the substrate 1302 and extends over the widths 1356 and 1357 between the edges of the central area and the opposite edges 1316 and 1318 of the package, respectively.

18A illustrates a microelectronic package 1400 in accordance with a variation of one or more of the embodiments described above. In this case, the substrate may be omitted so that the microelectronic package 1400 may be in the form of a microelectronic element 1430 having a packaging structure including an electrically conductive redistribution layer overlying the front surface 1428 of the microelectronic component 1430 . The redistribution layer has electrically conductive metallized vias 1440 that extend through the dielectric layer 1442 of the package to the contacts 1438 of the microelectronic element. The redistribution layer may include traces 1448 that are in electrical connection with the terminals 1446 and the terminals 1446 and may include terminals 1446 through the metallized vias 1440 or through the metallized vias 1440 and electrical And is electrically connected to the contacts 1438, such as through the conductive traces 1448. In this case, the package may be referred to as a " wafer-level package having a redistribution layer thereon ".

18B illustrates that one or more columns 1450 of the second terminal may be disposed on regions of the dielectric layer 1442 that extend past one or more edges 1432 and 1434 of the microelectronic element 1430 A microelectronic package 1410 similar to the microelectronic package 1400 is shown. In this case, the package 1410 may be referred to as a " fan-out wafer-level package having a redistribution layer thereon ".

Each of the above-described embodiments and modifications may likewise be applied to the package shown in FIG. 18A or 18B, and the above-described assembly shown and described above with reference to FIG. 7C may incorporate the microelectronic package shown in FIG. 18A or 18B .

The above-described structure can be utilized in the construction of various electronic systems. For example, as shown in FIG. 19, a system 1500 according to another embodiment of the present invention includes a microelectronic package or structure 1506 as described above with other electronic components 1508 and 1510. In the illustrated example, the component 1508 may be a semiconductor chip or a microelectronic package, while the component 1510 is a display screen, but any other component may be used. Of course, although only two additional components are shown in Fig. 19 for clarity of illustration, the present system may include any number of such components. The structure 1506 as described above may be, for example, a microelectronic package as described above in connection with any of the embodiments of the foregoing embodiments. In other variations, more than one package may be provided, and any number of such packages may be used. The package 1506 and the components 1508 and 1510 are mounted on a common housing 1501 schematically shown by dotted lines and are electrically interconnected with each other as required to form the desired circuit. In the illustrated example system, the system includes a circuit panel 1502, such as a flexible printed circuit panel or circuit board, which is shown only in FIG. 19 and includes a plurality of conductors 1504 ). However, this is only an example, and any suitable structure for achieving electrical connection can be used. The housing 1501 is shown as a portable housing of the type usable, for example, in a cellular telephone or a personal digital assistant (PDA), and the screen 1510 is exposed at the surface of the housing. Where the structure 1506 includes a photosensitive element such as an imaging chip, a lens 1511 or other optical device may be provided to route light to the structure. In addition, the simplified system shown in Fig. 19 is for illustrative purposes only, and other systems, including systems commonly considered as fixed structures such as desktop computers, routers, etc., can be configured using the above-described structure.

The various features of the above-described embodiments of the invention may be combined in ways other than those specifically set forth above without departing from the scope or spirit of the invention. The present invention includes all such combinations and variations of the embodiments of the invention described above.

Claims (29)

In a microelectronic assembly,
A circuit panel having first and second surfaces opposite each other and panel contacts on each of the first and second surfaces; And
And first and second microelectronic packages having terminals each electrically connected to the panel contacts at the first and second surfaces, respectively,
/ RTI >
The circuit panel electrically interconnecting at least some of the terminals of the first microelectronic package with at least some of the corresponding terminals of the second microelectronic package,
Each of said first and second microelectronic packages comprising:
A microelectronic element that implements a greater number of active elements to provide memory storage array functionality than the number of active elements for any other function, wherein the microelectronic element comprises one or more columns of element contacts Wherein each column extends in a first direction along a surface of the microelectronic element and an axial plane perpendicular to the surface of the microelectronic element extends along a line extending in the first direction, A microelectronic element intersecting a face of the microelectronic element and being centered relative to one or more columns of the elementic contact;
A substrate having opposing first and second surfaces and a plurality of substrate contacts connected to the element contacts at the first surface facing the element contacts; And
A plurality of parallel columns of terminals extending in a first direction at a second surface of the substrate, the terminals being electrically connected to the substrate contacts and configured to connect the microelectronic package with a component external to the microelectronic package , A plurality of parallel columns
/ RTI >
Wherein the terminal comprises a first terminal exposed in a central region of a second surface of the substrate and the first terminal is an available addressable memory location of a memory storage array in the microelectronic element. And to communicate address information usable by the circuitry in the package to determine an addressable memory point among all of the addresses,
Wherein the central region has a width in a second direction along a second surface of the substrate across the first direction and wherein the width of the central region is at least equal to a minimum between any two adjacent columns of parallel columns of the terminal Not more than 3.5 times the pitch, the axial plane intersecting the central region,
Microelectronic assembly. The method according to claim 1,
Wherein at least some of the first terminals of each of said first and second microelectronic packages are disposed at a location within a grid on each of said microelectronic packages and said grid is parallel to said first and second circuit panel surfaces Aligned within one ball pitch of one another in one x and y orthogonal directions. 3. The method of claim 2,
Wherein the grid is aligned with each other in the x and y orthogonal directions such that at least some of the first terminals of the grids of each of the first and second microelectronic packages coincide with each other. 3. The method of claim 2,
Each position of each of said grids being occupied by one of the terminals. 3. The method of claim 2,
Wherein at least one position of the at least one grid is not occupied by the terminals. 3. The method of claim 2,
Wherein at least half of the locations of the grid in the first and second microelectronic packages are aligned with one another in x and y orthogonal directions parallel to the first surface of the circuit panel. 3. The method of claim 2,
Wherein a first terminal disposed at a location within the grid of each microelectronic package is configured to deliver all of the available address information by circuitry within each microelectronic package to determine an addressable memory location, . 3. The method of claim 2,
Wherein a first terminal disposed at a location within a grid of each micro-package is configured to convey information controlling an operating mode of the micro-electronic component of each micro-electronic package. 9. The method of claim 8,
Wherein a first terminal located at a location within the grid of each microelectronic package is configured to transfer all of the command signals transmitted to each of the microelectronic packages and wherein the command signal comprises a write enable signal, Signal, and a column address strobe signal. 3. The method of claim 2,
Wherein a first terminal disposed at a location within the grid of each of the microelectronic packages is configured to deliver a clock signal to be transmitted to the microelectronic package, And to use the clock signal to sample the signal. 3. The method of claim 2,
Wherein a first terminal disposed at a location within the grid of each of the microelectronic packages is configured to deliver all of the bank address signals transmitted to each of the microelectronic packages. The method according to claim 1,
The length of a stub of at least one of the electrical connections between one of the first terminals of the first microelectronic package and a corresponding one of the first terminals of the second microelectronic package, Is less than seven times the minimum pitch of the first terminal on the electronic package. 13. The method of claim 12,
Wherein at least some of the electrical connections through the circuit panel between the first terminal of the first microelectronic package and the first terminal of the second microelectronic package have an electrical length of the thickness of the circuit panel. 13. The method of claim 12,
The total length of the conductive elements connecting each pair of electrically connected first and second panel contacts exposed at the first and second surfaces of the circuit panel is less than seven times the minimum pitch of the panel contacts, Electronic assembly. The method according to claim 1,
Wherein the circuit panel includes a bus having a plurality of conductors configured to communicate at least some of the address information transmitted to each of the microelectronic packages, the conductors extending in a first direction parallel to the first and second surfaces , A microelectronic assembly. 3. The method of claim 2,
Wherein a first terminal of each of the microelectronic packages is disposed at a location within a column of a grid on each of the microelectronic packages, the circuit panel being electrically connected to the circuitry to which the terminals of the first and second microelectronic packages are electrically connected Wherein the microelectronic assembly includes only one routing layer for routing all of the address information between the connection sites on the panel and the different connection sites to which the terminals of the at least one third microelectronic package are electrically connected. 17. The method of claim 16,
Wherein said only one routing layer provides routing for a command signal, an address signal, a bank address signal, and a clock signal on a command-address bus of a circuit panel between said connection sites. The method according to claim 1,
Wherein the circuit panel includes an element having a coefficient of thermal expansion (CTE) less than 12 parts per million per degree Celsius, wherein panel contacts at the first and second surfaces are connected to vias extending through the element The microelectronic assembly. 19. The method of claim 18,
Wherein the element essentially comprises a semiconductor, glass, ceramic or liquid crystal polymer material. 12. A memory module comprising:
Circuit panel; And
A plurality of microelectronic packages
Wherein the microelectronic package is electrically connected to the circuit panel through a terminal of each microelectronic package to transmit a signal to each microelectronic package and to transmit a signal from each microelectronic package, ,
Each microelectronic package comprising:
A microelectronic element for implementing a greater number of active elements to provide a memory storage array function than the number of active elements for any other function, the microelectronic element having at least one column of element contacts, Wherein a column extends in a first direction along a face of the microelectronic element and an axial face perpendicular to the face of the microelectronic element intersects the face of the microelectronic element along a line extending in the first direction, A microelectronic element adapted to be centered relative to one or more columns of the contact;
A substrate having opposing first and second surfaces and a plurality of substrate contacts connected to the element contacts at the first surface facing the element contacts; And
A plurality of parallel columns of terminals extending in a first direction at a second surface of the substrate, the terminals being electrically connected to the substrate contacts and configured to connect the microelectronic package with a component external to the microelectronic package , A plurality of parallel columns
/ RTI >
Wherein the terminal comprises a first terminal exposed in a central region of a second surface of the substrate and the first terminal is an available addressable memory location of a memory storage array in the microelectronic element. And to communicate address information usable by the circuitry in the package to determine an addressable memory point among all of the addresses,
Wherein the central region has a width in a second direction along a second surface of the substrate across the first direction and wherein the width of the central region is at least equal to a minimum between any two adjacent columns of parallel columns of the terminal Not more than 3.5 times the pitch, the axial plane intersecting the central region,
Memory modules. In a microelectronic assembly,
A circuit panel having first and second surfaces opposite each other and panel contacts on each of the first and second surfaces; And
A first and a second microelectronic package having terminals mounted to the panel contacts at the first and second surfaces, respectively,
/ RTI >
The circuit panel electrically interconnecting at least some of the terminals of the first microelectronic package with at least some of the corresponding terminals of the second microelectronic package,
Each of said first and second microelectronic packages comprising:
A microelectronic element for implementing a greater number of active elements to provide a memory storage array function than the number of active elements for any other function, the microelectronic element having at least one column of element contacts, Wherein a column extends in a first direction along a face of the microelectronic element and an axial face extending in a direction perpendicular to the face of the microelectronic element intersects a face of the microelectronic element along a line extending in the first direction And is adapted to be centered relative to one or more columns of the element contacts; And
A dielectric layer overlying a surface of the microelectronic element and having a surface facing away from a surface of the microelectronic element;
A plurality of terminals exposed at a surface of the dielectric layer, wherein at least some of the terminals are electrically connected to traces extending along the dielectric layer and through the metallized vias extending from the traces and in contact with the element contacts, Wherein the terminal is arranged in a plurality of parallel columns and is configured to connect the microelectronic package to at least one component external to the microelectronic package, the terminal being disposed at a location within at least one column in a central region Wherein the first terminal comprises a first terminal and wherein the first terminal is located within the microelectronic package to determine an addressable memory location among all of the available addressable memory locations of the memory storage array in the microelectronic element. Used by circuit A plurality of terminals < RTI ID = 0.0 >
≪ / RTI >
/ RTI >
Wherein the central region is not wider than 3.5 times the minimum pitch between any two adjacent columns of the terminal and the axial plane intersects the central region,
Microelectronic assembly. 22. The method of claim 21,
Wherein at least some of the first terminals of each of the first and second microelectronic packages are disposed at a location in a grid on a respective microelectronic package, the grid comprising x and y parallel to the first and second circuit panel surfaces, Wherein a first terminal disposed at a location within each grid is arranged to transmit information controlling a mode of operation of the microelectronic component of each microelectronic package, . 23. The method of claim 22,
Wherein a first terminal located at a location within the grid of each microelectronic package is configured to transfer all of the command signals transmitted to each of the microelectronic packages and wherein the command signal comprises a write enable signal, Signal, and a column address strobe signal. 23. The method of claim 22,
Wherein at least some of the electrical connections through the circuit panel between the first terminals of the first microelectronic package and the second microelectronic package have an electrical length of the thickness of the circuit panel. 23. The method of claim 22,
The total length of the conductive elements connecting each pair of electrically connected first and second panel contacts exposed at the first and second surfaces of the circuit panel is less than seven times the minimum pitch of the panel contacts, Electronic assembly. As an electronic device,
Microelectronic package; And
One or more other electronic components electrically connected to the microelectronic package
The microelectronic package comprising:
A microelectronic element for implementing a greater number of active elements to provide a memory storage array function than the number of active elements for any other function, the microelectronic element having at least one column of element contacts, Wherein a column extends in a first direction along a face of the microelectronic element and an axial face perpendicular to the face of the microelectronic element intersects the face of the microelectronic element along a line extending in the first direction, A microelectronic element adapted to be centered relative to one or more columns of the contact;
A substrate having opposing first and second surfaces and a plurality of substrate contacts connected to the element contacts on the first surface facing the element contacts; And
A plurality of parallel columns of terminals extending in a first direction at a second surface of the substrate, the terminals being electrically connected to the substrate contacts and configured to connect the microelectronic package with a component external to the microelectronic package , A plurality of parallel columns
/ RTI >
Wherein the terminal comprises a first terminal exposed in a central region of a second surface of the substrate and the first terminal is an available addressable memory location of a memory storage array in the microelectronic element. And to communicate address information usable by the circuitry in the package to determine an addressable memory point among all of the addresses,
Wherein the central region has a width in a second direction along a second surface of the substrate across the first direction and wherein the width of the central region is at least equal to a minimum between any two adjacent columns of parallel columns of the terminal Is not greater than 3.5 times the pitch, and the axial plane intersects the central region. 27. The method of claim 26,
Further comprising a housing on which the microelectronic package and one or more other electronic components are mounted. 27. The method of claim 26,
Wherein the microelectronic package is a first microelectronic package and the electronic device further comprises a second microelectronic package. delete
KR1020147012162A 2011-10-03 2012-10-01 Stub minimization for assemblies without wirebonds to package substrate KR101901218B1 (en)

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US201261600361P 2012-02-17 2012-02-17
US61/600,361 2012-02-17
US13/439,354 US8629545B2 (en) 2011-10-03 2012-04-04 Stub minimization for assemblies without wirebonds to package substrate
US13/439,354 2012-04-04
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