KR101814843B1 - The printed circuit board and the method for manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device comprising a first insulating layer, a second insulating layer on the first insulating layer, a third insulating layer below the first insulating layer, a fourth insulating layer on the second insulating layer, 4 at least one via through the insulating layer, the via having a layered structure, the via comprising a first via layer through the first insulating layer, a second via layer extending through the second insulating layer and formed over the first via layer A second via layer, a third via layer formed through the third insulating layer and below the first via layer, a fourth via layer extending through the fourth insulating layer and formed over the second via layer, A plurality of adhesive layers respectively formed between the first to fourth via layers
Wherein the first and third via layers are symmetrically formed with the second and fourth via layers, wherein the first and third via layers have the same shape, and the second and fourth via layers For the same printed circuit board. Therefore, the adhesion between the copper layer and the insulating layer is improved, and the vias for interlayer circuit connection between the plurality of insulating layers are etched without proceeding to the laser or polishing process, thereby improving the processability and reducing the cost.

Description

[0001] The present invention relates to a printed circuit board and a method of manufacturing the same,

The present invention relates to a printed circuit board and a method of manufacturing the same.

The circuit board includes a circuit pattern on an electrically insulating substrate, and is a substrate for mounting electronic components or the like.

In recent years, a thin film multilayer circuit board has been proposed. For this purpose, various attempts have been made to form a thinner support substrate capable of supporting a central insulation layer, that is, a bending in the process.

1 shows a conventional printed circuit board.

The conventional printed circuit board 10 has multilayered circuit patterns 4 and 5 formed between a plurality of multilayered insulating layers 1 and has vias 2 and 3 for connecting the circuit patterns 4 and 5 to each other, 3 are formed.

At this time, the vias 2 and 3 are formed by filling the conductive paste after the mechanical hole processing, or by hole-processing by the laser drilling method and plating or the like.

At this time, the via 2 formed by the conductive paste is applied when it is difficult to form the via 2 because of the large size of the via 2, but the via 2 formed by the conductive paste has a high electrical resistance, Reliability is poor.

On the other hand, the via 3 formed by laser drilling has an economical problem in that a hole process must be performed for each insulating layer 1 with respect to a plurality of insulating layers 1.

An embodiment provides a printed circuit board having a new structure and a method of manufacturing the same.

The embodiments provide printed circuit boards that form vias in a simple process and methods of making the same.

An embodiment includes a first insulating layer, a second insulating layer over the first insulating layer, and at least one via through the first and second insulating layers and having a layered structure, A first via layer passing through the insulating layer, a second via layer passing through the second insulating layer and formed on the first via layer, and an adhesive layer formed between the first and second via layers, 1 and the second via layer have different cross-sections.

Meanwhile, a method of manufacturing a printed circuit board according to an embodiment of the present invention includes the steps of forming a via layer in a via region of a plurality of bulk metal layers to form a via layer, filling a via hole of one of the bulk metal layers with a first insulating layer Forming an adhesive layer on the plurality of via layers of one of the bulk metal layers so as to align the via layers of the other bulk metal layer on the adhesive layer while filling the via holes with a second insulating layer Depositing a plurality of the bulk metal layers, and etching the bulk gold layer to expose the first and second insulating layers.

According to the present invention, the adhesion between the copper layer and the insulating layer is improved, and the use of the bulk copper improves the heat radiation characteristic.

In addition, the vias for interlayer circuit connection between a plurality of insulating layers are etched without proceeding to a laser or a polishing process, thereby improving the processability and reducing the cost.

1 is a cross-sectional view of a conventional printed circuit board.
2 is a cross-sectional view of a device chip package to which a printed circuit board according to an embodiment of the present invention is applied.
Figs. 3 to 16 are cross-sectional views showing a method for manufacturing the printed circuit board of Fig.
FIG. 17 is a cross-sectional view showing a device chip package using the printed circuit board of FIG. 2;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

In order to clearly illustrate the present invention in the drawings, thicknesses are enlarged in order to clearly illustrate various layers and regions, and parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification .

Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

The present invention provides a printed circuit board that does not use laser drilling during via hole formation.

Hereinafter, a heat radiation circuit board according to an embodiment of the present invention will be described with reference to FIGS. 2 to 16. FIG.

2 is a cross-sectional view of a package 100 to which a printed circuit board and a printed circuit board according to an embodiment of the present invention are applied.

Referring to FIG. 2, the device chip package 100 according to the present invention includes a printed circuit board and a device chip 200 mounted on the printed circuit board.

The printed circuit board includes a plurality of insulating layers 120, 150, 176 and 186, a plurality of vias passing between the plurality of insulating layers 120, 150, 176 and 186, and a coverlay 195 covering the vias. .

 The plurality of insulating layers 120, 150, 176 and 186 may include a first insulating layer 120 and a second insulating layer 150 formed on the first insulating layer 120, And third and fourth insulating layers 176 and 186 formed on upper and lower portions of the first and second insulating layers 120 and 150, respectively.

The first to fourth insulating layers 120, 150, 176, and 186 may include an epoxy-based insulating resin having a low thermal conductivity (about 0.2 to 0.4 W / mK) Imide-based resin. Also, the first to fourth insulating layers 120, 150, 176, and 186 may be formed of the same material or different materials.

In addition, the first to fourth insulating layers 120, 150, 176, and 186 are formed by filling between adjacent vias, and have different shapes in cross section depending on the shape of the vias.

The plurality of vias are spaced apart from each other and may be through vias penetrating from the upper surface to the lower surface of the printed circuit board.

Each via has a layered structure comprising a plurality of layers.

Each via comprises a first via layer 110 formed through the first insulating layer 120, a second via layer 140 through the second insulating layer 150 and aligned with the first via layer 110, And third and fourth via layers 170 and 180 formed through the third and fourth insulating layers 176 and 186 on the upper and lower portions of the first and second via layers 110 and 140 do.

In this case, the printed circuit board is described as being formed in a multi-layered structure having four insulating layers 120, 150, 176, and 186 so that the vias have four layered structures. Alternatively, Or a number of layers smaller than the number of the insulating layers 120, 150, 176, 186, so that the number of layers of the insulating layer 120, 150, 176, It may have the shape of the buried vias.

Hereinafter, the vias will be limited to having four layered structures.

The first via layer 110 is formed in a central region of the printed circuit board and may have a shape in which a cross section is expanded toward the bottom.

The second via layer 140 may extend from the top surface of the first via layer 110 and may have a shape in which the cross section is enlarged toward the top.

The third via layer 170 may be formed on the second via layer 140 and may have the same shape as the second via layer 140 and the fourth via layer 180 may be formed on the first via layer 110, And may have the same shape as the first via layer 110.

That is, the plurality of layered structures may be formed to be symmetrical with respect to the center region.

The first and fourth via layers 110, 140, 170, and 180 may be formed of the same material, and preferably, a material including copper, which is a conductive material having good heat dissipation.

Meanwhile, a plurality of adhesive layers 131, 161, and 191 may be formed between the respective layers of the vias.

The plurality of adhesive layers 131, 161, and 191 may be disposed between the first adhesive layer 131 and the second and third via layers 140 and 170 formed between the first and second via layers 110 and 140, The second adhesive layer 161 formed between the first and fourth via layers 110 and 180 and the third via layer 170 exposed on the upper surface of the printed circuit board and the lower surface of the printed circuit board And a third adhesive layer 191 formed on the exposed surface of the fourth via layer 180.

The plurality of adhesive layers 131, 161, and 191 may be formed of the same material, and may be formed of the same material as the via layer to adhere a plurality of via layers formed by different processes to each other.

That is, the adhesive layers 131, 161, and 191 may be formed of an alloy including copper.

The printed circuit board includes a cover layer 195 on the upper and lower surfaces and a portion of the via from the cover layer 195 is exposed to form pads 198 and 199.

The pads 198 and 199 may be formed of an alloy including a metal such as silver, gold, nickel, or palladium, and may include an inner lead 198 formed on a surface on which chips are to be formed, And an outer lead 199 formed.

A solder paste 220 is applied to the upper surface of the exposed vias and the device chip 200 is mounted on the solder paste 220.

The device chip 200 may include a semiconductor chip, a light emitting diode chip, or other driving chip, and is electrically connected to the inner lead 198 through the wire 210.

The device chip 200 is resin molded 230 on the printed circuit board to be protected from the outside.

Hereinafter, a method of manufacturing the printed circuit board of FIG. 2 will be described with reference to FIGS. 3 to 16. FIG.

First, as shown in Fig. 3, a bulk first metal plate 111 is prepared.

The bulk first metal plate 111 may be a copper plate having a thickness greater than the thickness of each layer of the via.

Next, except for a region where a via is to be formed, the first insulating groove 115 is formed by etching the via between the via and the via as shown in FIG.

The first insulation groove 115 may be formed by forming a resist pattern on the copper plate 111 and then wet-etching the copper plate 111, and may have a curved section.

Therefore, a protrusion forming the first via layer 110 is formed between the first insulation groove 115 and the first insulation groove 115.

6, holes corresponding to the first via layer 110 are formed in the first insulating layer 120, and then the first insulating layer 120 is pressed onto the first metal plate 111, The first insulating layer 120 is buried in the insulating trench 115.

Next, a first metal layer 130 is formed on the first via layer 110 and the first insulating layer 120, as shown in FIG.

The first metal layer 130 may be formed by aerosol deposition of copper. That is, the copper may be aerosolized by mixing with the gas, and then the first via layer 110 and the first insulation layer The first metal layer 130 is formed.

When aerosol deposition is performed in the formation of the metal layer 130, deposition at room temperature is possible without deposition at a high temperature.

Next, as shown in FIG. 8, the first adhesive layer 131 of FIG. 2 is formed by etching the first metal layer 130 so as to leave only the region above the first via layer 110.

At this time, the first metal layer 130 may be etched by wet etching after the resist pattern is formed. At this time, the first adhesive layer 131 may have a larger surface than the upper surface of the first via layer 110, Lt; RTI ID = 0.0 > 120 < / RTI >

Next, as shown in FIG. 9, the steps of FIGS. 2 to 4 are repeated to form a second insulating groove 145 in the second metal plate 141, and the first insulating groove 115 and the second insulating groove 145 The second insulating layer 150 is disposed so as to correspond to the second insulating groove 145 so that the first and second metal plates 111 and 141 are heated and pressed so that the shape of FIG. Is completed.

Next, as shown in FIG. 11, if both surfaces of the first and second metal plates 111 and 141 are etched until the first and second insulating layers 120 and 150 are exposed, the first and second via- Layers 110 and 140 are formed.

Next, as shown in FIG. 12, a second metal layer 160 is formed on the first and second via layers 110 and 140 and the exposed first and second insulating layers 120 and 150.

As shown in FIG. 13, the second metal layer 160 may be formed by etching a part of the second metal layer 160 to form the first and second via layers 110 and 140 The second adhesive layer 161 is formed.

The second adhesive layer 161 has a larger area than the first adhesive layer 131 due to the shape of the first and second via layers 140.

Next, the processes of Figs. 3 to 13 are repeated to form the multilayer structure of Fig.

14, a third via layer 170 is formed on the second via layer 140, a fourth via layer 180 is formed under the first via layer 110, A third adhesive layer 191 is formed on the exposed surfaces of the layer 110 and the fourth via layer 180.

The third adhesive layer 191 may have the same shape as the second adhesive layer 161 and have a region extending over the third and fourth insulating layers 186.

Next, a coverlay 195 is formed by exposing an area where the inner lead 198, the outer lead 199, and the device chip 200 are to be formed.

The coverlay 195 may be formed of a solder resist or a dry film.

Next, an inner lead 198 and an outer lead 199 are formed by plating the surface exposed to the coverlay 195. The inner leads 198 and the outer leads 199 may be formed of an alloy including a metal such as silver, gold, nickel, and palladium, and may be plated to have a multi-layer structure.

When the pads of the inner leads 198 and the outer leads 199 are formed as shown in FIG. 16, the printed circuit board is completed.

17, the solder paste 220 is applied to the mounting area of the device chip 200, the device chip 200 is mounted, and the device chip 200 and the inner When the leads 198 are electrically connected to each other, the device chip 200 package 100 is completed.

As described above, the formation of the vias through etching during the formation of the multilayer via of the printed circuit board having the multilayer insulating layer can reduce the cost, and the adhesive layer can be formed between the via layers to secure the adhesive force and the signal characteristics .

 While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Device chip package 100
Device chip 200
The insulating layer 120, 150, 176, 186
Coverlay 195

Claims (15)

A plurality of insulating layers including a first insulating layer, a second insulating layer on the first insulating layer, a third insulating layer on the second insulating layer, and a fourth insulating layer below the first insulating layer;
A first via layer passing through the first insulating layer and having a curved side, a second via layer disposed through the second insulating layer on the first via layer and having a curved side surface, A third via layer disposed through the third insulating layer and having a curved side surface and a fourth via layer disposed below the first via layer and disposed through the fourth insulating layer and having a curved side surface, A plurality of via layers having a mutually layered structure;
A first adhesive layer formed between the first and second via layers, a second adhesive layer formed between the second and third via layers and between the first and fourth via layers respectively, A third adhesive layer formed on the surface of the third via layer exposed on the upper surface of the fourth insulating layer, and a fourth adhesive layer formed on the surface of the fourth via layer exposed on the lower surface of the fourth insulating layer;
An inner lead disposed on the third adhesive layer;
An outer lead disposed under the fourth adhesive layer;
A solder paste disposed on the third insulating layer and the third adhesive layer and disposed in a formation region of the device chip; And
And a coverlay disposed on the third insulating layer and the third adhesive layer and exposing a formation region of the inner lead and the solder paste,
Wherein the first via layer to the fourth via layer are formed of the same metal material,
The first to fourth adhesive layers are formed of the same metal material as the first via layer,
Wherein the metallic material comprises copper,
Wherein the second adhesive layer, the third adhesive layer and the fourth adhesive layer have the same width and a width larger than the width of the first adhesive layer,
Wherein the first and fourth via layers are symmetrically formed with the second and third via layers, the first and fourth via layers have the same shape, and the second and third via layers have the same shape In addition,
The upper surface of the first via layer is located on the same plane as the upper surface of the first insulating layer,
The upper surface of the second via layer is located on the same plane as the upper surface of the second insulating layer,
The lower surface of the third via layer is located on the same plane as the lower surface of the third insulating layer,
The lower surface of the fourth via layer is located on the same plane as the lower surface of the fourth insulating layer,
The upper surface of the inner lead is located on the same plane as the upper surface of the solder paste and the upper surface of the cover lay,
In the solder paste,
A third adhesive layer disposed on the third adhesive layer and having a width larger than the width of the device chip,
Wherein the printed circuit board includes:
Wherein a cross section of the first via layer and the second via layer facing each other has an area smaller than a cross section of the third via layer and the fourth via layer,
Wherein the first to fourth via layers have a curved side surface connecting between both end faces. delete delete delete delete delete delete delete delete Forming via holes in the via regions of the first to fourth bulk metal layers to form first to fourth via layers each having a curved side surface,
Filling a first insulating layer in a via groove of the first bulk metallic layer,
Forming a first metal layer over the first via layer and the first insulating layer of the first bulk metal layer,
Etching the first metal layer to form a first adhesive layer in contact with the first via layer;
Depositing the first and second bulk metal layers on the first adhesive layer so that the second via layer of the second bulk metal layer is aligned and burying a second insulating layer in the via groove of the second bulk metal layer ,
Etching the first and second bulk metal layers to expose the first and second insulating layers,
Forming a second metal layer on the upper surface of the second via layer, the upper surface of the second insulating layer, the lower surface of the first insulating layer, and the lower surface of the first insulating layer, respectively;
Etching the second metal layer to form a second adhesive layer connected to the first via layer and the second via layer, respectively;
The third via layer of the third bulk metallic layer is arranged on the second adhesive layer on the second via layer and the third insulating layer is buried in the via groove of the third bulk metallic layer, ;
The fourth via layer of the fourth bulk metallic layer is arranged below the second adhesive layer below the first via layer and the fourth insulating layer is buried in the via groove of the fourth bulk metallic layer, Attaching a bulk metal layer;
Etching the third and fourth bulk metal layers to expose the third and fourth insulating layers,
Forming a third metal layer on the third via layer and the third insulating layer;
Forming a fourth metal layer below the fourth via layer and the fourth insulating layer;
Etching the third metal layer to form a third adhesive layer connected to the third via layer and etching the fourth metal layer to form a fourth adhesive layer connected to the fourth via layer;
Forming a coverlay exposing the formation area of the inner leads and the formation area of the device chips on the third insulating layer;
Forming an inner lead in the formation region of the inner lead exposed through the coverlay, the inner lead being connected to the third adhesive layer; And
Forming a solder paste in a formation region of the device chip exposed through the coverlay,
Wherein the second adhesive layer, the third adhesive layer and the fourth adhesive layer each have the same width and a width wider than the width of the first adhesive layer
Wherein said first and fourth via layers are symmetrically formed with said second and third via layers, wherein said first and fourth via layers have the same shape and said second and third via layers have the same shape In addition,
The upper surface of the first via layer is located on the same plane as the upper surface of the first insulating layer,
The upper surface of the second via layer is located on the same plane as the upper surface of the second insulating layer,
The lower surface of the third via layer is located on the same plane as the lower surface of the third insulating layer,
The lower surface of the fourth via layer is located on the same plane as the lower surface of the fourth insulating layer,
The upper surface of the inner lead is located on the same plane as the upper surface of the solder paste and the upper surface of the cover lay,
In the solder paste,
A third adhesive layer disposed on the third adhesive layer and having a width larger than the width of the device chip,
Wherein the first via layer and the second via layer have a smaller cross-section than the cross-section of the third via layer and the fourth via layer,
Wherein the first through fourth via layers have a curved side surface connecting both end surfaces. 11. The method of claim 10,
Wherein the forming of the via groove comprises wet etching the region except the via region. delete delete delete delete

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