KR101705369B1 - Method of controlling polarity of data voltage and liquid crystal display using the same - Google Patents

Abstract

The present invention relates to a polarity control method of a data voltage for adjusting a polarity of data voltages supplied to a liquid crystal display panel and a liquid crystal display using the same, Analyzing the degree of polarity balance of the input image in units of dots; A polarity pattern of a default polarity control signal in the I dot unit and a polarity pattern of an inverted polarity control signal generated in an inverted signal of the default polarity control signal and supplies data indicating the selected polarity pattern to the source drive IC ; And a control circuit for restoring the polarity control signal of the selected polarity pattern based on the data indicating the polarity pattern in the source drive IC, Polarity analog data voltages and outputting them to the data lines of the liquid crystal display panel.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of controlling polarity of a data voltage and a liquid crystal display using the same,

The present invention relates to a polarity control method of a data voltage for balancing a polarity of data voltages supplied to a liquid crystal display panel and a liquid crystal display using the same.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

Liquid crystal cells of a liquid crystal display display an image by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode. The liquid crystal display device is driven by an inversion method in which the polarity of the data voltage applied to the liquid crystal is periodically inverted in order to reduce the afterimage and prevent deterioration of the liquid crystal.

If the liquid crystal display device is driven in an inversion mode, the image quality of the liquid crystal display device may be deteriorated according to the correlation between the polarity of the data voltage charged in the liquid crystal cells and the data pattern of the input image. When the data of the problem pattern shown in FIGS. 1 and 2 is included in the input image, the polarities of the data voltages charged in the liquid crystal display panel are not balanced between the positive polarity and the negative polarity, have. In this case, the common voltage applied to the common electrode in the dominant polarity direction is shifted. When the common voltage is shifted, since the reference potential of the liquid crystal cells is fluctuated, the observer can feel flicker or smear in the image displayed on the liquid crystal display device.

Figs. 1 and 3 show data examples of a problem pattern in which image quality may be degraded when the liquid crystal display device is driven in a dot-inversion mode.

As shown in Fig. 1, a pattern in which pixel data (white) of white gradation and pixel data (black) of black gradation alternate in units of one pixel is referred to as a shutdown pattern. Each of the pixel data includes red subpixel data R, green subpixel data G, and blue subpixel data B, respectively. The method of detecting the shutdown pattern can count the shutdown pattern included in the input image and judge whether or not the shutdown pattern is in accordance with the count value. For example, in the method of detecting the shutdown pattern, the count value of the problem pixel counter is incremented by 1 when the N-th (N is a natural number) pixel data is white gradation pixel data and the (N + 1) th pixel data is black gradation pixel data When the count value is equal to or larger than a predetermined threshold value, the data of the input image is determined as a shutdown pattern. In order to recognize the shutdown pattern, as shown in FIG. 2, a maximum of (2 ³ -1) 2 = 14 patterns that can appear in six subpixels should be defined in advance, and a logic circuit for detecting each of the patterns need.

As shown in Fig. 3, a pattern in which pixel data (white) of white gradation and pixel data (black) of black gradation alternate in units of two pixels is called a smear pattern. Each of the pixel data includes red subpixel data R, green subpixel data G, and blue subpixel data B, respectively. The smear pattern detection method can count the smear pattern included in the input image and determine whether or not the pattern is a shutdown pattern according to the count value. For example, the smear pattern detection method is a method in which the Nth and (N + 1) -th pixel data are pixel data of white tones, and when the (N + 1) And the data of the input image is determined as a smear pattern when the count value is equal to or greater than a predetermined threshold value. In the case of a squared pattern, a maximum of (2 ⁶ -1) x 2 = 126 patterns that can appear in 12 subpixel data must be defined in advance, and a detection logic circuit for detecting each of the patterns is required Do.

The problematic patterns causing the shift of the common voltage (Vcom) are not limited to the shutdown pattern or the squared pattern. For example, as shown in Figs. 6 and 7, the problem pattern includes one-pixel data of a white gradation subpixel data (white) and a black gradation subpixel data.

Prior art has to predefine a large amount of basic patterns to define each of the problem patterns in order to recognize various types of problem patterns. Therefore, the conventional technique requires a large memory storage capacity for defining basic patterns, requires a logic circuit that compares the basic patterns with input patterns, and compares the results with a threshold value, resulting in high hardware complexity and high circuit cost . Further, in the related art, if the problem pattern is recognized, the polarity of the data voltage can be changed in a direction that suppresses the shift of the common voltage, and the polarity change point can not be applied to the next line data or the next frame data. The polarity conversion of the data voltage is equally applied to non-problematic patterns smaller than the threshold value.

In the polarity conversion method, there is a method of selecting either a horizontal 1 dot inversion (horizontal 1 dot inversion) or a horizontal 2 dot version depending on the problem pattern type. The version with the horizontal one dot converts the polarity of the data voltage charged in the liquid crystal cells of 4k (k is positive integer) to 4k + 4 dots arranged side by side on the same horizontal display line in the liquid crystal display panel as follows . (N is a positive integer) frame period, the polarity of the data voltage charged in the liquid crystal cell of 4k (k is a positive integer) + 1 dot is defined as positive (+), The polarity of the data voltage charged in the liquid crystal cell of 4k + 2 dots is negative (-), the polarity of the data voltage charged in the liquid crystal cell of the (4k + 3) The negative polarity of the data voltage charged in the liquid crystal cell of the liquid crystal cell is converted to negative (-). In the case of the horizontal one-dot version, the polarity of the data voltage charged in the liquid crystal cell of the (4k + 1) -th dot is negative (-) while the polarity of the data voltage charged in the liquid crystal cell of the The polarity of the data voltage charged in the liquid crystal cell of the (4k + 3) -th dot is set to the negative (-), the polarity of the data voltage charged in the liquid crystal cell of the (+), Respectively. Therefore, the version with the horizontal one dot is used to repeat the polarity of the data voltages charged in the liquid crystal cells arranged on the same horizontal display line in the liquid crystal display panel from "+ - + -" or "- + - +" .

The version with horizontal two dots converts the polarity of the data voltage charged in the liquid crystal cells of the 4k th to the 4k + 4th dots arranged side by side on the same horizontal display line in the liquid crystal display panel as follows. In a version with a horizontal 2-dot period, the polarity of the data voltage charged in the liquid crystal cell of the (4k + 1) -th dot is positive (+) while the polarity of the data voltage charged in the liquid crystal cell of the (-), the polarity of the data voltage charged in the liquid crystal cell of the (4k + 3) th dot is negative (-), the polarity of the data voltage charged in the liquid crystal cell of the +). In a version with a horizontal 2-dot period, the polarity of the data voltage charged in the liquid crystal cell of the (4k + 1) -th dot is negative (-) while the data charged in the liquid crystal cell of the The polarity of the data voltage charged in the liquid crystal cell of the (4k + 3) th dot is set to the positive (+), and the polarity of the data voltage charged in the liquid crystal cell of the And negative polarity (-), respectively. Therefore, the version with the horizontal two-dot repetition of "+ - - +" or "- + + -" repeats the polarities of the data voltages charged in the liquid crystal cells arranged on the same horizontal display line in the liquid crystal display panel .

When the polarity pattern of the data voltages is converted into the horizontal 1-dot version in the shutdown pattern, the number of the positive polarity data voltages is about twice as large as that of the negative polarity data voltages as shown in FIG. 4, so that the polarity of the data voltages is biased toward the positive polarity , Whereby the common voltage Vcom is shifted toward the positive polarity data voltage. If the polarity of the data is converted to the horizontal 2-dot version with the polarity of the data in the same shutdown pattern, the positive polarity data voltage and the negative polarity data voltage are balanced as shown in FIG. 5, and the common voltage Vcom is not shifted.

However, in the prior art, there is a problem pattern data in which the common voltage Vcom is shifted in both the horizontal one-dot version and the horizontal two-dot version. For example, both the horizontal one-dot version and the horizontal two-dot version cause polarity irregularities of the data voltages for the input image data including the flicker pattern as shown in FIGS. 6 and 7, thereby improving the common voltage shift phenomenon I can not. Thus, the prior art fails to polarize the data voltages in some problematic patterns.

The present invention provides a polarity control method of a data voltage capable of obtaining a polarity balance effect of data voltages in any type of problem pattern without requiring a basic pattern necessary for problem pattern recognition and a liquid crystal display using the method.

The method of controlling a polarity of a data voltage according to the present invention includes the steps of: analyzing a degree of polarity balance of an input image in a unit of I (I is any one of multiples of 3 between 3 and 18); A polarity pattern of a default polarity control signal in the I dot unit and a polarity pattern of an inverted polarity control signal generated in an inverted signal of the default polarity control signal and supplies data indicating the selected polarity pattern to the source drive IC ; And a control circuit for restoring the polarity control signal of the selected polarity pattern based on the data indicating the polarity pattern in the source drive IC, Polarity analog data voltages and outputting them to the data lines of the liquid crystal display panel.

The polarity control method of the data voltage may include assigning weights of different values to data of the input image according to a gradation level of the data, applying a polarity pattern of the default polarity control signal and a polarity pattern of the reverse polarity control signal to data having a highest weight for n (n is a positive integer) I-dot data, respectively; Counting the number of positive polarity and the number of negative polarity of the data to which the default polarity control signal is applied to calculate a first positive polarity count result and a first negative polarity count result of the nth I dot data, Counting the number of positive polarity and the number of negative polarity of the data to calculate a second positive polarity count result and a second negative polarity count result of the nth I dot data; Calculating a first cumulative count result for the n-th I-dot data by adding the difference between the first positive polarity count result and the first negative polarity count result to an n-1-th cumulative count value, Calculating a second cumulative count result for the n-th I-dot data by adding the difference between the polarity count result and the second negative polarity count result to the (n-1) -th cumulative count value; And comparing the first cumulative count result and the second cumulative count result and determining a polarity balance degree of the input image according to the comparison result.

Wherein the polarity control method of the data voltage comprises: selecting a count result of a smaller one of the first cumulative count result and the second cumulative count result; And selecting a polarity pattern in which the selected count result is reflected from the polarity pattern of the default polarity control signal and the polarity pattern of the reverse polarity control signal.

The polarity control method of the data voltage further includes the step of selecting a polarity pattern of the default polarity control signal if the first and second cumulative count results are the same.
The data indicating the selected polarity pattern includes first polarity control data indicating a polarity of the first dot data among the nth I dot data and first polarity control data indicating a polarity pattern having a horizontal 1 dot version and a horizontal 2 dot version And second polarity control data indicating either one of them.
The polarity control method of the data voltage transmits the first and second polarity control data to the source drive ICs together with the nth I dot data through the data bus transmission lines through which the nth I dot data is transmitted step; And reversing the horizontal polarity of the data voltages output to the data lines of the liquid crystal display panel by restoring the selected polarity control signal based on the first and second polarity control data in the source drive IC .

delete

A liquid crystal display device of the present invention includes: a liquid crystal display panel in which data lines and gate lines cross each other; The polarity pattern of the polarity control signal generated by inverting the polarity pattern of the polarity pattern of the default polarity control signal is selected by analyzing the degree of polarity balance of the input image in units of dots, A timing controller for generating data indicating a selected polarity pattern; And a controller for receiving data indicating the selected polarity pattern from the timing controller, restoring a polarity control signal of the polarity pattern selected in the I-dot unit based on data indicating the selected polarity pattern, And a source driver IC converting the data of the input image into a positive / negative analog data voltage using a control signal and outputting the data to the data lines.

The present invention analyzes the polarity balance of the input image in units of I dots and selects either the polarity pattern of the default polarity control signal or the polarity pattern of the reverse polarity control signal. The present invention eliminates the need for reference patterns for recognizing a problem pattern defined in advance in an input image, and it is possible to finely adjust the polarity of data according to the data pattern of the input image in units of I dots, The imbalance can be finely corrected in real time.

1 is a diagram showing an example of a shutdown pattern.
2 is a diagram showing basic patterns for recognizing a shutdown pattern.
3 is a view showing an example of a smear pattern.
4 is a diagram showing the data polarity irregularity of the shutdown pattern in the horizontal one-dot version.
Figure 5 is a plot showing the data polarity uniformity of the shutdown pattern in a horizontal two dot version.
6 is a diagram showing data polarity irregularity of a flicker pattern in a horizontal one-dot version.
7 is a diagram showing the data polarity irregularity of the flicker pattern in the horizontal two-dot version.
8 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
9 is a waveform diagram showing an example of a digital data stream transmitted from the timing controller to the source drive ICs.
10 is a block diagram showing the source drive IC in detail.
11 is a circuit diagram showing the digital-analog converter shown in FIG. 10 in detail.
12 is a circuit diagram showing the gate drive IC in detail.
13 is a block diagram showing the timing controller in detail.
FIG. 14 is a detailed block diagram illustrating the fly-eye polarity selector shown in FIG. 13
15 is a flowchart showing the control procedure of the fly-eye polarity selection unit.
16 is a table for defining the first polarity control data.
17 is a table for defining the second polarity control data.
18 is a diagram illustrating a horizontal one-dot version of a method of controlling polarity of a data voltage according to an embodiment of the present invention in a shutdown pattern.
19 is a diagram illustrating a horizontal two dot inversion of a method of controlling polarity of a data voltage according to an embodiment of the present invention in a shutdown pattern.
20 is a diagram showing a horizontal one-dot version of a method of controlling a polarity of a data voltage according to an embodiment of the present invention in a flicker pattern.
21 is a diagram showing a horizontal two-dot version of a method of controlling polarity of a data voltage according to an embodiment of the present invention in a flicker pattern.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Referring to FIG. 8, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a data driving circuit 102, and a gate driving circuit 103. The data driving circuit 102 includes a plurality of source drive ICs (Integrated Circuit). The gate drive circuit 103 includes a plurality of gate drive ICs.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 100 includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of the data lines 105 and the gate lines 106. [

On the lower glass substrate of the liquid crystal display panel 100, a TFT array is formed. The TFT array includes liquid crystal cells Clc formed at the intersections of the data lines 105 and the gate lines 106, TFTs connected to the pixel electrode 1 of the liquid crystal cells, and a storage capacitor Cst do. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel 100, a color filter array including a black matrix, a color filter, and the like is formed. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system.

The liquid crystal display panel 100 applicable to the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 101 supplies digital video data (RGB) of an input image input from the system board 104 to the data driving circuit 102. The timing controller 101 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the system board 104, And generates control signals for controlling the operation timing of the driving circuit 102 and the gate driving circuit 103. [ The control signals include a gate timing control signal for controlling the operation time of the gate drive circuit 103, a data timing control signal for controlling the operation timing of the data drive circuit 102 and the vertical polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC which generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The timing controller 101 transmits the gate timing control signal to the gate drive ICs via a separate control signal bus transmission line.

The data timing control signal includes first polarity control data G_POL, second polarity control data G_HINV, a source output enable signal SOE, output channel selection option data G_MODE1 and G_MODE2, . 15, the first polarity control data G_POL includes data voltages (hereinafter, referred to as " data voltages ") to be charged in the liquid crystal cells Clc of dots arranged adjacently to the same horizontal line (I is any one of multiples of 3 between 3 and 18) The polarity of the leftmost first data voltage is controlled. The second polarity control data G_HINV controls the horizontal polarity pattern of the data voltages to be charged in the liquid crystal cells Clc of the I-dots arranged adjacently to the same horizontal line. In the following embodiments, the I-dot is described by taking 6 dots as an example, but 3 dots, 9 dots, 12 dots, 15 dots and 18 dots are also applicable to the polar pattern conversion unit of the present invention, Be careful. The source output enable signal SOE controls the output timing of the source drive ICs. The output channel selection option data (G_MODE1, G_MODE2) is input to the source drive ICs supporting multi-channel to select the output channel number of the source drive ICs and disable the unselected output channel. The timing controller 101 transmits a data timing control signal such as first and second polarity control data G_POL and G_HINV and output channel selection option data G_MODE1 and G_MODE2 to the data bus transmission together with the RGB digital video data of the input video RTI ID = 0.0 > IC < / RTI > The timing controller 101 transmits the source output enable signal SOE to the source drive ICs via a separate control signal bus transmission line.

The timing controller 101 internally generates a default polarity control signal POL and an inverse polarity control signal / POL. The timing controller 101 assigns weights according to the gradation levels to each of the input image data and virtually applies the default polarity control signal POL and the reverse polarity control signal / POL to generate the default polarity control signal POL and the reverse polarity control The polarity imbalance degree of the data voltages to be charged in the liquid crystal cells of the liquid crystal display panel 100 in each of the signals / POL. The timing controller 101 supplies a default polarity control signal POL and an inverse polarity control signal / POL (POL) to the liquid crystal cells of the liquid crystal display panel 100 in units of dots so as to balance the positive and negative polarities of the data voltages to be charged in the liquid crystal cells of the liquid crystal display panel 100. [ ).

The default polarity control signal POL is a horizontal polarity pattern of data voltages charged in the liquid crystal cells arranged on the same horizontal display line in the liquid crystal display panel and is a horizontal one dot in the timing controller 101 or a horizontal two dot Version pattern. The reverse polarity control signal / POL is generated in a version pattern whose phase is the reverse phase of the default polarity control signal POL and is either a horizontal 1-dot version or a horizontal 2-dot version pattern. The information of the default polarity control signal POL and the reverse polarity control signal / POL is coded into the first and second polarity control data G_POL and G_HINV and transmitted to the source drive ICs, And restores the default polarity control signal POL and the reverse polarity control signal / POL in response to the second polarity control data G_POL, G_HINV.

The data driving circuit 102 includes one or more source drive ICs. The source driver IC latches the digital video data (RGB) in response to the data timing control signal. The data driving circuit 102 converts the digital video data RGB to the analog positive / negative gamma compensation voltages PGMA and NGMA in response to the vertical polarity control signal POL and outputs the positive / negative polarity data voltages And simultaneously outputs the data voltages having the polarity pattern of the horizontal dot in accordance with the horizontal polarity control signal HINV.

The gate driving circuit 103 sequentially supplies gate pulses to the gate lines 106 in response to gate timing control signals.

9 is a waveform diagram showing an example of a digital data stream transmitted from the timing controller 101 to the source drive ICs. 9 shows an example in which a digital data stream is transmitted between the timing controller 101 and the source drive ICs in a mini LVDS (Low Voltage Differential Signaling) interface standard.

9, the timing controller 101 receives the clock signal CLK +, R, G, and B digital video data, polarity control data G_POL, and G_HINV as a differential signal pair of the mini LVDS interface specification, , And output channel selection option data (G_MODE1, G_MODE2) to the source drive ICs through the data bus transmission lines. FIG. 9 shows only the positive polarity data among the differential signal pairs. CLK + is a clock bus transmission line through which a positive clock signal is transmitted, and LV1 + to LV7 + are data bus transmission lines through which a positive polarity data stream is transmitted. D00 to D29 are 10-bit odd-numbered RGB digital video data. D30 to D59 are 10-bit superior RGB digital video data, respectively.

10 and 11 are views showing the source drive IC in detail.

Referring to Figs. 10 and 11, each of the source drive ICs supplies data voltages to data lines D1 to Dk (j is a positive integer smaller than the number of data lines). Each of the source drive ICs includes a data receiver 201, an internal control signal generator 202, a shift register 203, a latch 204, a digital-to-analog converter (DAC) 205, Output circuit 206 as shown in FIG.

The data receiving unit 201 receives the clock signal, the digital video data, the polarity control data G_POL, G_HINV, and the output channel selection option through the data bus transmission lines LVO + to LV7-, CLK +, and CLK- And receives differential signal pairs including data (G_MODE1, G_MODE2). The data receiving unit 201 samples the polarity control data G_POL and G_HINV and the output channel selection option data G_MODE1 and G_MODE2 in the differential signal pair based on the clock signal and supplies the sampled digital data to the internal control signal generator 202 Supply. The data receiving unit 201 samples the RGB digital video data in the differential signal pair on the basis of the clock signal, and transmits the digital video data to the latch 204. The SB inputted to the data receiving unit 201 is an option signal for changing the data sorting order. EIO1 and EIO2 input to the data receiving unit 201 are start pulses of the shift register 203. [ The data receiving unit 201 is synchronized with the shift register 203 in response to EI01 and EI02.

The internal control signal generating unit 202 restores the default polarity control signal POL and the reverse polarity control signal / POL according to the polarity control data G_POL and G_HINV and generates the horizontal polarity control signal HINV. The default polarity control signal POL, the reverse polarity control signal / POL and the horizontal polarity control signal HINV are supplied to the DAC 205. The internal control signal generation unit 202 generates a channel enable / disable signal (not shown) according to the output channel selection option data (G_MODE1, G_MODE2) and supplies the signal to the output unit 206.

The shift register 203 shifts EI01 and EIO2 to generate an internal clock signal and supplies the internal clock signal to the latch 204. [ L / R is an option signal for changing the shift direction of the shift register 203. The latch 204 sequentially latches RGB digital video data from the data receiving unit 201 in response to an internal clock signal sequentially input from the shift register 203 and sequentially outputs the data to a source output enable signal SOE And outputs them at the same time.

The DAC 205 includes a P-decoder 21A to which a positive gamma reference voltage (PGMA) is supplied, an N-decoder 21B to which a negative gamma reference voltage (NGMA) is supplied, The multiplexers 22 # 1 to # 6 and the horizontal polarity control signal HINV which select the output of the P-decoder 21A and the output of the N-decoder 21B in response to any one of the polarity control signals POL and POL, And a horizontal polarity control circuit 23 for inverting the polarity control signal POL or / POL in response. The P-decoder 21A decodes the digital video data input from the latch 204 and outputs a positive gamma compensation voltage corresponding to the tone value of the data. The N-decoder 21B decodes the digital video data input from the latch 204 and outputs a negative gamma compensation voltage corresponding to the tone value of the data.

The multiplexers 22 # 1 to # 6 are divided into I and select one of the positive gamma compensation voltage and the negative gamma compensation voltage in response to the default polarity control signal POL or the reverse polarity control signal / POL . If I is 6, if the fly-eye polarity selection (FEPOL) as shown in FIG. 18 is selected by the timing controller 101, the control of the first to sixth multiplexers 22 # 1 to # 6 The terminal receives the default polarity control signal POL and the inverted polarity control signal / POL is input to the control terminals of the seventh through twelfth multiplexers (not shown). The horizontal polarity control circuit 23 outputs a polarity control signal POL or (j) to the control terminals of the 4j + 3 and 4j + 4 multiplexers 22 # 3 and 22 # 4 in response to the horizontal polarity control signal HINV / POL) to switch between a horizontal one-dot version and a horizontal two-dot version.

The first multiplexer 22 # 1 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its non-inverted control terminal, And outputs the polarity / negative polarity gamma compensation voltage as the analog data voltage OUT1. The second multiplexer 22 # 2 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its inverting control terminal and outputs the selected positive / And outputs the negative gamma compensation voltage as the analog data voltage OUT2. The third multiplexer 22 # 3 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its non-inverted control terminal, / Negative polarity gamma compensation voltage as the analog data voltage OUT3. The fourth multiplexer 22 # 4 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its inversion control terminal, And outputs the negative gamma compensation voltage as the analog data voltage OUT # 4. The fifth multiplexer 22 # 5 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its non-inverted control terminal, And outputs the polarity / negative polarity gamma compensation voltage as the analog data voltage OUT5. The sixth multiplexer 22 # 2 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its inverting control terminal and outputs the selected positive / And outputs the negative gamma compensation voltage as the analog data voltage OUT6.

The horizontal polarity control circuit 23 includes switch elements S1 and S2, and an inverter INV. The horizontal polarity control circuit 23 outputs the polarity control signals POL and / or POL to the control terminals of the 4j + 3 and 4j + 4 multiplexers 22 # 3 and 22 # 4 in response to the horizontal polarity control signal HINV. POL). The first switch element S1 directly outputs the polarity control signal POL or / POL to the 4j + 3 and 4j + 4 multiplexers 22 # 3 and 22 # 3 in response to the horizontal polarity control signal HINV of the low logic value, 4). The second switch device S2 inverts the logical value of the polarity control signal POL or / POL in response to the horizontal polarity control signal HINV of the high logic value to generate the fourth j + 3 and fourth j + 4 multiplexers 22 # 3, 22 # 4). Therefore, if the horizontal polarity control signal HINV is a high logic value, the polarity of the first to fourth data voltages OUT1 to OUT4 is a horizontal two-dot version pattern, that is, "+ - ". On the other hand, if the horizontal polarity control signal HINV is a low logical value, the polarity of the first to fourth data voltages OUT1 to OUT4 is a version pattern of horizontal one dot, that is, "+ - + - + ".

The output section 206 outputs the data voltage from the DAC 205 to the data lines through the output buffer. The output unit 206 disables the output channel in which the data voltage is not output in response to the channel enable / disable signal input from the internal control signal generating unit 202.

12 is a circuit diagram showing the gate drive IC of the gate drive circuit 103 in detail.

Each of the gate drive ICs includes a shift register 301, a level shifter 304, a plurality of AND gates 302 (hereinafter referred to as "AND gates ") connected between a shift register 301 and a level shifter 304 And an inverter 303 for inverting the gate output enable signal GOE.

The shift register 301 shifts the gate start pulse GSP sequentially in accordance with the gate shift clock GSC using a plurality of D flip-flops connected in a dependent manner. Each of the AND gates 302 logically multiplies the output signal of the shift register 301 and the inverted signal of the gate output enable signal GOE to generate an output. The inverter 303 inverts the gate output enable signal GOE and supplies it to the AND gates 302. Thus, each of the gate drive ICs generates an output only when the enable signal GOE, which is the gate output, is a low logic section.

The level shifter 304 shifts the output voltage swing width of the AND gate 302 to a swing width at which the TFT formed in the TFT array of the liquid crystal display panel can operate. The output signal of the level shifter 304 is sequentially supplied to the gate lines 106.

The shift register 301 may be formed directly on the lower glass substrate of the liquid crystal display panel 100 together with the TFT array in the GIP (Gate In Panel) process. In this case, the level shifter 304 is formed on the control board or the source printed circuit board together with the timing controller 101 to adjust the swing width to the gate shift clock signals And supplies the shift register GSC to the shift register 301.

13 is a block diagram showing the timing controller 101 in detail.

13, the timing controller 101 includes a data receiving unit 11, an internal algorithm processing unit 12, a fly-eye polarity selecting unit 13, a data logic processing unit 14, a data transmitting unit 15, .

The data receiving unit 11 receives RGB digital video data, vertical / horizontal synchronizing signals Vsync and Hsync from the system board 104 through an interface such as an LVDS (Low Voltage Differential Signaling) interface or a TMDS (Transition Minimized Differential Signaling) A data enable signal DE, and a dot clock signal CLK.

The internal algorithm processing unit 12 processes predetermined algorithms such as FRC (Frame Rate Control), ODC (Over Driving Control) algorithm, MEMC (Motion Estimation / Motion Compensation) algorithm and BDI (Black Data Insertion). The internal algorithm processing unit 12 also counts the timing signals input from the system board 104 to generate a gate timing signal, a data timing signal, and a default polarity control signal POL.

The fly-eye polarity selection unit 13 assigns weights according to the gradation level of the digital video data input from the internal algorithm setting unit 12 as shown in Figs. 14 and 15, and outputs the weighted data in units of the weighted I dots The polarity pattern of the default polarity control signal POL and the polarity control signal / POL is virtually applied. The fly-eye polarity selection section 13 counts the positive number and the negative number of the I-dot data to which the default polarity control signal POL and the reverse polarity control signal / POL are applied, To determine the degree of polarity imbalance. The fly-eye polarity selector 13 selects the polarity pattern of the I-dot data to which the polarity pattern of the default polarity control signal POL is applied and the cumulative polarity count result of the polarity pattern of the reverse polarity control signal / And generates a polarity selection control signal CTRPOL indicating a smaller one of the count results. And the fly-eye polarity selector 13 generates a fly-eye polarity select signal FEPOL for finely adjusting the polarity of data in I-dot units in response to the polarity-selection control signal CTRPOL.

The data logic processing unit 14 receives the RGB digital video data from the internal algorithm processing unit 12 and receives the fly-eye polarity selection signal FEPOL from the fly-eye polarity selection unit 13. The data logic processing unit 14 generates a data signal indicating the horizontal polarity inversion period of the fly-eye polarity selection signal FEPOL and the first polarity of the I-dot so that the fly-eye polarity selection signal FEPOL can be restored by the source drive ICs 1 and second polarity control data G_POL, G_HINV. 9, the data logic processing unit 14 transmits control data such as first and second polarity control data G_POL and G_HINV and output channel selection option data G_MODE1 and G_MODE2 together with RGB digital video data to a data transmission unit 15).

The data transmission unit 15 transmits data such as RGB digital video data, first and second polarity control data G_POL and G_HINV and output channel selection option data G_MODE1 and G_MODE2 input from the data logic processing unit 14, To the source drive ICs through the data bus transmission lines in the mini-LVDS interface specification.

14 is a block diagram showing the fly-eye polarity selector 13 in detail. Fig. 15 is a flowchart showing the control procedure of the fly-eye polarity selector 13. Fig.

14 and 15, the fly-eye polarity selector 13 includes a weight assigning unit 31, a first polarity applying unit 32, a second polarity applying unit 33, a first counter 34, A first cumulative counter 36, a second cumulative counter 37, a polarity selector 38, a multiplexer 39, and the like.

The weight assigning unit 31 assigns weights to the RGB digital video data of the odd pixel and the RGB digital video data of the superior pixel, respectively, according to the gradation level. (S1) The weight assigning unit 31 adds the weight '1 And gives a weight value '0' to the black gradation data. The white gradation data and the black gradation data may be determined to be the most significant bit (MSB). The weighting assignment unit 31 determines data having the most significant 2 bits as " 11 ₂ "as white tone data and determines data having the highest two bits as " 00 ₂ " as black tone data.

 The first polarity applying unit 32 applies the polarity pattern of the default polarity control signal POL to the weight W6RGB assigned for each data. (S2) The second polarity applying unit 33 applies a weight value The first and second polarity applying units 32 and 33 apply a polarity pattern of the inversion polarity control signal / POL to the weight given to the black level data W6RGB. The polarity pattern of the polarity control signal (POL or / POL) is applied only to the white gradation data. The reverse polarity control signal / POL is output through an inverter which inverts the default polarity control signal POL.

The first counter 34 counts the positive number and the negative number of the white gradation data in units of I dots with respect to the polarity application results input from the first polarity applying section 32 and outputs the result as a first positive polarity The second counter 35 supplies the result of the first negative polarity count to the first cumulative counter 36. (S4) The second counter 35 counts the polarity application results input from the second polarity application unit 33, And supplies the count result to the second cumulative counter 37 as the second positive count result and the second negative count result (S5).

The first cumulative counter 36 counts the first positive count result input from the first counter 34 and the first negative count result input from the first counter 34 in the first previous count result to which the polarity pattern of the default polarity control signal POL is applied (S6) The second cumulative counter 37 outputs the second cumulative count result obtained by adding the difference from the second counter 35 to the second previous count result to which the polarity pattern of the reverse polarity control signal / POL is applied (S7) The first positive polarity count result for the nth I dot data is set to P-count # 2, and the negative polarity count result is added to the negative polarity count result 2 (n), the result of the first negative polarity count is N-count # 1 (n), the result of second positive polarity count is P-count # 2 n), the first cumulative count result is Accum. count # 1 (n), the second cumulative count result is Accum-count # 2 (n), and the cumulative count result of the last selected polarity pattern for the n- 1 (n), Accum-count # 1 (n) = Accum-count (n-1) + P-count # 1 ) = Accum-count (n-1) + P-count # 2 (n) - N-count # 2 (n).

The polarity selector 38 inputs the previous cumulative count result to the first and second cumulative counters 36 and 37. The polarity selector 38 selects the minimum value among the first cumulative count result and the second cumulative count result and generates a polarity selection control signal CTRPOL indicating the polarity pattern applied to the minimum value. Selects the default polarity control signal POL and the reverse polarity control signal / POL in response to the polarity selection control signal CTRPOL input from the polarity selection unit 38 to generate the fly-eye polarity selection signal FEPOL . The fly-eye polarity selection signal FEPOL is a final polarity control signal for finely controlling the polarity of the data voltage in units of dots for the liquid crystal cells disposed adjacent to the same horizontal line in the liquid crystal display panel 100, (14).

16 is a table for defining the first polarity control data (G_POL). FIG. 17 is a table for defining the second polarity control data G_HINV.

Referring to FIGS. 16 and 17, the internal control signal generator 202 of the source drive IC generates a first polarity control signal POL or / POL at the first polarity control signal POL or / POL, if the first polarity control data G_POL is high logic Is negative (-). The internal control signal generator 202 of the source drive IC generates the first polarity of the I dot in the polarity control signal POL or / POL as positive (+) if the first polarity control data G_POL is logic low . The internal control signal generator 202 of the source drive IC generates the horizontal polarity control signal HINV in the form of a horizontal two dot version (H2Dot) when the second polarity control data G_HINV is high logic, If the data G_HINV is a logic low, the horizontal polarity control signal HINV is generated in a horizontal 1-dot version (H1Dot). The source drive IC converts the polarity of the data voltages output to the data lines in response to the first and second polarity control data (G_POL, G_HINV) input from the timing controller based on the tables of Figs. 16 and 17 .

For example, when the first polarity control data G_POL is a high logic and the second polarity control data G_HINV is a high logic, the source driver IC charges six neighboring liquid crystal cells horizontally when the I dot is 6 dots. (+ - - + + -) which is the horizontal two-dot starting from the positive polarity. The source drive IC is configured such that when the first polarity control data G_POL is high logic and the second polarity control data G_HINV is low logic, when the I dot is 6 dots, The polarity is converted to a horizontal one dot (+ - + - + -) starting from positive polarity. The source drive IC may be configured such that when the first polarity control data G_POL is low logic and the second polarity control data G_HINV is high logic, when the I dot is 6 dots, (- + + - - +) with a horizontal two-dot starting with negative polarity. The source drive IC is configured such that when the first polarity control data G_POL is low logic and the second polarity control data G_HINV is low logic, when the I dot is 6 dots, Converts the polarity to a horizontal one dot (- + - + - +) starting with negative polarity.

Hereinafter, a polarity control method of a data voltage according to an embodiment of the present invention will be described in detail with reference to several types of problem patterns that can be included in an input image assuming that the I dot is 6 dots.

18 is a diagram illustrating a horizontal one-dot version of a method of controlling polarity of a data voltage according to an embodiment of the present invention in a shutdown pattern.

The shutdown pattern is input to the timing controller 101. [ As an example of the shutdown pattern, the odd pixel data may be white gradation data and the superior pixel data may be black gradation data as shown in Fig.

The odd pixel data and the even pixel data each include R, G, and B subpixel data. The timing controller 101 assigns a weight to each data of the input image. The weighted value '1' is given to the white gradation data, and the weighted value '0' is given to the black gradation data.

Referring to FIG. 18, the timing controller 101 generates a default polarity control signal POL in the form of a horizontal 1-dot version, inverts the default polarity control signal POL to generate an inverted polarity control signal / POL, And the polarity pattern of the polarity control signals POL and / POL is virtually applied to the weight of the data. The default polarity control signal POL in the form of a horizontal 1-dot version inverts the polarity of the data voltage to be charged in the liquid crystal cells disposed adjacent to one another in the same horizontal line in the unit of one dot in the liquid crystal display panel, Quot; + (HIGH) - (LOW) + (HIGH) - (LOW) " The inverted polarity control signal / POL in the version form of a horizontal one dot has a logical value in which "- (LOW) + (HIGH) - (LOW) + (HIGH)" is repeated in the example of FIG. The polarity pattern of the polarity control signals POL and / POL is applied only to the white gradation data according to the weight of the data. The sign in the ellipse in FIG. 18 denotes the first polarity of each of the 6-dot data defined by the first polarity control data (G_POL).

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the first 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the first 6-dot data to which the second polarity / POL is applied. (1st 6 dot), the first negative polarity count result is N-count # 1 (1st 6 dot), and the second positive polarity count result is set to P-count # 1 (1st 6 dot) and the second negative polarity count result is N-count # 2 (1st 6 dot), the first 6 dot data to which the default polarity control signal POL is applied in FIG. P-count # 1 (1st 6 dot) = + 2, and N-count # 1 (1st 6 dot) = -1. On the other hand, P-count # 2 (1st 6 dot) = +1 and N-count # 2 (1st 6 dot) = -2 in the first 6 dot data to which the reverse polarity control signal / .

Next, the timing controller 101 adds the difference " +1 " of the first positive and negative polarity count results applied with the default polarity control signal POL to the previous accumulated count value '0' Quot; -1 " of the second positive polarity and negative polarity count results to which the reverse polarity control signal / POL is applied to the previous cumulative count value '0', and outputs the second cumulative count result as " -1 ". If the first cumulative count result for the first 6 dot data is Accum-count # 1 (1st 6 dot) and the second cumulative count result is Accum-count # 2 (1st 6 dot) (1st 6 dot) = 0 + (+1) = +1 and Accum-count # 2 (1st 6 dot) = 0 + (-1) = -1. The timing controller 101 determines whether or not the polarity unbalance number when the default polarity control signal POL is applied is equal to the polarity unbalance number when the reverse polarity control signal / POL is applied based on the first and second cumulative count results The horizontal polarity pattern to be applied to the 6-dot data is applied as a polarity pattern of the default polarity control signal POL having a higher priority than the reverse polarity control signal / POL. Therefore, the timing controller 101 selects Accum-count # 1 as the cumulative count result for the 6th dot data and generates the polarity selection control signal CTRPOL as the high logic for the horizontal polarity pattern of the 6th dot And applies the horizontal polarity pattern of the first 6-dot data as the horizontal polarity pattern of the default polarity control signal POL.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the second 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the second 6-dot data to which the second polarity (/ POL) is applied. (2nd 6 dot), the first negative polarity count result is N-count # 1 (2nd 6 dot), and the second positive polarity count result is P-count # 1 P-count # 1 (2nd 6 dot) = + 2, N-count # 2 (2nd 6 dot), and P- 1 (2nd 6 dot) = -1, P-count # 2 (2nd 6 dot) = +1 and N-count # 2 (2nd 6 dot) = -2.

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the second 6-dot data. If the first cumulative count result for the second 6 dot data is Accum-count # 1 (2nd 6 dot) and the second cumulative count result is Accum-count # 2 (2nd 6 dot) (2nd 6 dot) = +1 + (+1) = + 2, and Accum-count # 2 (2nd 6 dot) = +1 + (-1) = 0. The timing controller 101 selects Accum-count # 2 (2nd 6 dot), in which the number of polarity imbalances becomes 0, as the cumulative count value of the second 6 dot data among the first and second cumulative count results, The polarity selection control signal CTRPOL is generated as low logic with respect to the horizontal polarity pattern of the dot data to apply the horizontal polarity pattern of the second 6 dot data as the horizontal polarity pattern of the reverse polarity control signal / POL.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the third 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the third 6-dot data to which the second polarity / POL is applied. (3rd 6 dot), the first negative polarity count result is N-count # 1 (3rd 6 dot), and the second positive polarity count result is set to P-count # 1 P-count # 1 (3rd 6 dot) = + 2, N-count # 2 (3rd 6 dot) and P- 1 (3rd 6 dot) = -1, P-count # 2 (3rd 6 dot) = -1 and N-count # 2 (3rd 6 dot) = +2.

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the third 6-dot data. If the first cumulative count result for the third 6 dot data is Accum-count # 1 (3rd 6 dot) and the second cumulative count result is Accum-count # 2 (3rd 6 dot) (3rd 6 dot) = 0 + (+1) = +1 and Accum-count # 2 (3rd 6 dot) = 0 + (-1) = -1. Accordingly, the timing controller 101 selects Accum-count # 1 (3rd 6 dot) as the cumulative count result for the 3 rd 6 dot data and sets the polarity selection control signal CTRPOL ) As a logic high to apply the horizontal polarity pattern of the third 6-dot data as the horizontal polarity pattern of the default polarity control signal POL.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the fourth 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the fourth 6 dot data to which the second polarity / POL is applied. (4th 6 dot), the first negative polarity count result is N-count # 1 (4th 6 dot), the second positive polarity count result is set to P-count # 1 P-count # 1 (4th 6 dot) = + 2 and N-count # 2 (4th 6 dot), and the second negative polarity count result is N-count # 1 (4th 6 dot) = -1, P-count # 2 (4th 6 dot) = +1 and N-count # 2 (4th 6 dot) = -2.

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the 4 6 dot data. If the result of the first cumulative count for the 46th dot data is Accum-count # 1 (4th 6 dot) and the result of the second cumulative count is Accum-count # 2 (4th 6 dot) 1, the Accum-count # 1 (4th 6 dot) = +1 + (+1) = 2 and the Accum-count # 2 (4th 6 dot) = +1 + (-1) = 0. The timing controller 101 selects Accum-count # 2 (4th 6 dot) in which the number of polarity imbalances becomes 0 out of the first and second cumulative count results as the cumulative count value of the fourth 6 dot data, The polarity selection control signal CTRPOL is generated as a low logic with respect to the horizontal polarity pattern of the dot data to apply the horizontal polarity pattern of the 4th dot data to the horizontal polarity pattern of the reverse polarity control signal / POL.

When the shutdown pattern as shown in FIG. 18 is input, the polarity of the horizontal one-dot polarity is inverted in six-dot units, and the data voltage charged in the liquid crystal cells in the liquid crystal display panel Balance the polarities of the two. The source drive IC is controlled by the timing controller 101 to supply the data voltages Vs supplied to the first to sixth data lines in response to the first and second polarity control data G_POL and G_HINV when the shutdown pattern as shown in FIG. The horizontal polarity of the data voltage supplied to the seventh to the twelfth data lines is inverted to the reverse polarity control signal / POL (horizontal one-dot) ). 18, a default polarity control signal POL is supplied to the control terminals of the first to sixth multiplexers 22 # 1 to 22 # 6 of the source drive IC, and the seventh to twelfth A reverse polarity control signal (/ POL) is supplied to the control terminal of the multiplexer. Then, the horizontal polarity control circuit 23 outputs the polarity control signals POL or / POL input to the third, fourth, seventh, eighth, eleventh, and twelfth multiplexers to implement the version with the horizontal one dot To the control terminals of the multiplexers.

19 is a diagram illustrating a horizontal two dot inversion of a method of controlling polarity of a data voltage according to an embodiment of the present invention in a shutdown pattern.

Referring to FIG. 19, the timing controller 101 assigns weights to data of input images. The weighted value '1' is given to the white gradation data, and the weighted value '0' is given to the black gradation data.

The timing controller 101 generates a default polarity control signal POL of a version type with a horizontal 2 dot and generates a reverse polarity control signal / POL by inverting the default polarity control signal POL, The polarity pattern of the signals POL, / POL is virtually applied to the weight of the data. The default polarity control signal POL in the form of a horizontal two-dot version inverts the polarity of the data voltage to be charged in the liquid crystal cells disposed adjacent to one another in the same horizontal line in the unit of one dot in the liquid crystal display panel, "+ (HIGH) - (LOW) - (LOW) + (HIGH)" are repeated. The inverted polarity control signal / POL in the form of a horizontal two-dot version has a logical value in which "- (LOW) + (HIGH) + (HIGH) - (LOW)" is repeated in the example of FIG. The polarity pattern of the polarity control signals POL and / POL is applied only to the white gradation data by the weight of the data.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the first 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the first 6-dot data to which the second polarity / POL is applied. (1st 6 dot), the first negative polarity count result is N-count # 1 (1st 6 dot), and the second positive polarity count result is set to P-count # 1 (1st 6 dot) and the second negative polarity count result is N-count # 2 (1st 6 dot), the first 6 dot data to which the default polarity control signal POL is applied in FIG. P-count # 1 (1st 6 dot) = +1 and N-count # 1 (1st 6 dot) = -2. On the other hand, P-count # 2 (1st 6 dot) = + 2 and N-count # 2 (1st 6 dot) = -1 in the first 6-dot data to which the reverse polarity control signal / POL is applied in FIG. .

Next, the timing controller 101 adds the difference " -1 " between the first positive polarity control signal POL and the negative polarity count result applied to the previous polarity control signal POL to the previous accumulated count value '0' +1 "of the second positive polarity and negative polarity count results applied with the reverse polarity control signal / POL to the previous cumulative count value '0' to obtain the second cumulative count result as" -1 " Quot; +1 " If the first cumulative count result for the first 6 dot data is Accum-count # 1 (1st 6 dot) and the second cumulative count result is Accum-count # 2 (1st 6 dot) (1st 6 dot) = 0 + (-1) = -1 and Accum-count # 2 (1st 6 dot) = 0 + (+1) = +1. The timing controller 101 determines whether or not the polarity unbalance number when the default polarity control signal POL is applied is equal to the polarity unbalance number when the reverse polarity control signal / POL is applied based on the first and second cumulative count results The horizontal polarity pattern to be applied to the 6-dot data is applied as the polarity pattern of the high-priority default polarity control signal POL. Therefore, the timing controller 101 selects Accum-count # 1 as the cumulative count result for the 6th dot data and generates the polarity selection control signal CTRPOL as the high logic for the horizontal polarity pattern of the 6th dot And applies the horizontal polarity pattern of the first 6-dot data as the horizontal polarity pattern of the default polarity control signal POL.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the second 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the second 6-dot data to which the second polarity (/ POL) is applied. (2nd 6 dot), the first negative polarity count result is N-count # 1 (2nd 6 dot), and the second positive polarity count result is P-count # 1 P-count # 1 (2nd 6 dot) = +1, N-count # 2 (2nd 6 dot), and P- (2nd 6 dot) = 2, P-count # 2 (2nd 6 dot) = + 2, N-count # 2 (2nd 6 dot) = -1.

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the second 6-dot data. If the first cumulative count result for the second 6 dot data is Accum-count # 1 (2nd 6 dot) and the second cumulative count result is Accum-count # 2 (2nd 6 dot) (2nd 6 dot) = -1 + (-1) = -2, and Accum-count # 2 (2nd 6 dot) = -1 + (+1) = 0. The timing controller 101 selects Accum-count # 2 (2nd 6 dot), in which the number of polarity imbalances becomes 0, as the cumulative count value of the second 6 dot data among the first and second cumulative count results, The polarity selection control signal CTRPOL is generated as low logic with respect to the horizontal polarity pattern of the dot data to apply the horizontal polarity pattern of the second 6 dot data as the horizontal polarity pattern of the reverse polarity control signal / POL.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the third 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the third 6-dot data to which the second polarity / POL is applied. (3rd 6 dot), the first negative polarity count result is N-count # 1 (3rd 6 dot), and the second positive polarity count result is set to P-count # 1 P-count # 1 (3rd 6 dot) = +1, N-count # 2 (3rd 6 dot), and P- 1 (3rd 6 dot) = -2, P-count # 2 (3rd 6 dot) = + 2, N-count # 2 (3rd 6 dot) = -1.

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the third 6-dot data. If the first cumulative count result for the third 6 dot data is Accum-count # 1 (3rd 6 dot) and the second cumulative count result is Accum-count # 2 (3rd 6 dot) , The Accum-count # 1 (3rd 6 dot) = 0 + (-1) = -1 and the Accum-count # 2 (3rd 6 dot) = 0 + (+1) = +1. Accordingly, the timing controller 101 selects Accum-count # 1 (3rd 6 dot) as the cumulative count result for the 3 rd 6 dot data and sets the polarity selection control signal CTRPOL ) As a logic high to apply the horizontal polarity pattern of the third 6-dot data as the horizontal polarity pattern of the default polarity control signal POL.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the fourth 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the fourth 6 dot data to which the second polarity / POL is applied. (4th 6 dot), the first negative polarity count result is N-count # 1 (4th 6 dot), the second positive polarity count result is set to P-count # 1 P-count # 1 (4th 6 dot) = +1 and N-count # 2 (4th 6 dot), and the second negative polarity count result is N-count # (4th 6 dot) = 2, P-count # 2 (4th 6 dot) = + 2, N-count # 2 (4th 6 dot) = -1.

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the 4 6 dot data. If the result of the first cumulative count for the 46th dot data is Accum-count # 1 (4th 6 dot) and the result of the second cumulative count is Accum-count # 2 (4th 6 dot) 1 = (4th 6 dot) = -1 + (-1) = -2 and Accum-count # 2 (4th 6 dot) = -1 + (+1) = 0. The timing controller 101 selects Accum-count # 2 (4th 6 dot) in which the number of polarity imbalances becomes 0 out of the first and second cumulative count results as the cumulative count value of the fourth 6 dot data, The polarity selection control signal CTRPOL is generated as a low logic with respect to the horizontal polarity pattern of the dot data to apply the horizontal polarity pattern of the 4th dot data to the horizontal polarity pattern of the reverse polarity control signal / POL.

When the shutdown pattern as shown in FIG. 19 is input, the polarity of the horizontal two-dot polarity is inverted in six-dot units, and the data voltage Balance the polarities of the two. The source drive IC is controlled by the timing controller 101 to supply the data voltages Vs1 to Vsn supplied to the first to sixth data lines in response to the first and second polarity control data G_POL and G_HINV when the shutdown pattern as shown in FIG. The horizontal polarity of the data voltage supplied to the seventh to the twelfth data lines is inverted to the reverse polarity control signal / POL (horizontal one-dot) ). 19, a default polarity control signal POL is supplied to the control terminals of the first to sixth multiplexers 22 # 1 to 22 # 6 of the source drive IC, and the seventh to twelfth A reverse polarity control signal (/ POL) is supplied to the control terminal of the multiplexer. The horizontal polarity control circuit 23 then outputs the polarity control signals POL or / POL input to the third, fourth, seventh, eighth, eleventh and twelfth multiplexers in order to realize a horizontal two-dot version Inverted and delivered to the control terminals of the multiplexers.

20 is a diagram showing a horizontal one-dot version of a method of controlling a polarity of a data voltage according to an embodiment of the present invention in a flicker pattern.

The flicker pattern is input to the timing controller 101. [ As an example of the flicker pattern, only the R subpixel data of the (4k + 1) th pixel and the G subpixel data of the (4k + 2) th pixel may be white gradation data and the remaining data may be black gradation data as shown in Fig.

Referring to FIG. 20, the timing controller 101 assigns a weight to each data of the input image. The weighted value '1' is given to the white gradation data, and the weighted value '0' is given to the black gradation data.

The timing controller 101 generates a default polarity control signal POL in the version form of horizontal 1 dot and inverts the default polarity control signal POL to generate an inverted polarity control signal / The polarity pattern of the signals POL, / POL is virtually applied to the weight of the data. The default polarity control signal (POL) in the form of a horizontal one-dot version inverts the polarity of the data voltage to be charged in the liquid crystal cells disposed adjacent to one another in the same horizontal line in the unit of one dot in the liquid crystal display panel, Quot; + (HIGH) - (LOW) + (HIGH) - (LOW) " The inverted polarity control signal / POL in the version form of a horizontal one dot has a logical value in which "- (LOW) + (HIGH) - (LOW) + (HIGH)" is repeated in the example of FIG. The polarity pattern of the polarity control signals POL and / POL is applied only to the white gradation data according to the weight of the data.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the first 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the first 6-dot data to which the second polarity / POL is applied. (1st 6 dot), the first negative polarity count result is N-count # 1 (1st 6 dot), and the second positive polarity count result is set to P-count # 1 (1st 6 dot) and the second negative polarity count result is N-count # 2 (1st 6 dot), the first 6-dot data to which the default polarity control signal POL is applied in FIG. P-count # 1 (1st 6 dot) = + 2 and N-count # 1 (1st 6 dot) = 0. On the other hand, P-count # 2 (1st 6 dot) = 0 and N-count # 2 (1st 6 dot) = -2 in the first 6 dot data to which the reverse polarity control signal / POL is applied in FIG.

Next, the timing controller 101 adds the difference ' +2 ' of the first positive and negative polarity count results applied with the default polarity control signal POL to the previous cumulative count value ' 0 & -2 "of the second positive polarity and negative polarity count results to which the reverse polarity control signal / POL is applied to the previous cumulative count value '0', and outputs the second cumulative count result as" -2 ". If the result of the first accumulation count for the first 6 dot data is Accum-count # 1 (1st 6 dot) and the result of accumulation count is Accum-count # 2 (1st 6 dot) (1st 6 dot) = 0 + (+2) = + 2, and Accum-count # 2 (1st 6 dot) = 0 + (-2) = -2. The timing controller 101 determines whether or not the polarity unbalance number when the default polarity control signal POL is applied is equal to the polarity unbalance number when the reverse polarity control signal / POL is applied based on the first and second cumulative count results The horizontal polarity pattern to be applied to the 6-dot data is applied as a polarity pattern of the default polarity control signal POL having a higher priority than the reverse polarity control signal / POL. Therefore, the timing controller 101 selects Accum-count # 1 as the cumulative count result for the 6th dot data and generates the polarity selection control signal CTRPOL as the high logic for the horizontal polarity pattern of the 6th dot And applies the horizontal polarity pattern of the first 6-dot data as the horizontal polarity pattern of the default polarity control signal POL.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the second 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the second 6-dot data to which the second polarity (/ POL) is applied. (2nd 6 dot), the first negative polarity count result is N-count # 1 (2nd 6 dot), and the second positive polarity count result is P-count # 1 P # count # 2 (2nd 6 dot) and the second negative polarity count result is N-count # 2 (2nd 6 dot). 6 dot) = 0, N-count # 1 (2nd 6 dot) = 0, P-count # 2 (2nd 6 dot) = 0 and N-count # 2 (2nd 6 dot) = 0.

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the second 6-dot data. If the first cumulative count result for the second 6 dot data is Accum-count # 1 (2nd 6 dot) and the second cumulative count result is Accum-count # 2 (2nd 6 dot) 2, the Accum-count # 1 (2nd 6 dot) = + 2 + 0 = + 2 and the Accum-count # 2 (2nd 6 dot) = +2 + 0 = +2. Accordingly, the timing controller 101 selects Accum-count # 1 (2nd 6 dot) as the cumulative count value of the second 6-dot data, and outputs the polarity selection control signal CTRPOL to the horizontal polarity pattern of the second 6-dot data. And applies the horizontal polarity pattern of the second 6-dot data as the horizontal polarity pattern of the default polarity control signal POL.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the third 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the third 6-dot data to which the second polarity / POL is applied. (3rd 6 dot), the first negative polarity count result is N-count # 1 (3rd 6 dot), and the second positive polarity count result is set to P-count # 1 P-count # 1 (3rd 6 dot) = + 2, N-count # 2 (3rd 6 dot) and P- 1 (3rd 6 dot) = 0, P-count # 2 (3rd 6 dot) = 0 and N-count # 2 (3rd 6 dot) = -2.

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the third 6-dot data. If the first cumulative count result for the third 6 dot data is Accum-count # 1 (3rd 6 dot) and the second cumulative count result is Accum-count # 2 (3rd 6 dot) 2, the Accum-count # 1 (3rd 6 dot) = + 2 + (+2) = + 4 and the Accum-count # 2 (3rd 6 dot) = +2 + (-2) = 0. Therefore, the timing controller 101 selects Accum-count # 2 (3rd 6 dot) as the minimum cumulative count result for the 3 rd 6 dot data, and outputs the polarity selection control signal (CTRPOL) is generated as low logic to apply the horizontal polarity pattern of the third 6-dot data as the horizontal polarity pattern of the reverse polarity control signal (/ POL).

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the fourth 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the fourth 6 dot data to which the second polarity / POL is applied. (4th 6 dot), the first negative polarity count result is N-count # 1 (4th 6 dot), the second positive polarity count result is set to P-count # 1 P-count # 2 (4th 6 dot) and the second negative polarity count result is N-count # 2 (4th 6 dot) 6th dot) = 0, N-count # 1 (4th 6 dot) = 0, P-count # 2 (4th 6 dot) = 0 and N-count # 2

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the 4 6 dot data. If the first cumulative count result for the 46th dot data is Accum-count # 1 (4th 6 dot) and the second cumulative count result is Accum-count # 2 (4th 6 dot) , The Accum-count # 1 (4th 6 dot) = 0 + 0 = 0 and the Accum-count # 2 (4th 6 dot) = 0 + 0 = 0. Accordingly, the timing controller 101 selects Accum-count # 1 (4th 6 dot) as the cumulative count value of the 4 6 dot data, and outputs the polarity selection control signal CTRPOL to the horizontal polarity pattern of the 4 6 dot data. And applies the horizontal polarity pattern of the fourth 6-dot data as the horizontal polarity pattern of the default polarity control signal POL.

When a flicker pattern as shown in FIG. 20 is input, the polarity pattern in which the polarity unevenness is minimized is selected in units of six dots, and the polarity balance of the data voltages charged in the liquid crystal cells in the liquid crystal display panel . The source drive IC is controlled by the timing controller 101 to supply the data voltages Vs supplied to the first to 12th data lines in response to the first and second polarity control data G_POL and G_HINV when the flicker pattern as shown in FIG. The horizontal polarity of the data voltage supplied to the thirteenth to eighteenth data lines is inverted to the reverse polarity control signal / POL (horizontal one-dot) ). 20, the default polarity control signal POL is supplied to the control terminals of the first to twelfth multiplexers of the source drive IC, and the control terminals of the thirteenth to eighteenth multiplexers are supplied with the reverse polarity control signal (/ POL) is supplied. The horizontal polarity control circuit 23 outputs a polarity control signal to be input to the third, fourth, seventh, eighth, eleventh, twelfth, fifteenth, and sixteenth multiplexers to implement a horizontal one- (POL or / POL) as it is to the control terminals of the multiplexers.

21 is a diagram showing a horizontal two-dot version of a method of controlling polarity of a data voltage according to an embodiment of the present invention in a flicker pattern.

Referring to FIG. 20, the timing controller 101 assigns a weight to each data of the input image. The weighted value '1' is given to the white gradation data, and the weighted value '0' is given to the black gradation data.

The timing controller 101 generates a default polarity control signal POL of a version type with a horizontal 2 dot and generates a reverse polarity control signal / POL by inverting the default polarity control signal POL, The polarity pattern of the signals POL, / POL is virtually applied to the weight of the data. The default polarity control signal (POL) in the form of a horizontal two-dot version inverts the polarity of the data voltage to be charged in the liquid crystal cells arranged adjacent to each other in the same horizontal line in the unit of one dot in the liquid crystal display panel, "+ (HIGH) - (LOW) - (LOW) + (HIGH)" are repeated. The inverted polarity control signal / POL in the form of a horizontal 1-dot version has a logical value in which "- (LOW) + (HIGH) + (HIGH) - (LOW)" is repeated in the example of FIG. The polarity pattern of the polarity control signals POL and / POL is applied only to the white gradation data according to the weight of the data.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the first 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the first 6-dot data to which the second polarity / POL is applied. (1st 6 dot), the first negative polarity count result is N-count # 1 (1st 6 dot), and the second positive polarity count result is set to P-count # 1 (1st 6 dot) and the second negative polarity count result is N-count # 2 (1st 6 dot), the first 6 dot data to which the default polarity control signal POL is applied in FIG. P-count # 1 (1st 6 dot) = + 2 and N-count # 1 (1st 6 dot) = 0. On the other hand, P-count # 2 (1st 6 dot) = 0 and N-count # 2 (1st 6 dot) = -2 in the first 6 dot data to which the reverse polarity control signal / POL is applied in FIG.

Next, the timing controller 101 adds the difference ' +2 ' of the first positive and negative polarity count results applied with the default polarity control signal POL to the previous cumulative count value ' 0 & -2 "of the second positive polarity and negative polarity count results to which the reverse polarity control signal / POL is applied to the previous cumulative count value '0', and outputs the second cumulative count result as" -2 ". If the result of the first accumulation count for the first 6 dot data is Accum-count # 1 (1st 6 dot) and the result of accumulation count is Accum-count # 2 (1st 6 dot) (1st 6 dot) = 0 + (+2) = + 2, and Accum-count # 2 (1st 6 dot) = 0 + (-2) = -2. The timing controller 101 determines whether or not the polarity unbalance number when the default polarity control signal POL is applied is equal to the polarity unbalance number when the reverse polarity control signal / POL is applied based on the first and second cumulative count results The horizontal polarity pattern to be applied to the 6-dot data is applied as a polarity pattern of the default polarity control signal POL having a higher priority than the reverse polarity control signal / POL. Therefore, the timing controller 101 selects Accum-count # 1 as the cumulative count result for the 6th dot data and generates the polarity selection control signal CTRPOL as the high logic for the horizontal polarity pattern of the 6th dot And applies the horizontal polarity pattern of the first 6-dot data as the horizontal polarity pattern of the default polarity control signal POL.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the second 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the second 6-dot data to which the second polarity (/ POL) is applied. (2nd 6 dot), the first negative polarity count result is N-count # 1 (2nd 6 dot), and the second positive polarity count result is P-count # 1 P # count # 2 (2nd 6 dot) and the second negative polarity count result is N-count # 2 (2nd 6 dot). 6 dot) = 0, N-count # 1 (2nd 6 dot) = 0, P-count # 2 (2nd 6 dot) = 0 and N-count # 2 (2nd 6 dot) = 0.

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the second 6-dot data. If the first cumulative count result for the second 6 dot data is Accum-count # 1 (2nd 6 dot) and the second cumulative count result is Accum-count # 2 (2nd 6 dot) 2, the Accum-count # 1 (2nd 6 dot) = + 2 + 0 = + 2 and the Accum-count # 2 (2nd 6 dot) = +2 + 0 = +2. Accordingly, the timing controller 101 selects Accum-count # 1 (2nd 6 dot) as the cumulative count value of the second 6-dot data, and outputs the polarity selection control signal CTRPOL to the horizontal polarity pattern of the second 6-dot data. And applies the horizontal polarity pattern of the second 6-dot data as the horizontal polarity pattern of the default polarity control signal POL.

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the third 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the third 6-dot data to which the second polarity / POL is applied. (3rd 6 dot), the first negative polarity count result is N-count # 1 (3rd 6 dot), and the second positive polarity count result is set to P-count # 1 P-count # 1 (3rd 6 dot) = + 2, N-count # 2 (3rd 6 dot) and P- 1 (3rd 6 dot) = 0, P-count # 2 (3rd 6 dot) = 0 and N-count # 2 (3rd 6 dot) = -2.

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the third 6-dot data. If the first cumulative count result for the third 6 dot data is Accum-count # 1 (3rd 6 dot) and the second cumulative count result is Accum-count # 2 (3rd 6 dot) 2, the Accum-count # 1 (3rd 6 dot) = + 2 + (+2) = + 4 and the Accum-count # 2 (3rd 6 dot) = +2 + (-2) = 0. Therefore, the timing controller 101 selects Accum-count # 2 (3rd 6 dot) as the minimum cumulative count result for the 3 rd 6 dot data, and outputs the polarity selection control signal (CTRPOL) is generated as low logic to apply the horizontal polarity pattern of the third 6-dot data as the horizontal polarity pattern of the reverse polarity control signal (/ POL).

The timing controller 101 counts the number of positive polarity and the number of negative polarity for the fourth 6-dot data to which the default polarity control signal POL is applied to calculate first positive and negative polarity count results, The second positive polarity and negative polarity count results are calculated by counting the number of positive polarity and the number of negative polarity for the fourth 6 dot data to which the second polarity / POL is applied. (4th 6 dot), the first negative polarity count result is N-count # 1 (4th 6 dot), the second positive polarity count result is set to P-count # 1 P-count # 2 (4th 6 dot) and the second negative polarity count result is N-count # 2 (4th 6 dot) 6th dot) = 0, N-count # 1 (4th 6 dot) = 0, P-count # 2 (4th 6 dot) = 0 and N-count # 2

Subsequently, the timing controller 101 calculates the first and second cumulative count results for the 4 6 dot data. If the first cumulative count result for the 46th dot data is Accum-count # 1 (4th 6 dot) and the second cumulative count result is Accum-count # 2 (4th 6 dot) , The Accum-count # 1 (4th 6 dot) = 0 + 0 = 0 and the Accum-count # 2 (4th 6 dot) = 0 + 0 = 0. Accordingly, the timing controller 101 selects Accum-count # 1 (4th 6 dot) as the cumulative count value of the 4 6 dot data, and outputs the polarity selection control signal CTRPOL to the horizontal polarity pattern of the 4 6 dot data. And applies the horizontal polarity pattern of the fourth 6-dot data as the horizontal polarity pattern of the default polarity control signal POL.

By repeating this process, the polarity pattern in which the polarity unevenness is minimized when the flicker pattern as shown in FIG. 21 is input is selected in units of 6 dots, and the polarity balance of the data voltages charged in the liquid crystal cells in the liquid crystal display panel . The source drive IC is controlled by the timing controller 101 to supply the data voltages Vs supplied to the first to the twelfth data lines in response to the first and second polarity control data G_POL and G_HINV when the flicker pattern as shown in FIG. The horizontal polarity of the data voltage supplied to the thirteenth to eighteenth data lines is inverted to the reverse polarity control signal / POL of the horizontal two-dot version, ). When a flicker pattern as shown in FIG. 21 is input, a default polarity control signal POL is supplied to the control terminals of the first to twelfth multiplexers of the source drive IC, and the control terminals of the thirteenth to eighteenth multiplexers are supplied with a reverse polarity control signal (/ POL) is supplied. The horizontal polarity control circuit 23 outputs a polarity control signal to be input to the third, fourth, seventh, eighth, eleventh, twelfth, fifteenth, and sixteenth multiplexers to implement a horizontal two- (POL or / POL) to the control terminals of the multiplexers.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

11: Data receiving unit 12: Internal algorithm processing unit
13: fly-eye polarity selection unit 14: data logic processing unit
15: Data transmission unit 31: Whether to assign a weight
32: first polarity applying portion 33: second polarity applying portion
34: first counter 35: second counter
36: first cumulative counter 37: second cumulative counter
38: Polarity selection unit 39: Multiplexer
100: liquid crystal display panel 101: timing controller
102: data driving circuit 104: gate driving circuit

Claims (11)

(a) analyzing the degree of polarization balance of the input image in units of I (I is any one of 3 to 18);
(b) a polarity pattern of a default polarity control signal in the I-dot unit, and a polarity pattern of an inverted polarity control signal generated as an inverted signal of the default polarity control signal, and outputs data indicating the selected polarity pattern To a source drive IC; And
(c) restoring the polarity control signal of the selected polarity pattern based on the data indicating the polarity pattern in the source drive IC, and using the polarity control signal of the selected polarity pattern, / Negative polarity analog data voltage to the data lines of the liquid crystal display panel.
The method according to claim 1,
The step (a)
Assigning weights of different values to the data of the input image according to a gradation level of the data;
applying a polarity pattern of the default polarity control signal and a polarity pattern of the reverse polarity control signal to data having a highest weight for n (n is a positive integer) I-dot data, respectively;
Counting the number of positive polarity and the number of negative polarity of the data to which the default polarity control signal is applied to calculate a first positive polarity count result and a first negative polarity count result of the nth I dot data, Counting the number of positive polarity and the number of negative polarity of the data to calculate a second positive polarity count result and a second negative polarity count result of the nth I dot data;
Calculating a first cumulative count result for the n-th I-dot data by adding the difference between the first positive polarity count result and the first negative polarity count result to an n-1-th cumulative count value, Calculating a second cumulative count result for the n-th I-dot data by adding the difference between the polarity count result and the second negative polarity count result to the (n-1) -th cumulative count value; And
Comparing the first cumulative count result and the second cumulative count result, and determining a polarity balance degree of the input image according to the comparison result.
3. The method of claim 2,
The step (b)
Selecting a count result of a smaller one of the first cumulative count result and the second cumulative count result;
And selecting a polarity pattern in which the selected count result is reflected from the polarity pattern of the default polarity control signal and the polarity pattern of the reverse polarity control signal.
The method of claim 3,
The step (b)
And selecting a polarity pattern of the default polarity control signal if the first and second cumulative count results are the same.
3. The method of claim 2,
The data indicating the selected polarity pattern may include:
A first polarity control data indicating a polarity of a first dot data among the nth I dot data and a second polarity control data indicating a polarity pattern of a horizontal 1 dot version and a horizontal 2 dot version, Data,
The step (c)
Transmitting the first and second polarity control data to the source drive ICs along with the nth I dot data through the data bus transmission lines through which the nth I dot data is transmitted; And
And restoring the selected polarity control signal based on the first and second polarity control data in the source drive IC to invert the horizontal polarity of the data voltages output to the data lines of the liquid crystal display panel And the polarity of the data voltage is controlled.
A liquid crystal display panel in which data lines and gate lines cross each other;
And a polarity pattern of a default polarity control signal by analyzing the polarity balance of the input image in I (I is any one of multiples of 3 between 3 and 18) and an inverse polarity A timing controller for selecting any one of the polarity patterns of the control signal and generating data indicating the selected polarity pattern; And
And a controller for receiving data indicating the selected polarity pattern from the timing controller, restoring the polarity control signal of the selected polarity pattern based on data indicating the selected polarity pattern, and using the polarity control signal of the selected polarity pattern And a source driver IC converting the data of the input image into a positive / negative analog data voltage and outputting the data to the data lines.
The method according to claim 6,
The timing controller includes:
A weighting unit for assigning weights of different values to data of the input image according to a gradation level of the data;
a polarity applying unit for applying the polarity pattern of the default polarity control signal and the polarity pattern of the reverse polarity control signal to the data having the highest weight for n (n is a positive integer) I-dot data, respectively;
Counting the number of positive polarity and the number of negative polarity of the data to which the default polarity control signal is applied to calculate a first positive polarity count result and a first negative polarity count result of the nth I dot data, A counter for counting a positive number and a negative number of data to calculate a second positive polarity count result and a second negative polarity count result of the nth I dot data;
Calculating a first cumulative count result for the n-th I-dot data by adding the difference between the first positive polarity count result and the first negative polarity count result to an n-1-th cumulative count value, A cumulative counter for adding a difference between the polarity count result and the second negative polarity count result to the (n-1) -th cumulative count value to calculate a second cumulative count result for the n-th I-dot data; And
And a polarity selector for comparing the first cumulative count result and the second cumulative count result and determining a polarity balance degree of the input image according to the comparison result.
8. The method of claim 7,
Wherein the polarity selector comprises:
Selects a count result of a smaller one of the first cumulative count result and the second cumulative count result,
And a polarity pattern in which the selected count result is reflected from the polarity pattern of the default polarity control signal and the polarity pattern of the reverse polarity control signal is selected.
9. The method of claim 8,
Wherein the polarity selector comprises:
And selects a polarity pattern of the default polarity control signal if the first and second cumulative count results are the same.
8. The method of claim 7,
The data indicating the selected polarity pattern may include:
A first polarity control data indicating a polarity of a first dot data among the nth I dot data and a second polarity control data indicating a polarity pattern of a horizontal 1 dot version and a horizontal 2 dot version, Data,
The timing controller includes:
And transmits the first and second polarity control data to the source drive ICs along with the nth I dot data through the data bus transmission lines through which the nth I dot data is transmitted.
11. The method of claim 10,
The source drive IC includes:
Restoring the polarity control signal of the selected polarity pattern based on the first and second polarity control data,
And reverses the horizontal polarity of the data voltages output to the data lines in response to the polarity control signal of the selected polarity pattern.

Images