KR101633621B1 - Field effect transistor and method for manufacturing same, display device, image sensor, and x-ray sensor - Google Patents

Abstract

Field effect transistor, a field effect transistor having an oxide semiconductor layer, a source electrode and a drain electrode, a gate insulating film, a gate electrode, the oxide semiconductor _{layer, In (a) Sn (b} ) Zn (c ₎ to _{O (d) (a> 0} , b> 0, c> 0, d> 0, a + b + c and the first region including a = 1), wherein the far side from the gate electrode than the first region 2 that is arranged, including _{In (e) Ga (f)} Zn (g) O (h) (e> 0, f> 0, g> 0, h> 0, e + f + g = 1) Area.

Description

FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME, DISPLAY DEVICE, IMAGE SENSOR, AND X-RAY SENSOR Field of the Invention The present invention relates to a field effect transistor,

Field of the Invention [0002] The present invention relates to a field effect transistor, a manufacturing method thereof, a display device, an image sensor, and an X-ray sensor.

Recently, research and development of a field effect transistor, particularly a thin film transistor (TFT) using an oxide semiconductor thin film of an In-Ga-Zn-O system (hereinafter referred to as InGaZnO) It is actively. The oxide semiconductor thin film can form a flexible TFT on a substrate such as a plastic plate or a film in view of low temperature film formation, high mobility than amorphous silicon and transparency to visible light (for example, CS Chuang et al., SID 08 DIGEST, P-13).

As a modification of the TFT using such an InGaZnO as the oxide semiconductor layer, JP-A-2010-21555 discloses that a first region including ITO (In and Sn and O) is disposed on the side close to the gate electrode, And a second region including InGaZnO is disposed on the side far from the electrode.

Similarly, in JP-A-2010-21333, a first region containing an oxide semiconductor of In-Zn-O system (hereinafter referred to as InZnO) is disposed near the gate electrode, and a first region containing InGaZnO Layer structure in which a second region including an oxide semiconductor layer of a two-layer structure is disposed.

Japanese Unexamined Patent Application Publication No. 2006-165529 discloses a TFT in which an amorphous oxide including an oxide semiconductor of an In-Sn-Zn-O system (hereinafter referred to as InSnZnO) is used for an oxide semiconductor layer.

The blue light emitting layer used for the organic EL (Electro Luminescence) including the TFT or the liquid crystal shows broad light emission having a peak at a wavelength of about 450 nm, but the lower part of the light emitting spectrum of the blue light of the organic EL element has a wavelength of 420 nm And that the blue color filter is required to have a low characteristic deterioration with respect to light irradiation in a wavelength region shorter than a wavelength of 450 nm in consideration of passing light having a wavelength of 400 nm through about 70%. For example, when the optical band gap of the InGaZnO film is relatively narrow and the region has optical absorption, there arises a problem that the threshold shift of the transistor occurs.

Here, for example, if the reference value of the absolute value of the threshold shift amount with respect to light irradiation at 420 nm as |? Vth | is set to 1 V or less is set as an index of stability against light irradiation, It is difficult to realize a TFT satisfying |? Vth |? 1V.

Specifically, CS Chuang et al., SID 08 DIGEST, and P-13 evaluated the characteristic deterioration of the TFT using InGaZnO as an oxide semiconductor layer for light irradiation. However, the threshold for light irradiation at a wavelength of 420 nm The absolute value of the value shift amount |? Vth | exceeds 1 V.

On the other hand, high-mobility (for example, more than 20 cm2 / Vs) of a single layer of a TFT for driving a display is required along with the enlargement and high definition of the display. CS Chuang et al., SID 08 DIGEST, High-performance displays that can not be covered by a conventional TFT (mobility of about 10 cm A ² / Vs) such as 13 are also proposed.

Japanese Laid-Open Patent Publication No. 2010-21555 discloses that although the first region as the current path layer contains ITO and a high mobility TFT can be realized, the light irradiation characteristic is not mentioned.

Further, in Japanese Laid-Open Patent Publication No. 2010-21333, the mobility of the first region as the current path layer containing InZnO is lower than 10 cmA ² / Vs, and the light irradiation characteristic is not mentioned. In addition, there is also described a combination in which Sn is contained in the first region at a level equal to or higher than the inevitable impurities in addition to InZnO. However, the TFT, mobility, and light irradiation characteristics related to the embodiment in this case are not mentioned.

Further, it is difficult to realize a high mobility and a high switching performance (for example, an On / Off ratio exceeding 10 ⁶ ) when a TFT using an InSnZnO film as a monolayer oxide semiconductor layer as in Japanese Laid-Open Patent Publication No. 2006-165529. This is because the carrier concentration of the InSnZnO film is comparatively high, and therefore it is difficult to pinch off the InSnZnO film alone. In addition, Japanese Patent Application Laid-Open No. 2006-165529 does not mention light irradiation characteristics.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a high mobility of more than 20 cm2 / Vs and a high optical stability that an absolute value of the threshold shift amount |? Vth | And a manufacturing method thereof, a display device, an image sensor, and an X-ray sensor.

The above object of the present invention has been solved by the following means.

<1> oxide as a field effect transistor having a semiconductor layer, a source electrode and a drain electrode, a gate insulating film, a gate electrode, the oxide semiconductor _{layer, In (a) Sn (b} ) Zn (c) O ( _{d) (a> 0, b} > 0, c> 0, d> 0, a + b + c = 1) first is disposed on the far side from the first region, and wherein the said gate electrode than the first region including and And a second region including In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0, e + f + , A field effect transistor.

<2> The field effect transistor according to <1>, wherein the composition of the first region is c / (a + b + c) ≥ 0.200.

<3> The field effect transistor according to <1> or <2>, wherein the composition of the first region is c / (a + b + c) ≤ 0.700.

<4> The field effect transistor according to any one of <1> to <3>, wherein the composition of the first region is represented by c / (a + b + c) ≥ 1/3.

<5> The field-effect transistor according to any one of the items <1> to <4>, wherein the composition of the first region is c / (a + b + c) ≥0.400.

<6> The field-effect transistor according to any one of <1> to <5>, wherein the composition of the first region is represented by a / (a + b + c) ≥ 1/3.

<7> The field effect transistor according to any one of <1> to <6>, wherein the film thickness of the first region is 50 nm or less.

<8> The field-effect transistor according to <7>, wherein the film thickness of the first region is 16 nm or less.

<9> The field effect transistor according to any one of <1> to <8>, wherein the film thickness of the first region is 5 nm or more.

<10> The field effect transistor according to any one of <1> to <9>, wherein the composition of the second region is represented by f / (e + f)? 0.875.

<11> The field-effect transistor according to any one of <1> to <10>, wherein the composition of the second region is represented by f / (e + f)> 0.250.

<12> The field effect transistor according to any one of <1> to <11>, wherein the film thickness of the second region is more than 10 nm but less than 70 nm.

<13> The field effect transistor according to any one of <1> to <12>, wherein the oxide semiconductor layer is an amorphous film.

<14> The field effect transistor according to any one of <1> to <13>, wherein the second region has a lower electrical conductivity than the first region.

<15> as an oxide semiconductor layer, a source electrode and a drain electrode, a gate insulating film, a method of manufacturing a field effect transistor having a gate electrode, a film-forming step of the oxide semiconductor _{layer, In (a) Sn (b} ) The first region including Zn _(c) O _(d) (a> 0, b> 0, c> 0, d> 0, a + b + c = 1) _(E) Ga _(f) Zn _(g) O _(h) (e ₎ is deposited at a position farther from the gate electrode than the first region by a sputtering method, A second region including 0, f> 0, g> 0, h> 0, and e + f + g = 1) is formed by sputtering using the second oxygen partial pressure / argon partial pressure in the deposition chamber And a second film forming step.

<16> The method of manufacturing a field effect transistor according to <15>, wherein the first oxygen partial pressure / argon partial pressure is higher than the second oxygen partial pressure / argon partial pressure.

<17> A display device comprising the field-effect transistor according to any one of <1> to <14>.

<18> An image sensor comprising the field effect transistor according to any one of <1> to <14>.

<19> An X-ray sensor comprising the field-effect transistor according to any one of <1> to <14>.

According to the present invention, it is possible to provide a field effect transistor having both high mobility exceeding 20 cm 2 / Vs and high optical stability with which the absolute value of the threshold shift amount | DELTA Vth | A manufacturing method thereof, a display device, an image sensor, and an X-ray sensor.

Fig. 1 (A) is a schematic view showing an example of a top contact type TFT with a top gate structure as a TFT according to an embodiment of the present invention. FIG. 1B is a schematic view showing an example of a bottom contact type TFT in a top gate structure, as a TFT according to an embodiment of the present invention. FIG. FIG. 1C is a schematic view showing an example of a top contact type TFT with a bottom gate structure as a TFT according to an embodiment of the present invention. FIG. FIG. 1D is a schematic view showing an example of a bottom contact type TFT with a bottom gate structure as a TFT according to an embodiment of the present invention. FIG.
2 is a schematic cross-sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the present invention.
3 is a schematic configuration diagram of the electric wiring of the liquid crystal display device shown in Fig.
4 is a schematic cross-sectional view of a part of an active matrix type organic EL display device according to an embodiment of the electro-optical device of the present invention.
Fig. 5 is a schematic configuration diagram of the electric wiring of the electro-optical device shown in Fig. 4. Fig.
6 is a schematic sectional view of a part of the X-ray sensor which is one embodiment of the sensor of the present invention.
7 is a schematic configuration diagram of the electric wiring of the sensor shown in Fig.
FIG. 8A is a plan view of the TFTs of Examples and Comparative Examples, and FIG. 8B is a cross-sectional view taken along the line AA of the TFT shown in FIG. 8A.
Fig. 9 is a diagram showing a three-way diagram paying attention to the composition of the first region in Examples 1 to 10 and Comparative Examples 2 to 4. Fig.
10 is a graph showing representative Vg-Id characteristics among the measurement results of the transistor characteristics (Vg-Id characteristics) with respect to the TFTs related to Examples 1 to 10 and Comparative Examples 1 to 6. FIG.
11 is a diagram showing the IV characteristics of the TFT related to Example 3 at the time of monochromatic light irradiation, together with IV characteristics before monochromatic light irradiation.
Fig. 12 is a diagram showing the IV characteristic at the time of monochromatic light irradiation of the TFT relating to the fifth embodiment together with the IV characteristic before the monochromatic light irradiation. Fig.
Fig. 13 is a diagram showing the IV characteristic at the time of monochromatic light irradiation of the TFT related to the sixth embodiment, together with the IV characteristic before the monochromatic light irradiation. Fig.
FIG. 14 is a diagram showing IV characteristics at the time of monochromatic light irradiation of the TFT related to Example 7, together with IV characteristics before monochromatic light irradiation. FIG.
Fig. 15 is a diagram showing the IV characteristic at the time of monochoric light irradiation of the TFT related to Comparative Example 1 together with the IV characteristic before the monochromatic light irradiation. Fig.
16 is a graph plotting the relationship of the threshold voltage and the Zn ratio {c / (a + b + c)} to the sum of the composition ratios of In, Sn and Zn in the first region, .
17 is a graph plotting the relationship between the mobility and the Zn ratio {c / (a + b + c)} to the sum of the composition ratios of In and Sn and Zn in the first region based on Table 3 .
18 is a graph in which the relationship of the In ratio {a / (a + b + c)} to the sum of the mobility and the composition ratio of In and Sn and Zn in the first region is plotted based on Table 3 .
19 shows the relationship between the threshold shift amount? Vth and the Zn ratio {c / (a + b + c)} to the sum of the composition ratios of In, Sn and Zn in the first region, FIG.
20 is a graph showing the composition dependency of the carrier concentration in the InSnZnO monolayer.

Hereinafter, a field-effect transistor, a manufacturing method thereof, a display device, an image sensor, and an X-ray sensor according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals, and a description thereof will be omitted as appropriate. The terms &quot; upper &quot; and &quot; lower &quot; used in the following description are used for convenience and are not limited to directions.

1. Field effect transistor

With respect to a field-effect transistor according to an embodiment of the present invention, a TFT is specifically described as an example.

<Schematic Configuration of TFT>

A TFT according to an embodiment of the present invention has a gate electrode, a gate insulating film, an oxide semiconductor layer (active layer), a source electrode and a drain electrode, and a voltage is applied to the gate electrode to control a current flowing in the oxide semiconductor layer, And an active element having a function of switching the current between the electrode and the drain electrode. In the TFT related to the embodiment of the present invention, the oxide semiconductor layer further includes a first region in the film thickness direction and a second region arranged farther from the gate electrode than the first region. In the TFT of the present embodiment, a layer other than the oxide semiconductor layer such as an electrode layer is not inserted between the first region and the second region. Further, in the present invention, the TFT may be formed on the substrate, or a separate substrate may be omitted when a component (for example, an electrode) of the TFT functions as the substrate. Further, the TFT and the substrate may be in direct contact with each other, or an additional layer or element may be formed between the TFT and the substrate.

The element structure of the TFT may be any of a so-called reverse stagger structure (also referred to as a bottom gate structure) and a stagger structure (also referred to as a top gate structure) based on the position of the gate electrode. In addition, any of the top contact type and the bottom contact type may be used based on the contact portion of the oxide semiconductor layer and the source electrode and the drain electrode (appropriately referred to as "source / drain electrode").

The top gate structure is a structure in which a gate electrode is disposed on the top of the gate insulating film and an oxide semiconductor layer is formed on the bottom of the gate insulating film. The bottom gate structure is a structure in which a gate electrode is disposed below the gate insulating film, And an oxide semiconductor layer is formed on the upper side. In the bottom contact type, the source / drain electrodes are formed before the oxide semiconductor layer and the lower surface of the oxide semiconductor layer is in contact with the source / drain electrodes. The top contact type means that the oxide semiconductor layer is formed before the source / And the upper surface of the oxide semiconductor layer is in contact with the source / drain electrodes.

Fig. 1 (A) is a schematic view showing an example of a top contact type TFT with a top gate structure as a TFT according to an embodiment of the present invention. The second region 14B of the oxide semiconductor layer 14 and the first region 14A of the oxide semiconductor layer 14 are formed on one surface in the thickness direction of the substrate 12 in the TFT 10 shown in Fig. ) Are stacked in this order. The source electrode 18 and the drain electrode 20 are provided apart from each other on the first region 14A and the gate insulating film 22 and the gate electrode 24 ) Are stacked in this order.

FIG. 1B is a schematic view showing an example of a bottom contact type TFT in a top gate structure, as a TFT according to an embodiment of the present invention. FIG. In the TFT 30 shown in Fig. 1 (B), the source electrode 18 and the drain electrode 20 are provided on one surface of the substrate 12 in the thickness direction. The second region 14B of the oxide semiconductor layer 14, the first region 14A of the oxide semiconductor layer 14, the gate insulating film 22 and the gate electrode 24 are stacked in this order .

FIG. 1C is a schematic view showing an example of a top contact type TFT with a bottom gate structure as a TFT according to an embodiment of the present invention. FIG. The gate electrode 24, the gate insulating film 22 and the first region 14A of the oxide semiconductor layer 14 are formed on one surface of the substrate 12 in the thickness direction of the substrate 12, And the second region 14B of the oxide semiconductor layer 14 are stacked in this order. The source electrode 18 and the drain electrode 20 are provided separately on the second region 14B (on the surface).

FIG. 1D is a schematic view showing an example of a bottom contact type TFT with a bottom gate structure as a TFT according to an embodiment of the present invention. FIG. In the TFT 50 shown in Fig. 1 (D), a gate electrode 24 and a gate insulating film 22 are sequentially stacked on one surface of the substrate 12 in the thickness direction. A source electrode 18 and a drain electrode 20 are provided on the surface of the gate insulating film 22 so as to be spaced apart from each other and a first region 14A of the oxide semiconductor layer 14 And the second region 14B of the oxide semiconductor layer 14 are stacked in this order.

In addition, the TFT related to the present embodiment may have various configurations other than the above, and may be configured to include a protective layer on the oxide semiconductor layer and an insulating layer on the substrate, as appropriate.

Hereinafter, each component will be described in detail. As a representative example, the top contact type TFT 40 will be described concretely with the bottom gate structure shown in Fig. 1 (C), but the following materials and thickness can be applied to other types of TFTs .

<Detailed Configuration of TFT>

-Board-

The shape, structure, size, etc. of the substrate 12 for forming the TFT 40 are not particularly limited and can be appropriately selected according to the purpose. The substrate 12 may have a single-layer structure or a stacked-layer structure. As the substrate 12, for example, an inorganic material such as glass or YSZ (yttrium stabilized zirconium), a composite plastic material of a resin such as polyethylene terephthalate or polyethylene naphthalate, or a particle having a clay mineral or a mica- A resin composite material of the above-mentioned material can be used. Among them, a substrate formed of a resin or a resin composite material is preferable in that it is lightweight and has flexibility. Further, the resin substrate may be provided with a gas barrier layer for preventing permeation of water or oxygen, an undercoat layer for improving the flatness of the resin substrate and the adhesion with the lower electrode, and the like.

- gate electrode -

The gate electrode 24 is not particularly limited as long as it has high conductivity. For example, a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, Al-Nd, tin oxide, A metal oxide conductive film such as indium tin oxide (ITO), zinc oxide indium oxide (InZnO), or the like can be used as a single layer or a laminated structure of two or more layers.

- Gate insulating film -

As the gate insulating film 22, it is preferable to have a high insulating property, and for example, an insulating film such as SiO ₂ , SiN x, SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , HfO ₂ , And an insulating film containing at least two or more insulating films.

- oxide semiconductor layer -

The oxide semiconductor layer 14 is formed of _{a material selected from the group} consisting of In _(a) Sn _(b) Zn _(c) O _(d) (a> 0, b> 0, c> 0, d> 0, a + b + _(E) Ga _(f) Zn ₍ which may be abbreviated as InSnZnO film in some cases), and a second region 14A which is disposed farther from the gate electrode 24 than the first region 14A, _(g) O _(h) a second area (14B) containing the (e> 0, f> 0 , g> 0, h> 0, e + f + g = 1, since there is a case to be abbreviated as InGaZnO film) the .

The second region 14B is disposed on the side farther from the gate electrode 24, and preferably has a lower electrical conductivity than the first region 14A.

The above-mentioned &quot; electric conductivity &quot; is a physical property value showing the ease of electric conduction of a substance. Assuming a carrier concentration n, an electric charge amount e, and a carrier mobility μ, .

σ = neμ

When the first region 14A or the second region 14B is an n-type semiconductor, the carrier is electrons, the carrier concentration is the electron carrier concentration, and the carrier mobility is the electron mobility. Similarly, in the p-type semiconductor, the first region 14A or the second region 14B is a hole, and the carrier concentration is the hole carrier concentration and the carrier mobility is the hole mobility. The carrier concentration and carrier mobility of a substance can be determined by hole measurement.

The electric conductivity can be obtained by measuring the specific resistance of the film whose thickness is known. The electrical conductivity of a semiconductor varies with temperature, but the electrical conductivity described herein refers to electrical conductivity at room temperature (20 占 폚).

The composition of the first region 14A and the second region 14B can be recognized by using fluorescence X-ray analysis or ICP emission analysis as a short film and secondary ion mass spectrometry (SIMS) as a lamination film, respectively have.

The TFT 40 of the present embodiment having the oxide semiconductor layer 14 having the above-described oxide semiconductor layer 14 has a high mobility exceeding 20 cm 2 / Vs and an absolute value of the threshold shift amount |? Vth | Or less.

Concretely, by using the InSnZnO film in the first region 14A serving as a so-called &quot; carrier traveling layer &quot; by having a higher electric conductivity than the second region 14B, a high mobility exceeding 20 cm2 / Vs can be realized. In addition, the second region 14B becomes a so-called &quot; resistive layer &quot;.

In the TFT of the present embodiment, since the first region 14A is made of the InSnZnO film, higher light stability can be achieved as compared with the case of using the InGaZnO film as the first region 14A, for example. One of the factors is that the InSnZnO film can realize high mobility even in the composition of In: Sn: Zn = 1.000: 1.000: 1.000, which does not require extreme composition modulation compared to the InGaZnO film . In the InGaZnO film, it is difficult to realize a high mobility only in a composition region with a high In content. In the oxide semiconductor of the InGaZnO film, when modulated with a composition largely deviating from In: Ga: Zn = 1.000: 1.000: Is expected to deteriorate. For this reason, in this embodiment, by using the InSnZnO film as the first region 14A, it becomes possible to achieve both high mobility and optical stability.

It is also difficult to realize high mobility and high switching performance (for example, an On / Off ratio exceeding 10 ⁶ ) in a TFT in which the oxide semiconductor layer 14 is composed of only one layer of InSnZnO film. This is because the carrier concentration of the InSnZnO film is relatively high, so that it is difficult to pinch off with only the InSnZnO film. In this embodiment, by using the laminated structure of the first region 14A and the second region 14B, high mobility and high switching performance are realized.

It is also conceivable that the first region 14A is an InGaZnO film and the second region 14B is an InSnZnO film. However, in this case, even if InSnZnO does not undergo large composition modulation compared with InGaZnO, the carrier concentration in the second region 14B can not be sufficiently suppressed because the carrier concentration is high over a wide composition range, and InSnZnO It is expected that it is in a state of being measured as a single film or that a large amount of carriers flow into the first region 14A so that even if conduction of the first region 14A (InGaZnO film) can be observed, do.

As described above, in the present embodiment, the oxide semiconductor layer 14 has the two-layer structure of the first region 14A and the second region 14B, the first region 14A is the InSnZnO film, (14B) is an InGaZnO film.

The oxide semiconductor layer 14 may be either an amorphous film or a crystalline film. However, in the case of the amorphous film, since the film can be formed at a low temperature, it is preferably formed on the flexible substrate 12. In the case of an amorphous film, there is no grain boundary and a film with high uniformity is obtained. Whether or not the oxide semiconductor layer 14 is an amorphous film can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, the oxide semiconductor layer 14 can be judged to be an amorphous film.

Although the film thickness (total film thickness) including the first region 14A and the second region 14B in the oxide semiconductor layer 14 is not particularly limited, From the viewpoint of controlling the total carrier concentration, it is preferably 10 nm or more and 200 nm or less.

The first region 14A of the oxide semiconductor layer 14 preferably contains In, Sn, Zn, and O as main constituent elements. The "main constituent element" means that the total ratio of In, Sn, Zn and O to the total constituent elements of the first region 14A is 98% or more. Therefore, the first region 14A may contain another element such as Mg described later.

The first region 14A includes In _(a) Sn _(b) Zn _(c) O _(d) and the composition of the first region 14A is c / (a + b + C) &gt; = 0.200. This is because it is possible to suppress the threshold voltage Vth of the TFT 40 from remarkably appearing on the negative side. In addition, the above composition does not take into consideration elements other than In, Sn, Zn and O described above, but does not indicate that the first region 14A contains no other element. The expression of the subsequent composition is also the same.

The composition of the first region 14A is more preferably represented by c / (a + b + c) &gt; / 1/3. This is because the threshold voltage of the TFT 40 can be made higher on the plus side than 0V.

The composition of the first region 14A is more preferably represented by c / (a + b + c) 0.400. If c / (a + b + c) &gt; = 0.400, the threshold voltage is almost saturated and variation of the threshold voltage with respect to the composition ratio of Zn can be suppressed.

The composition of the first region 14A is preferably represented by c / (a + b + c)? 0.700. The mobility of the TFT 40 can be made to exceed 30 cm 2 / Vs.

It is more preferable that the composition of the first region 14A is 0.200? C / (a + b + c)? 0.700. It is possible to suppress the absolute value of the threshold shift amount | DELTA Vth | for light irradiation of the wavelength (lambda) 420 nm to less than 0.6 V.

It is more preferable that the composition of the first region 14A is changed to a / (a + b + c) &gt; The mobility of the TFT 40 can be made to exceed 40 cm2 / Vs.

It is preferable that the film thickness of the first region 14A is 50 nm or less by changing the film thickness. It is possible to suppress the threshold voltage of the TFT 40 from remarkably appearing on the negative side and to suppress deterioration of the S value. It is preferable that the film thickness of the first region 14A is 5 nm or more. This is because the flatness of the film can be increased.

The film thickness of the first region 14A is preferably 16 nm or less from the following theoretical equations (1) to (3) of the complete depletion type. Table 1 shows the meanings of symbols in the respective theoretical formulas. The parameters in Table 1 are set forth in T. Kawamura's 1.5-V Operating Fully-Depleted Amorphous Oxide Thin Film Transistors Achieved by 63-mV / decSubthreshold Slope, IEDM08 Digest p.77 (2008) ) &Quot;) is also used.

(1) and (3) are satisfied at the same time, a complete depletion state is realized. In this case, it is considered that it is possible to realize normally off drive or a very good S value.

According to Japanese Patent Application Laid-Open No. 2007-250987 or IEDM08 Digest, p.77 (2008), the value of N _e is, for example, t _ch = 5 nm If there is a substantially ^{_{N e ≤ 5 × 10 19 cm}} -3 or less. Among the embodiments described later, those having the highest carrier concentration are those in which the first region 14A has a: b: c = 0.4: 0.4: 0.2, and the carrier concentration is 5 x 10 ¹⁸ cm ^-3 . In this case, when the condition of complete depletion is satisfied, the film thickness becomes 16 nm or less.

Therefore, in order to realize a good switching characteristic and a low off current, it is understood from the above theoretical expression that the film thickness of the first region 14A is preferably 16 nm or less.

The electric conductivity of the first region 14A is preferably 10 ^-6 Scm ^-1 or more and less than 10 ² Scm ^-1 . More preferably 10 ^-4 Scm ^-1 or more and less than 10 ² Scm ^-1 , and still more preferably 10 ^-1 Scm ^-1 or more and less than 10 ² Scm ^-1 .

On the other hand, although the second region 14B of the oxide semiconductor layer 14 contains In _(e) Ga _(f) Zn _(g) O _(h) as described above, As a main constituent element. The "main constituent element" means that the total ratio of In, Ga, Zn and O to the total constituent elements of the second region 14B is 98% or more. Therefore, the second region 14B may contain another element such as Mg as described later.

The composition of the second region 14B is preferably represented by f / (e + f)? 0.875. This is because if the composition of the second region 14B is in the composition range represented by f / (e + f)? 0.875, high mobility can be easily realized. On the other hand, when the composition of the second region 14B is e / (e + f) &gt; 0.875, the resistance value of the second region 14B becomes relatively high, so that it becomes difficult to secure the ohmic contact. It is easy to get troubled.

The composition of the second region 14B is preferably represented by f / (e + f) &gt; 0.250. When the composition of the second region 14B is f / (e + f)? 0.250, the carrier concentration of the second region 14B is relatively high, and the carrier concentration of the second region 14B from the second region 14B to the first region 14A There is a case where the hump effect occurs in the Vg-Id characteristic or the threshold voltage takes a large negative value. Therefore, it is preferable that the composition of the second region 14B is f / (e + f) &gt; 0.250.

It is preferable that the film thickness of the second region 14B is changed from more than 10 nm to less than 70 nm. If the film thickness of the second region 14B is more than 10 nm, reduction of the off current and suppression of deterioration of the S value can be expected. When the film thickness of the second region 14B is less than 70 nm, the resistance between the source / drain electrodes 18, 20 and the first region 14A is prevented from increasing, and as a result, I can do it.

The electric conductivity of the second region 14B may be the same as that of the first region 14A but is preferably in the range of 10 ^-7 Scm ^-1 to 10 ¹ Scm ^-1 . More preferably 10 ^-7 Scm- ¹ or more and 10 ^-1 Scm- ^{1 or} less.

The control of the carrier concentration of the oxide semiconductor layer, in other words, the electric conductivity can be carried out not only by modulating the composition of the first region 14A and the second region 14B, but also by controlling the oxygen partial pressure at the time of film formation have.

Specifically, the oxygen concentration can be controlled by controlling the oxygen partial pressures at the time of film formation in the first region 14A and the second region 14B, respectively. By increasing the oxygen partial pressure at the time of film formation, the carrier concentration can be reduced, and accordingly, the off current can be expected to be reduced. On the other hand, if the oxygen partial pressure at the time of film formation is lowered, the carrier concentration can be increased, and accordingly the field effect mobility can be expected to increase. It is also possible to promote the oxidation of the film and reduce the amount of oxygen deficiency in the first region, for example, by performing a treatment for irradiating oxygen radicals or ozone after the film formation of the first region 14A.

Further, by doping a part of Zn of the oxide semiconductor layer 14 including the first region 14A and the second region 14B with element ions having a wider bandgap, light accompanying the increase in the optical band gap Irradiation stability can be given. Specifically, it is possible to increase the bandgap of the film by doping Mg. For example, by doping Mg to each region of the first region 14A and the second region 14B, the band profile of the laminated film is maintained compared to a system in which the composition ratio of only In, Sn (or Ga) and Zn is controlled It is possible to increase the band gap. In this case, since the first region 14A is an InSnZnO film, the band gap is more likely to be narrower than that of the InGaZnO film in the second region 14B. Therefore, It is considered that a large amount of Mg is doped to expand the band gap contributing to light irradiation stability more efficiently.

The blue light emitting layer used for the organic EL exhibits broad light emission having a peak at a wavelength of about 450 nm. For example, the optical bandgap of the first region 14A and the second region 14B is relatively narrow, There is a problem that the threshold shift of the transistor occurs. Therefore, in particular, as the thin film transistor used for driving the organic EL, it is preferable that the band gap of the material used for the channel layer is larger.

The carrier concentration in the first region 14A and the second region 14B can be optionally controlled by cation doping. When it is desired to increase the carrier concentration, a material (for example, Ti, Ta or the like) which is liable to become a relatively large cation can be doped. However, in the case of doping a large cation with cations, the number of constituent elements of the oxide semiconductor layer 14 increases, which is disadvantageous from the viewpoint of simplification of the film formation process and cost reduction. It is preferable to control the carrier concentration.

- source / drain electrode -

The source electrode 18 and the drain electrode 20 are not particularly limited as long as they have high conductivity. For example, a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, Al-Nd, tin oxide, A metal oxide conductive film such as zinc, indium oxide, indium tin oxide (ITO), zinc oxide indium (InZnO), or the like can be used as a single layer or a laminated structure of two or more layers.

<Manufacturing Method of TFT>

Next, a method of manufacturing a TFT according to an embodiment of the present invention will be briefly described with a bottom-gate structure shown in Fig. 1 (C) and a top contact type TFT 40 as a representative example. In addition, the following method can be applied to other methods of manufacturing TFTs.

In the manufacturing method of the TFT 40, the substrate 12 is first prepared, and the gate electrode 24 is formed on one surface of the substrate 12 in the thickness direction. The gate electrode 24 may be formed by a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as a CVD method or a plasma CVD method, . For example, in the case of using the sputtering method, the electrode film is formed by the sputtering method and then patterned into a predetermined shape by etching or lift-off method to form the gate electrode 24. At this time, it is preferable to simultaneously pattern the gate electrode 24 and the gate wiring.

Then, a gate insulating film 22 is formed on the surface of the gate electrode 24 and on one surface of the substrate 12 on the gate electrode 24 side. A method of forming the gate insulating film 22 may be the same as the method of forming the gate electrode 24. [ For example, in the case of using the sputtering method, the gate insulating film 22 is formed by forming the insulating film by the sputtering method and then patterning it into a predetermined shape by etching or lift-off method.

Thereafter, a film formation process is performed in which the oxide semiconductor layer 14 is formed (formed) on the surface of the gate insulating film 22.

The oxide semiconductor layer 14 may be formed by the same method as the gate electrode 24. Among them, it is preferable to use a vapor deposition method such as a vacuum deposition method, a sputtering method, an ion plating method, a CVD method, or a plasma CVD method from the viewpoint of easy control of the film thickness. Of the vapor phase film forming methods, a sputtering method and a pulsed laser deposition method (PLD method) are more preferable. From the viewpoint of mass production, a sputtering method is more preferable. For example, the film is formed by controlling the degree of vacuum and the oxygen flow rate by an RF magnetron sputtering deposition method. When sputtering is used, a composite oxide target adjusted to have a desired cation composition may be used, or a 3-ball sputter may be used.

Specifically, in the case of using the sputtering method, the film-forming step of the oxide semiconductor layer _{(14), In (a)} Sn (b) Zn (c) O (d) (a> 0, b> 0, c> 0, d A first region 14A including a first oxygen partial pressure /> 0, a + b + c = 1) is formed in the sputter deposition chamber at a first oxygen partial pressure / than it is arranged on the far side from the gate electrode _{(24), in (e)} Ga (f) Zn (g) O (h) (e> 0, f> 0, g> 0, h> 0, e + f + g = 1), and a second film forming step of forming the second oxygen partial pressure / argon partial pressure inside the sputtering film chamber in this order. However, in the case of the top gate type TFT 10 and the TFT 30, the order of the first film forming step and the second film forming step is reversed.

At the time of forming the oxide semiconductor layer 14, it is preferable that the first oxygen partial pressure / the argon partial pressure be higher than the second partial oxygen partial pressure / the argon partial pressure.

In addition to the effect of lowering the contact resistance of the second region 14B, by reducing the oxygen partial pressure of the first region 14A, it is possible to reduce defects associated with oxygen in the first region 14A that can become the carrier traveling layer It is because. As a result, an excessive carrier can be suppressed and a high switching characteristic can be obtained. In oxide semiconductors including InGaZnO, it is said that the deep level due to oxygen defects exists directly on the electric field itself. Although the light stability can be deteriorated by this deep level, if the oxygen partial pressure is increased to suppress this level, an effect of increasing the light stability can be expected even if the effect is not as great as the composition. In addition, by reducing the oxygen defects, it is considered that the effect of ionizing impurity scattering (functioning as a scattering source when an ionized oxygen defect is present as a donor) can be suppressed, so that a relatively high mobility is easily realized.

It is preferable that the substrate 12 is not exposed to the atmosphere during the film forming process of the oxide semiconductor layer 14. That is, it is preferable that the first film formation step and the second film formation step be performed successively without exposing the substrate 12 to the atmosphere. So as to suppress the mixing of the impurities into the oxide semiconductor layer 14. [

And then the oxide semiconductor layer 14 is patterned. The patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed on the remaining portion by photolithography, and a pattern is formed by etching with an acid solution such as hydrochloric acid, nitric acid, diluted sulfuric acid, or a mixed solution of phosphoric acid, nitric acid, and acetic acid.

Then, a metal film for forming the source / drain electrodes 18 and 20 is formed on the surface of the oxide semiconductor layer 14. The source and drain electrodes 18 and 20 may be formed by the same method as the gate electrode 24. Then, the metal film is patterned into a predetermined shape by an etching or a lift-off method to form a source electrode 18 and a drain electrode 20. At this time, it is preferable to simultaneously pattern the source / drain electrodes 18 and 20 and wirings, which are not shown, connected to these electrodes.

After the formation of the oxide semiconductor layer 14, such as after the formation of the source / drain electrode or immediately after the deposition, it is preferable to carry out post annealing at a temperature of 300 캜 or higher. When the post-annealing temperature is 300 占 폚 or higher, the structure of the defect related to the oxygen bonding state is relaxed, so that the deep defect level is reduced, and high optical stability is easily realized.

The post anneal temperature is preferably less than 600 ° C. When the heat treatment is performed at a temperature of 600 占 폚 or higher, mutual diffusion of the cation occurs between the first region 14A and the second region 14B, and the two regions may be mixed with each other. In this case, it becomes difficult to concentrate the conducting carrier only in the first region 14A. Therefore, the post anneal temperature is preferably less than 600 ° C. Whether or not the mutual diffusion of cation in the first region 14A and the second region 14B is occurring can be confirmed by, for example, performing analysis by a cross-sectional TEM.

It is preferable that the atmosphere during post annealing is an inert atmosphere or an oxidizing atmosphere. Particularly, in an oxidizing atmosphere, oxygen in the oxide semiconductor layer is hardly released, surplus carriers are generated, and electric characteristic deviations can be suppressed from occurring. There is no particular limitation on the post-annealing time, but it is preferable to keep it for at least 10 minutes in consideration of the time required for the film temperature to become uniform.

Further, by using the TFT 40 of the present embodiment, a protective layer for reducing characteristic deterioration upon light irradiation is not used on the oxide semiconductor layer 14, and high mobility and high light irradiation stability are obtained However, the protective layer may be formed on the oxide semiconductor layer 14, of course. For example, by forming a protective layer that absorbs and reflects light in the ultraviolet region (wavelength 400 nm or less), it is possible to further improve stability against light irradiation.

By the above procedure, the top contact type TFT 40 can be manufactured with the bottom gate structure as shown in Fig. 1 (C).

According to the above manufacturing method, since the InSnZnO film of the first region 14A and the InGaZnO film of the second region 14B can be formed at a low temperature (for example, 400 DEG C or less), the substrate 12 can be formed of a resin substrate or the like It becomes possible to manufacture a TFT device which is flexible over the TFT 40 as a whole.

2. Variations

While the present invention has been described in detail with reference to the specific embodiments, it is to be understood that the present invention is not limited to those embodiments and that various other embodiments are possible within the scope of the present invention, The above-described plurality of embodiments can be appropriately combined.

For example, the TFT related to the present embodiment can have various configurations in addition to the above. For example, an insulating layer may be formed on the substrate 12, or a source electrode 18 and a drain electrode 20 may be formed. A protective layer of a single layer or a plurality of protective layers may be formed on the surface of the oxide semiconductor layer 14 exposed between the oxide semiconductor layer 14 and the oxide semiconductor layer 14.

3. Application

The use of the TFT of the present embodiment described above is not particularly limited, but may be applied to an electro-optical device (for example, a liquid crystal display device, an organic EL (Electro Luminescence) display device, In particular, in a large-area device.

Further, the TFT of the present embodiment is particularly preferable for a device that can be manufactured by a low-temperature process using a resin substrate (for example, a flexible display and the like), various sensors such as an X-ray sensor, a MEMS (Micro Electro Mechanical System) (Driving circuit) in an electronic device of the present invention.

4. Electro-optic devices and sensors

The electro-optical device or sensor of the present embodiment is constituted by the TFT of the present invention described above.

Examples of the electro-optical device include a display device (for example, a liquid crystal display device, an organic EL display device, and an inorganic EL display device).

As an example of the sensor, an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) or an X-ray sensor is preferable.

The electro-optical device or sensor of this embodiment exhibits good characteristics with low power consumption. The characteristic referred to here is a display characteristic in the case of an electro-optical device (display device), and a sensitivity characteristic in the case of a sensor.

Hereinafter, a liquid crystal display, an organic EL display, and an X-ray sensor will be described as typical examples of an electro-optical device or sensor having a field effect transistor manufactured by the present invention.

5. Liquid crystal display

Fig. 2 shows a schematic cross-sectional view of a part of the liquid crystal display device according to an embodiment of the electro-optical device of the present invention, and Fig. 3 shows a schematic configuration diagram of the electric wiring thereof.

2, the liquid crystal display 100 according to the present embodiment includes a substrate 12, a top contact type TFT 10 having a top gate structure shown in Fig. 1 (A) A liquid crystal layer 108 sandwiched between the pixel lower electrode 104 and the opposing upper electrode 106 on the gate electrode 24 protected by the passivation layer 102 and a liquid crystal layer 108 for coloring RGB corresponding to each pixel A color filter 110 and polarization plates 112a and 112b on the substrate 12 side of the TFT 10 and on the RGB color filters 110 respectively.

3, the liquid crystal display device 100 according to the present embodiment includes a plurality of gate wirings 112 that are parallel to each other and a plurality of data wirings 114 . Here, the gate wiring 112 and the data wiring 114 are electrically insulated. A TFT 10 is provided near the intersection of the gate wiring 112 and the data wiring 114.

2 and 3, the gate electrode 24 of the TFT 10 is connected to the gate wiring 112, and the source electrode 18 of the TFT 10 is connected to the data wiring 114 . The drain electrode 20 of the TFT 10 is connected to the pixel lower electrode 104 through a contact hole 116 formed in the gate insulating film 22 (a conductor is buried in the contact hole 116). The pixel lower electrode 104 constitutes a capacitor 118 together with the grounded opposing upper electrode 106.

In the liquid crystal device of this embodiment shown in Fig. 2, the TFT 10 of the top gate structure is provided, but the TFT used in the liquid crystal device which is the display device of the present invention is not limited to the top gate structure, Or a TFT having a gate structure.

Since the TFT 10 manufactured by the present invention has high mobility, high-quality display such as high-precision, high-speed response, and high contrast can be performed in a liquid crystal display device, and is also suitable for large-screen display. In addition, when the InGaZnO film or the InSnZnO film of the oxide semiconductor layer 14 is amorphous, deviations in device characteristics can be suppressed, and excellent display quality without unevenness on the large surface is realized. In addition, since the characteristic shift is small, the gate voltage can be reduced, and further, the power consumption of the display device can be reduced. According to the present invention, since a thin film transistor can be manufactured using an amorphous InGaZnO film or an InSnZnO film which can be formed at a low temperature (for example, 200 DEG C or less) as a semiconductor layer, a resin substrate (plastic substrate) . Therefore, according to the present invention, a flexible liquid crystal display device having excellent display quality can be provided.

6. Organic EL display

Fig. 4 shows a schematic cross-sectional view of a part of an active matrix type organic EL display device according to an embodiment of the electro-optical device of the present invention, and Fig. 5 shows a schematic configuration diagram of the electric wiring.

There are two types of driving methods of the organic EL display device, that is, a simple matrix method and an active matrix method. The simple matrix method is advantageous in that it can be manufactured at a low cost, but the number of scanning lines and the light emitting time per scanning line are inversely proportional in that the scanning lines are selected one by one to emit light. As a result, it is difficult to obtain a high definition and a large screen. In the active matrix method, since transistors and capacitors are formed for each pixel, the manufacturing cost is increased. However, since there is no problem that the number of scanning lines can not be increased like a simple matrix method, it is suitable for high definition and large screen.

The organic EL display device 200 of the active matrix type of the present embodiment is configured such that the TFT 10 of the top gate structure shown in Fig. 1A is formed on the substrate 12 provided with the passivation layer 202, Emitting layer 212 provided as the switching TFT 206 and the lower electrode 208 and the upper electrode 210 on the driving TFT 204 and the switching TFT 206 And the top surface of the organic EL light emitting device 214 is protected by the passivation layer 216. [

4 and 5, the organic EL display device 200 of the present embodiment includes a plurality of gate wirings 220 parallel to each other, and a plurality of gate wirings 220 crossing the gate wirings 220, And includes a data wiring 222 and a driving wiring 224. Here, the gate wiring 220, the data wiring 222, and the driving wiring 224 are electrically insulated. The gate electrode 24 of the switching TFT 206 is connected to the gate wiring 220 and the source electrode 18 of the switching TFT 206 is connected to the data wiring 222. The drain electrode 20 of the switching TFT 206 is connected to the gate electrode 24 of the driving TFT 204 and the capacitor 226 is used to keep the driving TFT 10a in an ON state do. The source electrode 18 of the driving TFT 204 is connected to the driving wiring 224 and the drain electrode 20 is connected to the organic EL light emitting element 214.

In the organic EL device of this embodiment shown in Fig. 4, the driving TFT 204 and the switching TFT 206 of the top gate structure are provided, but the organic EL device of the present invention The TFT is not limited to the top gate structure, but may be a bottom gate structure TFT.

Since the TFT 10 manufactured according to the present embodiment has high mobility, low power consumption and high quality display can be achieved. According to the present embodiment, since the thin film transistor can be manufactured using the amorphous InGaZnO film or the InSnZnO film which can be formed at a low temperature (for example, 200 DEG C or less) as the oxide semiconductor layer 14, Plastic substrate) can be used. Therefore, according to the present embodiment, it is possible to provide the flexible organic EL display device 200 having excellent display quality.

In the organic EL display device 200 shown in Fig. 4, the upper electrode 210 may be a top emission type using a transparent electrode, and the lower electrode 208 and each electrode of the TFT may be transparent electrodes, .

7. X-ray sensor

Fig. 6 shows a schematic sectional view of a part of the X-ray sensor which is one embodiment of the sensor of the present invention, and Fig. 7 shows a schematic configuration diagram of the electric wiring.

6 is a schematic cross-sectional view of an enlarged portion of an X-ray sensor array, more specifically. The X-ray sensor 300 of the present embodiment includes a TFT 10 and a capacitor 310 formed on a substrate 12, a charge collecting electrode 302 formed on the capacitor 310, an X-ray converting layer 304, and an upper electrode 306.

On the TFT 10, a passivation film 308 is formed.

The capacitor 310 has a structure in which the insulating film 316 is sandwiched by the capacitor lower electrode 312 and the capacitor upper electrode 314. The capacitor upper electrode 314 is connected to either one of the source electrode 18 and the drain electrode 20 of the TFT 10 (the drain electrode 20 in Fig. 6) through the contact hole 318 formed in the insulating film 316 ).

The charge collecting electrode 302 is formed on the capacitor upper electrode 314 in the capacitor 310 and is in contact with the capacitor upper electrode 314.

The X-ray conversion layer 304 is a layer containing amorphous selenium and is formed so as to cover the TFT 10 and the capacitor 310.

The upper electrode 306 is formed on the X-ray conversion layer 304 and is in contact with the X-ray conversion layer 304.

7, the X-ray sensor 300 of the present embodiment includes a plurality of gate wirings 320 parallel to each other, a plurality of data wirings 322 parallel to each other and intersecting the gate wirings 320, . Here, the gate wiring 320 and the data wiring 322 are electrically insulated. A TFT 10 is provided near the intersection of the gate wiring 320 and the data wiring 322.

The gate electrode 24 of the TFT 10 is connected to the gate wiring 320 and the source electrode 18 of the TFT 10 is connected to the data wiring 322. The drain electrode 20 of the TFT 10 is connected to the charge collecting electrode 302 and the charge collecting electrode 302 is connected to the capacitor 310. [

In the X-ray sensor 300 of the present embodiment, the X-ray is irradiated from the upper portion (on the side of the upper electrode 306) in FIG. 6, and an electron-hole pair is generated in the X- By applying a high electric field to the X-ray conversion layer 304 by means of the upper electrode 306, the generated electric charge is accumulated in the capacitor 310 and read by sequentially scanning the TFT 10.

Since the X-ray sensor 300 of the present embodiment is provided with the TFT 10 having high mobility and high on-current and excellent sensitivity characteristics, the X-ray sensor 300 has a high S / N ratio and is suitable for a large screen. Further, since the sensitivity characteristic is excellent, an image of the optical dynamic range can be obtained in the case of using in an X-ray digital photographing apparatus. Particularly, the X-ray digital photographing apparatus of the present embodiment is preferably used in an X-ray digital photographing apparatus which can perform not only still image photographing but also photographing of moving images and photographing of still images in one operation. Further, when the InGaZnO film or the InSnZnO film in the TFT 10 is amorphous, an image with excellent uniformity is obtained.

In the X-ray sensor 300 of the present embodiment shown in Fig. 6, the TFT 10 of the top gate structure is provided, but the TFT used in the sensor of the present invention is not limited to the top gate structure , Or a TFT having a bottom gate structure.

Example

EXAMPLES Hereinafter, examples will be described, but the present invention is not limited at all by these examples.

&Lt; First region composition dependency on TFT characteristics &gt;

Examples 1 to 10 and Comparative Examples 1 to 4

First, the composition dependence of the first region was verified by fabricating a top contact type TFT with a bottom gate structure according to Examples 1 to 10 and Comparative Examples 1 to 4 as described below.

Fig. 8A is a plan view of the TFTs of the embodiment and the comparative example, and Fig. 8B is a cross-sectional view of the TFT shown in Fig. 8A taken along the line A-A.

First, in Examples 1 to 10 and Comparative Examples 1 to 4, as shown in Figs. 8A and 8B, a p-type Si substrate 502 (1 inch) having a thermally oxidized film 504 formed thereon as a substrate each (角) × 1 mm, thickness: manufacturing the TFT 100 (500 in the simple-shape with the use nmt), and the thermal oxide film 504 as a gate insulating film): 525 ㎛t, thermal oxide film (SiO _2).

Specifically, as shown in Table 2 below, composition modulation was performed for each of the examples and the comparative examples on the p-type Si substrate 502 on which the thermal oxide film was formed, so that the first region 506 of the oxide semiconductor layer was formed to a thickness of 5 nm. The film forming conditions were as follows: the degree of vacuum reached at the time of film formation: 6 × 10 ^-6 Pa; the pressure at the time of film formation: 4.4 × 10 ^-1 Pa; film forming temperature: room temperature; oxygen partial pressure / . In Comparative Example 1, the first region 506 is not an InSnZnO film but an InGaZnO film.

Thereafter, the oxygen partial pressure / argon partial pressure was changed to 0.33, which is about one half of the previous value, while maintaining the vacuum degree at the time of film formation, the pressure at the time of film formation, and the film formation temperature, ) Was formed into a film with a thickness of 50 nm and a width of 3 mm x 4 mm.

The composition of the second region 508 is expressed by the following formula: In _(e) Ga _(f) Zn _(g) O _(h) (1/6: 0.5: 1/3, f / &Gt; 0) in both of the examples and the comparative examples.

In each of the sputtering films, a pattern was formed using a metal mask, and the oxide semiconductor layer was continuously formed between the respective regions without exposure to the atmosphere. Sputtering of each region is performed using a ternary sputter using an In ₂ O ₃ target, a SnO ₂ (or Ga ₂ O ₃ ) target, and a ZnO target in the first region 506 and the second region 508 did. The film thickness adjustment in each region was performed by adjusting the film formation time.

In addition, the film-forming samples prepared by forming films under the same conditions as those of the first region 506 and the second region 508 relating to Examples 1 to 10 and Comparative Examples 1 to 4 were subjected to composition analysis It was confirmed that each of the first region 506 and the second region 508 had the above composition. It was confirmed by X-ray diffraction measurement that each film-forming sample was an amorphous film.

Thereafter, source / drain electrodes 510 and 512 were formed on the surface of the second region 508 by sputtering. The source / drain electrodes 510 and 512 were formed by patterning using a metal mask. After 10 nm of Ti was deposited, 40 nm of Au was deposited.

After the formation of the electrode layer, the post annealing treatment was performed in an atmosphere at 300 ° C and an oxygen partial pressure of 100%.

Thus, Examples 1 to 10 and Comparative Examples 1 to 4 of a bottom gate type TFT having a channel length of 180 탆 and a channel width of 1 mm were obtained.

Fig. 9 is a diagram showing a three-way diagram paying attention to the composition of the first region 506 in Examples 1 to 10 and Comparative Examples 2 to 4. Fig. In addition, the first region 506 in Comparative Example 1 is not represented by a triplet because part of the composition is Ga rather than Sn.

- Comparative Example 5 and Comparative Example 6-

Further, as Comparative Example 5 and Comparative Example 6, the oxide semiconductor layer was formed of 50 nm of In _(a) Sn _(b) Zn _(c) O _(d) (a = 1/3, b = = 1/3) and (a = 2/5, b = 2/5, c = 1/5). The TFTs related to Comparative Example 5 and Comparative Example 6 have the same configuration as the TFTs related to Embodiment 1 except for the configuration of the oxide semiconductor layer.

-evaluation-

Transistor characteristics (Vg-Id characteristics) and mobility μ were measured using the semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies) for the above-described Examples 1 to 10 and Comparative Examples 1 to 6. Representative Vg-Id characteristics among the measurement results are shown in Fig. The Vg-Id characteristic was measured by sweeping the gate voltage Vg within the range of -30 V to +30 V by fixing the drain voltage Vd to 10 V and setting the gate voltage Vg And measuring the drain current Id of the transistor. The mobility was calculated from the Vg-Id characteristic in the linear region obtained by sweeping the gate voltage (Vg) within the range of -30 V to +30 V with the drain voltage (Vd) fixed at 1 V, Are calculated and described.

The TFTs related to Examples 1 to 10 and Comparative Examples 1 to 4 among the fabricated TFTs were evaluated for stability of TFT characteristics for light irradiation by evaluating Vg-Id characteristics and then irradiated with monochromatic light of variable wavelength did.

In the evaluation of the stability, each TFT was placed on a probe stage, and after the drying atmosphere was allowed to flow for 2 hours or more, the TFT characteristics were measured in the dry atmosphere. The Vg-Id characteristic at the time of monochromatic light irradiation and the Vg-Id characteristic at the time of monochromatic light irradiation were compared by setting the irradiation intensity of the monochromatic light source to 10 μW / cm 2 and the wavelength λ to 360 to 700 nm , And light irradiation stability (? Vth). The measurement conditions of the TFT characteristics under monochrome light irradiation were determined by sweeping the gate voltage in the range of Vg = -15 to 15 V with Vds fixed at 10 V. [ In addition, all measurements are carried out after monochromatic light is irradiated for 10 minutes, except when specifically mentioned below. And the threshold shift amount? Vth with respect to light irradiation at 420 nm is used as an index of the optical stability of the TFT.

Representative Vg-Id characteristics among the results of measurement of the I-V characteristics at the time of monochroic light irradiation are shown in Figs. 11 to 15 together with the characteristics before monochromatic light irradiation. The above evaluation method is common in the following embodiments.

Table 3 below shows the measurement results of the threshold shift amount? Vth obtained from the mobility, the threshold voltage Vth obtained from the I-V characteristic, and the I-V characteristic before and after monochromatic light irradiation.

10 and Table 3, it can be seen that high mobility exceeding 20 cm 2 / Vs and good On / Off ratio of about 10 ⁸ are realized for Examples 1 to 10 and Comparative Examples 1 to 4.

On the other hand, as shown in Comparative Examples 5 and 6, when a film having the same composition as that of Example 5 or Example 3 is used as the thin film of the oxide semiconductor layer, the threshold voltage takes a large negative value or exhibits clear switching characteristics (Indicated by &quot; - &quot; in Table 3). Therefore, it can be seen from the present embodiment that the InSnZnO film is disposed on the side closer to the gate electrode and the InGaZnO film is disposed on the side farther from the gate electrode, indicating high mobility, good On / Off ratio, and switching characteristics in the TFT.

From Table 3 and Figs. 11 to 15, it can be seen that in Examples 1 to 10, the fluctuation amount (threshold shift amount? Vth) of the threshold value at the time of light irradiation is smaller than the results of Comparative Examples 1 to 4 have. In Embodiments 1 to 10, although the absolute value of the threshold shift amount | Vth | is within 1 V, in Comparative Examples 1 to 4, the absolute value | Vth | of the threshold shift amount takes a large value exceeding 1 V Able to know. Therefore, from the above results, it is found that the TFT having the InSnZnO / InGaZnO laminated type oxide semiconductor layer has a high mobility exceeding 20 cm 2 / Vs and an absolute value of the threshold shift amount |? Vth | Or less, and a high optical stability, which is equal to or less than that of the first embodiment.

Next, attention is paid to the threshold voltage.

16 is a graph plotting the relationship of the threshold voltage and the Zn ratio {c / (a + b + c)} to the sum of the composition ratios of In, Sn and Zn in the first region, . The dotted line in the figure is a line connecting the average value of the plot of the threshold voltage in the Zn ratio with respect to the sum of the composition ratios of In, Sn and Zn.

10, 16 and Table 3, the threshold voltage depends on the Zn ratio {c / (a + b + c)}, and the tendency that the threshold voltage rises as the Zn ratio increases have. In Embodiments 1, 3 and 4, the threshold voltage is on the minus side of the other embodiments, the second embodiment is also close to 0, and the off current is slightly higher. This is expected in the case of Examples 1 to 4 because the carrier concentration is higher than in the other embodiments. When the content dependence of the carrier concentration in the InSnZnO monolayer shown in Fig. 20 is taken into consideration, it is considered that the carrier concentration becomes higher when the element content of Zn is lower than that of the In or Sn element, which tends to cause carriers. Therefore, it can be said that the content of Zn in the InSnZnO film (first region) is desirably high to some extent from the viewpoint of the threshold voltage and the off current.

For example, as shown in FIG. 16, in Embodiment 1 {c / (a + b + c) = 0.1}, the threshold voltage remarkably appears on the negative side. On the other hand, in Examples 2 to 10 {c / (a + b + c)? 0.200}, the threshold voltage is around 0 or takes a positive value. Therefore, it is understood that it is preferable that the composition of the first region is represented by c / (a + b + c)? 0.200 from the viewpoint that the threshold voltage of the TFT is prevented from appearing significantly on the negative side.

16, the composition of the first region is preferably such that c / (a + b + c) &gt; = 1 or more, more preferably 0 or more, from the viewpoint that the threshold voltage of the TFT 40 can be made higher on the positive side than 0 V, / 3 is more preferable.

Further, from the viewpoint that the threshold voltage is almost saturated and the fluctuation of the threshold voltage with respect to the composition ratio of Zn can be suppressed, the composition of the first region is represented by c / (a + b + c)? 0.400 Is more preferable than the above.

Next, attention is paid to the mobility.

17 is a graph plotting the relationship between the mobility and the Zn ratio {c / (a + b + c)} to the sum of the composition ratios of In and Sn and Zn in the first region based on Table 3 . The dashed line in the figure is a line connecting the average of the plots of the mobility in the respective Zn ratios to the sum of the composition ratios of In, Sn and Zn.

As shown in Fig. 17, the mobility depends on the Zn ratio {c / (a + b + c)}, and it can be seen that the mobility tends to increase as the Zn ratio decreases. It was also confirmed that the Zn ratio rose sharply as the Zn ratio decreased from 0.800 to 0.700, and the mobility was more than 30 cm 2 / Vs at a temperature lower than 0.700. Therefore, it is understood that the composition of the first region is preferably represented by c / (a + b + c)? 0.700 from the viewpoint that the mobility exceeds 30 cm 2 / Vs.

For mobility, we change the viewpoint by In ratio.

18 is a graph in which the relationship of the In ratio {a / (a + b + c)} to the sum of the mobility and the composition ratio of In and Sn and Zn in the first region is plotted based on Table 3 . The dotted line in the figure is a line connecting the average of the plots of the mobility in each In ratio to the sum of the composition ratios of In, Sn and Zn.

As shown in Fig. 18, the mobility depends on the In ratio {a / (a + b + c)}, and it can be seen that the mobility tends to increase as the In ratio increases. It was also confirmed that the In ratio rose sharply as the In ratio increased from 0.100 to 1/3, and the mobility after 1/3 exceeded 40 cm 2 / Vs. Therefore, it was found that the composition of the first region is preferably represented by a / (a + b + c)? 1/3.

Next, attention is paid to the threshold shift amount? Vth.

19 shows the relationship between the threshold shift amount? Vth and the Zn ratio {c / (a + b + c)} to the sum of the composition ratios of In, Sn and Zn in the first region, FIG. The dotted line in the figure is a line connecting the average value of the plots of the threshold shift amount? Vth in each Zn ratio to the sum of the composition ratios of In, Sn and Zn.

As shown in Fig. 19, the threshold shift amount? Vth can be detected as if it does not depend on the Zn ratio, as compared with the mobility or the threshold voltage. However, when the Zn ratio c is 0.1 and 0.8, the absolute value |? Vth | of the threshold shift amount becomes 0.8 V or more and approaches the reference 1 V, but when the Zn ratio c is 0.200? C / the absolute value of the threshold shift amount |? Vth | can be remarkably reduced compared to when c = 0.1 and c = 0.8 at both ends thereof in the range of? 0.700 (hatched range shown in FIG. 9) It can be confirmed that it can be suppressed.

Therefore, it can be seen that the composition of the first region is more preferably 0.200? C / (a + b + c)? 0.700.

&Lt; Dependence of film thickness in the first region on TFT characteristics &gt;

Next, the film thickness dependency of the first region with respect to TFT characteristics was examined.

The TFTs according to Examples 11 to 15, which are identical to those of Example 6 (the composition of the first region is a: b: c = 0.2: 0.2: 0.4) and the film thicknesses of the first regions are different from each other, . The film thicknesses of the first regions of the TFTs related to Examples 11 to 15 were 10, 15, 30, 50, and 70 nm, respectively.

Next, the mobility, the threshold voltage, the off current, and the S value were measured for the TFTs according to Examples 11 to 15 and Example 6, which were fabricated as described above. The measurement results are summarized in Table 4 below.

As shown in Table 4, when the film thickness of the first region is 70 nm, the threshold voltage appears significantly on the minus side, and the deterioration of the S value slightly can be detected. Therefore, it was found that the film thickness of the first region is preferably 50 nm or less. When the thickness is 50 nm or less, it is possible to suppress the threshold voltage of the TFT from remarkably appearing on the negative side, and deterioration of the S value can be suppressed.

If the film thickness of the first region is 30 nm or less, it can be seen that the threshold voltage takes a positive value. Therefore, it was found that the film thickness of the first region is preferably 30 nm or less.

The disclosure of Japanese Patent Application No. 2012-101414 is hereby incorporated by reference in its entirety.

All publications, patent applications, and technical specifications described in this specification are herein incorporated by reference to the same extent as if each individual publication, patent application, and technical specification were specifically and individually indicated to be incorporated by reference. Accepted.

Claims (19)

A field-effect transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode,
Wherein the oxide semiconductor layer
A first region including In _(a) Sn _(b) Zn _(c) O _(d) (a> 0, b> 0.100, c> 0, d> 0, a + b + c =
The first is disposed on the far side from the gate electrode than the first _{region, In (e) Ga (f} ) Zn (g) O (h) (e> 0, f> 0, g> 0, h> 0, e + F + g = 1). &Lt; / RTI &gt; The method according to claim 1,
Wherein a composition of said first region is represented by c / (a + b + c)? 0.200. The method according to claim 1,
Wherein a composition of said first region is represented by c / (a + b + c)? 0.700. The method according to claim 1,
Wherein a composition of the first region is represented by c / (a + b + c)? 1/3. The method according to claim 1,
Wherein a composition of the first region is represented by c / (a + b + c)? 0.400. The method according to claim 1,
Wherein a composition of the first region is represented by a / (a + b + c) &gt; = 1/3. The method according to claim 1,
And the film thickness of the first region is 50 nm or less. 8. The method of claim 7,
And the film thickness of the first region is 16 nm or less. The method according to claim 1,
And the film thickness of the first region is 5 nm or more. The method according to claim 1,
And the composition of the second region is represented by f / (e + f)? 0.875. The method according to claim 1,
And the composition of the second region is represented by f / (e + f) &gt; 0.250. The method according to claim 1,
And the film thickness of the second region is more than 10 nm but less than 70 nm. The method according to claim 1,
Wherein the oxide semiconductor layer is an amorphous film. The method according to claim 1,
And the second region has a lower electrical conductivity than the first region. A method of manufacturing a field effect transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode,
As a process for forming the oxide semiconductor layer,
A first region including In _(a) Sn _(b) Zn _(c) O _(d) (a> 0, b> 0.100, c> 0, d> 0, a + b + c = 1) A first film forming step of forming a film by a sputtering method using a first oxygen partial pressure / an argon partial pressure in the chamber,
The first is arranged on the far side from the gate electrode than the first _{region, In (e) Ga (f} ) Zn (g) O (h) (e> 0, f> 0, g> 0, h> 0, e + f + g = 1), and a second film forming step of forming a film by sputtering with a second oxygen partial pressure / an argon partial pressure in the film forming chamber. 16. The method of claim 15,
Wherein the first oxygen partial pressure / argon partial pressure is higher than the second oxygen partial pressure / argon partial pressure. A display device comprising the field-effect transistor according to any one of claims 1 to 14. An image sensor comprising the field-effect transistor according to any one of claims 1 to 14. An X-ray sensor comprising the field-effect transistor according to any one of claims 1 to 14.

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