JP5626978B2 - THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND APPARATUS HAVING THE THIN FILM TRANSISTOR - Google Patents

Description

  The present invention relates to a thin film transistor including an oxide semiconductor film and a manufacturing method thereof. The present invention also relates to devices such as a display device, an imaging sensor, and an X-ray digital imaging device using the thin film transistor.

  In recent years, research and development of thin film transistors using an In-Ga-Zn-O-based (IGZO) oxide semiconductor thin film as a channel layer have been active. The oxide thin film can be formed at a low temperature, has higher mobility than amorphous silicon, and is transparent to visible light. Therefore, a flexible transparent thin film transistor is formed on a substrate such as a plastic plate or a film. It is possible.

Table 1 shows a comparison table of various transistor characteristics such as mobility and process temperature.

A conventional polysilicon thin film transistor can obtain a mobility of about 100 cm ² / Vs, but since the process temperature is as high as 450 ° C. or higher, it can be formed only on a substrate having high heat resistance, and is inexpensive, has a large area, Not suitable for flexibility. Amorphous silicon thin film transistors can be formed at a relatively low temperature of about 300 ° C., so the selectivity of the substrate is wider than that of polysilicon, but only a mobility of about 1 cm ² / Vs can be obtained at most, so that it can be used for high-definition displays. Is unsuitable. On the other hand, since organic thin film transistors can be formed at 100 ° C. or lower from the viewpoint of low-temperature film formation, application to flexible display applications using plastic film substrates with low heat resistance is expected. Only results similar to amorphous silicon have been obtained.

That is, it is difficult to realize a thin film transistor that can be formed at a relatively low temperature of about 300 ° C. or less and has a high mobility of about 100 cm ² / Vs or more.

As a method for improving the carrier mobility of a transistor, a HEMT (High Electron Mobility Transistor) structure in which different types of semiconductors having different electron affinities are joined and a quantum well is used as a transistor channel has been proposed. In the oxide semiconductor thin film transistor, a HEMT structure device in which ZnO is sandwiched between ZnMgO is manufactured, and a literature report has been made that a high mobility of 140 cm ² / Vs is obtained (Non-patent Document 1).

  In addition, a thin film transistor using an IGZO-based oxide semiconductor thin film and using an IGZO film having different physical quantities as a multilayer structure as an active layer has been proposed. In Patent Document 1, the active layer containing an amorphous oxide has a two-layer structure including a first region and a second region closer to the gate insulating film than the first region. A field effect transistor is described in which the oxygen concentration in the region 2 is higher than the oxygen concentration in the first region. It is described that with such a structure, the electrical resistance of the active layer on the gate insulating film side is increased, so that a channel is formed inside the amorphous oxide and leakage current can be reduced. Has been.

  Patent Document 2 proposes a thin film transistor having an active layer composed of a multilayer structure of an IGZO-based oxide semiconductor thin film and an a-Si thin film. By sandwiching an a-Si film having a small energy band gap with an IGZO film having a larger energy gap, carriers are concentrated in the a-Si portion at the center of the active layer in the layer thickness direction, and the field-effect mobility is the conventional a- There is a description that it is higher than that of the Si film.

  In Patent Document 3, as a field effect transistor using an amorphous oxide semiconductor having a high field effect mobility and a high ON / OFF ratio, the Ga content is between an active layer and a source / drain electrode. The structure provided with the resistance layer containing the oxide whose Ga content rate of this oxide is higher is disclosed.

JP 2006-165529 A JP 2009-170905 A JP 2010-073881 A

K. Koike et al., Applied Physics Letters, 87 (2005) 112106

  However, in patent document 1, it is not the design which supplies a carrier to a carrier travel layer by the electron affinity difference of an active layer. Although there is a description that the leakage current can be reduced, there is a problem that a sufficient carrier density cannot be obtained, and as a result, a sufficient mobility cannot be obtained.

  In Non-Patent Document 1, in order to obtain high mobility, a heterostructure field effect transistor (HEMT) is fabricated by epitaxial growth by molecular beam epitaxy (MBE), and lattice mismatch between the substrate and the semiconductor film layer is observed. It needs to be very small. Therefore, it is necessary to heat the substrate temperature to over 700 ° C., and there is a problem that the selectivity of the base material is remarkably lowered.

  In Patent Document 2, since the amorphous silicon whose mobility is about one digit lower than that of the oxide semiconductor is used for the carrier traveling layer which is the quantum well portion, sufficient mobility cannot be obtained. Another problem is that an IGZO film that is an oxide semiconductor and a non-oxide a-Si dissimilar semiconductor material are bonded together, and a good bonding interface cannot be obtained.

  In Patent Document 3, it is proposed to insert a resistance layer between the electrode layer and the active layer as a means for improving the On / Off ratio without impairing the carrier concentration of the IGZO film serving as the active layer. The design by affinity is not taken into consideration, and there is not enough inflow of carriers from the resistance layer to the active layer, so that the field effect mobility exceeding the mobility of the conventional IGZO single film cannot be obtained. There is.

  The present invention has been made in view of the above circumstances, and relates to an oxide semiconductor, in particular, an IGZO-based oxide semiconductor, which can be manufactured at a low temperature (for example, 300 ° C. or less) and has a high field effect mobility. And it aims at providing the manufacturing method. Another object of the present invention is to provide a device including a thin film transistor having high electron mobility in a channel layer.

The thin film transistor of the present invention is a thin film transistor having an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate,
The active layer is disposed on the gate electrode side through the gate insulating film, the first region having a first electron affinity, and the first electron disposed on the side far from the gate electrode. A second region having a second electron affinity less than the affinity,
In the film thickness direction of the active layer, a well-type potential is formed in which the first region is a well layer, and the second region and the gate insulating film are barrier layers.
The active layer is an oxide semiconductor layer made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) (where a, b, and c are a ≧ 0 and b ≧, respectively) 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0.) B / (a + b) of the second region is larger than b / (a + b) of the first region. It is characterized by.

FIG. 1 shows parameters of the semiconductor electronic structure. The electron affinity (χ) means the energy required to give one electron. In the case of a semiconductor, it refers to the energy difference from the lower end of the conductor (E _C ) to the vacuum level (E _Vac ). As shown in FIG. 1, the electron affinity can be obtained from the difference between the ionization potential (I) and the band gap energy (Eg). The ionization potential (I) can be obtained from photoelectron spectroscopy, and the band gap energy (Eg) can be obtained from transmission spectrum measurement and reflection spectrum measurement.

That is, the thin film transistor of the present invention has an oxide semiconductor layer made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) as shown in FIG. the gate electrode side (see FIG. 2 (a) a gate insulating film side in) the first region a ₁ in the thickness direction _from the second region a _2, wherein the electron affinity chi ₁ of the first region a ₁ is By forming a well-type potential larger than the electron affinity χ _{2 of} the second region and making b / (a + b) of the second region larger than b / (a + b) of the first region , characterized by applying the first region a ₁ and the electron affinity difference between the second region a _2.

  Here, the “region” indicates a three-dimensional region (part) in the film thickness direction. Note that the first and second regions of the oxide semiconductor layer are formed of the same kind of material. The same type means that the element types constituting the film are the same, the cation composition ratio and the oxygen concentration are different, or a part of the constituent elements is doped with a different element. For example, the IGZO films having different Ga / (In + Ga) are the same type, and the IGZO film and the IGZO film in which a part of Zn is doped with Mg are the same type.

By modulating b / (a + b) in the regions A ₁ and A ₂ , a potential difference (electron affinity difference) can be imparted between the regions. Further, the oxygen concentration in the region A ₁ is set to be greater than the oxygen concentration in the region A _2, it is possible to impart a further electron affinity difference. In the present invention, b / (a + b) and oxygen concentration may be modulated simultaneously.

  Here, the difference in electron affinity due to modulation of the cation composition ratio in the first and second regions and / or modulation of the oxygen concentration is preferably 0.17 eV or more and 1.3 eV or less. The difference in electron affinity in the second region is preferably 0.32 eV or more and 1.3 eV or less.

  When the difference in electron affinity between the first and second regions is 0.17 eV or more, carriers efficiently flow from the second region to the first region, and a high carrier concentration and mobility can be obtained.

  Further, in the thin film transistor of the present invention, when the difference in electron affinity is increased, the amount of carriers supplied to the first region is increased, and the mobility is increased. When the electron affinity difference is increased by modulating b / (a + b) with the Zn composition ratio being fixed among In, Ga, and Zn in the oxide semiconductor layer, a maximum electron affinity difference of about 1.3 eV is obtained. It is done. In order to obtain an electron affinity difference larger than this, for example, there is a method of greatly modulating the amount of Zn in the active layer. However, if the amount of Zn is significantly modulated, the amorphous structure in the oxide semiconductor layer becomes unstable, and the TFT Since the instability and non-uniformity of the characteristics are caused, the difference in electron affinity is preferably 1.3 eV or less.

In the thin film transistor of the present invention, the oxide semiconductor layer is preferably an amorphous film.
Whether or not the oxide semiconductor layer is amorphous can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, the oxide semiconductor layer can be determined to be amorphous.

The thin film transistor of the present invention uses an oxide semiconductor made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) as an active layer, and b / (a + b) in the first region A ₁ Is preferably less than 0.5.
More preferably, the first area _{A 1} of b / (a + b) is less than 0.4, and it is desirable for the second region _{A 2} b / (a + b) is 0.6 or more.

  In the thin film transistor of the present invention, it is desirable that the substrate has flexibility.

Examples of flexible substrates include saturated polyester / polyethylene terephthalate (PET) resin substrates, polyethylene naphthalate (PEN) resin substrates, cross-linked fumaric acid diester resin substrates, polycarbonate (PC) resin substrates, polyether sulfone ( PES) resin substrate, polysulfone (PSF, PSU) resin substrate, polyarylate (PAR) resin substrate, cyclic polyolefin (COP, COC) resin substrate, cellulose resin substrate, polyimide (PI) resin substrate, polyamideimide (PAI) Resin substrate, maleimide-olefin resin substrate, polyamide (PA) resin substrate, acrylic resin substrate, fluorine resin substrate, epoxy resin substrate, silicone resin film substrate, polybenzazole resin substrate, substrate made of episulfide compound Liquid crystal polymer (LCP) substrates, cyanate resin substrates, aromatic ether resin substrates, substrates made of composite plastic materials with silicon oxide particles, nanoparticles such as metal nanoparticles, inorganic oxide nanoparticles, and inorganic nitride nanoparticles Substrates made of composite plastic materials with, substrates made of composite plastic materials with metal and inorganic nanofibers and microfibers, substrates made of composite plastic materials with carbon fibers and carbon nanotubes, glass ferkes, glass fibers, A substrate made of a composite plastic material with glass beads, a substrate made of a composite material with clay mineral or particles having a mica-derived crystal structure, and at least one bonding interface between the thin glass and the single organic material. Substrate made of laminated plastic material, no Layer _{(e.g., SiO 2, Al 2 O 3} , SiO x N y) by alternately stacking the organic layer, the substrate made of a composite material having a barrier property having a bonding interface at least once, a stainless steel substrate, Examples thereof include a metal multilayer substrate in which stainless steel and a different kind of metal are laminated, an aluminum substrate, and an aluminum substrate with an oxide film whose surface insulation is improved by subjecting the surface to oxidation treatment (for example, anodization treatment).

The first thin film transistor manufacturing method of the present invention is a thin film transistor having an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate, wherein the active layer includes the gate. A first region having a first electron affinity disposed on the electrode side through the gate insulating film, and a second region disposed on a side farther from the gate electrode and smaller than the first electron affinity. A well-type potential having a well layer as the first region and a barrier layer between the second region and the gate insulating film in the film thickness direction of the active layer. As an active layer, an oxide semiconductor layer made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) (where a, b, and c are a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ , B + c ≠ 0, c + a ≠ 0.) A film forming step of forming by sputtering,
In the film forming step, the first region is formed in a film formation chamber under a first oxygen partial pressure / argon partial pressure, and the film formation chamber is formed in a first oxygen partial pressure / argon partial pressure. The second region having a composition ratio of b / (a + b) larger than b / (a + b) of the region is formed.

  Here, it is preferable that the second oxygen partial pressure / argon partial pressure is smaller than the first oxygen partial pressure / argon partial pressure.

The second thin film transistor manufacturing method of the present invention is a thin film transistor having, on a substrate, an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, wherein the active layer includes the gate. A first region having a first electron affinity disposed on the electrode side through the gate insulating film, and a second region disposed on a side farther from the gate electrode and smaller than the first electron affinity. A well-type potential having a well layer as the first region and a barrier layer between the second region and the gate insulating film in the film thickness direction of the active layer. As an active layer, an oxide semiconductor layer made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) (where a, b, and c are a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ , B + c ≠ 0, c + a ≠ 0.) A film forming step of forming by sputtering,
The film forming step includes the step of forming the first region and the second region having a composition ratio of b / (a + b) larger than b / (a + b) of the first region, The method includes irradiating a film-forming surface of the first region with an oxygen-containing radical during film formation of the first region and / or after film formation of the first region.

The third thin film transistor manufacturing method of the present invention is a thin film transistor having an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate, wherein the active layer includes the gate. A first region having a first electron affinity disposed on the electrode side through the gate insulating film, and a second region disposed on a side farther from the gate electrode and smaller than the first electron affinity. A well-type potential having a well layer as the first region and a barrier layer between the second region and the gate insulating film in the film thickness direction of the active layer. As an active layer, an oxide semiconductor layer made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) (where a, b, and c are a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ , B + c ≠ 0, c + a ≠ 0.) A film forming step of forming by sputtering,
The film forming step includes the step of forming the first region and the second region having a composition ratio of b / (a + b) larger than b / (a + b) of the first region, The method includes irradiating ultraviolet rays onto the film formation surface of the first region in an ozone atmosphere during film formation of the first region and / or after film formation of the first region.

  In any of the first to third thin film transistor manufacturing methods of the present invention, it is desirable that all of the film formation substrates are not exposed to the air during the film formation step.

  A display device according to the present invention includes the thin film transistor according to the present invention.

  The image sensor of the present invention includes the thin film transistor of the present invention.

  The X-ray sensor of the present invention includes the thin film transistor of the present invention.

  The X-ray digital imaging apparatus of the present invention includes the X-ray sensor of the present invention.

In the thin film transistor of the present invention, the first region of the oxide semiconductor layer made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) is in contact with the second region having a lower electron affinity. The lower end of the conduction band of the first region forms the second region and a well-type potential structure having the gate insulating film as a potential barrier. As a result, electron carriers flow into the first region, and the carrier density can be increased without changing the composition ratio or the amount of oxygen vacancies in the first region, so that it has high mobility. Can do.

  In general, in an oxide semiconductor, the amount of oxygen vacancies is increased in order to increase the carrier density. However, excessive oxygen vacancies simultaneously become scatterers for carriers, which causes a decrease in mobility. In the present invention, since it is not necessary to increase the amount of oxygen vacancies in the first region serving as the well layer, the mobility due to oxygen vacancies in the first region serving as the channel layer in addition to the increase in carriers due to the well-type potential structure. The decrease is suppressed, and the mobility can be further improved.

In the thin film transistor of the present invention, the oxide semiconductor layer made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) is formed of the same material in the first and second regions. Thus, the defect density at the interface is reduced as compared with the case where the first region serving as the channel layer is in contact with a different material, and a thin film transistor excellent in terms of uniformity, stability, and reliability is provided. Can do. At the same time, since the first region serving as the channel layer is not exposed to the outside air, the deterioration of the device characteristics depending on the time and the environment where the device is placed is reduced.

  In the present invention, when the oxide semiconductor layer is an amorphous film, it can be formed at a low temperature of 300 ° C. or lower, and thus can be easily formed over a flexible resin substrate such as a plastic substrate. Therefore, application to a flexible display using a plastic substrate with a thin film transistor becomes easier. Furthermore, an amorphous film can easily form a uniform film over a large area, and since there is no grain boundary like a polycrystal, it is easy to suppress variations in device characteristics.

  Since the display device of the present invention includes the thin film transistor of the present invention having high mobility, low power consumption and high-quality display can be realized.

  Since the X-ray sensor of the present invention includes the thin film transistor of the present invention having excellent reliability, the S / N is high and high sensitivity characteristics can be realized.

  Since the X-ray digital imaging apparatus of the present invention includes a transistor having high mobility in the X-ray sensor, it is lightweight and flexible, and an image with a wide dynamic range can be obtained. It is suitable for video shooting.

Diagram for explaining parameters of semiconductor electronic structure (A) Diagram showing potential structure due to electron affinity difference and (B) Diagram showing bandgap energy structure (A) Top gate-top contact type, (B) Top gate-bottom contact type, (C) Bottom gate-top contact type, (D) Bottom gate-bottom contact type thin film transistor Cross-sectional STEM image showing (A) immediately after lamination of IGZO laminated film, (B) after 250 ° C. annealing treatment, and (C) after 500 ° C. annealing treatment The figure which shows the Tauc plot about samples 1-5 The figure which shows the composition ratio dependence of the band gap energy derived from FIG. Diagram showing excitation light energy and normalized photoelectron yield for samples 1-5 The figure which shows the composition dependence of the ionization potential calculated | required from FIG. Diagram showing electron affinity composition dependence (A) Samples 6 and 7, (B) Tauc plots for samples 8 and 9 The figure which shows the oxygen partial pressure / argon partial pressure dependence of the band gap energy derived from FIG. (A) Excitation light energy and normalized electron yield for samples 6 and 7 and (B) samples 8 and 9 The figure which shows the oxygen partial pressure / argon partial pressure dependence of the ionization potential derived from FIG. Diagram showing the electron affinity's oxygen partial pressure / argon partial pressure dependence (A) Specific resistance, (B) Carrier density, and (C) Ga / (In + Ga) dependence of mobility, respectively. Schematic sectional view showing a part of the liquid crystal display device of the embodiment Schematic configuration diagram of electrical wiring of the liquid crystal display device of FIG. Schematic sectional view showing a part of the organic EL display device of the embodiment Schematic configuration diagram of electric wiring of the organic EL display device of FIG. Schematic sectional view showing a part of the X-ray sensor array of the embodiment Schematic configuration diagram of electrical wiring of the X-ray sensor array of FIG. The figure showing the Vg-Id characteristic of an Example and a comparative example The figure which shows the potential depth (DELTA) chi dependence of the mobility (micro | micron | mu) in Example 1, 2, 3 and the comparative example 1.

Embodiments of the present invention will be described below with reference to the drawings.

<Thin film transistor>
3A to 3D are cross-sectional views schematically showing the configuration of the thin film transistors 1 to 4 of the first to fourth embodiments of the present invention. In each thin film transistor of FIGS. 3A to 3D, common elements are denoted by the same reference numerals.

The thin film transistors 1 to 4 according to the embodiment of the present invention include an active layer 12, a source electrode 13, a drain electrode 14, a gate insulating film 15, and a gate electrode 16 on the substrate 11. but first, a second region _a 1, _{a 2} constituting the well potential in the film thickness direction (see FIG. 3 (a) ~ (D) ).

The active layer 12 is composed of an oxide semiconductor layer (IGZO layer) represented by a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO), and the first region A ₁ has a well-type potential. (Refer to FIG. 2A), which is a region having a _first electron affinity χ _{1 serving} as a well portion, and the second region A ₂ is arranged on the side farther from the gate electrode 16 than the first region A _1. The region having a _second electron affinity χ ₂ smaller than the first electron affinity χ ₁ and having a cation composition ratio b / (a + b) larger than that of the first region.

  In the thin film transistors 1 to 4 of the present invention, the first and second regions are continuously formed, and no layers other than the oxide semiconductor layer such as an electrode layer are inserted between the first and second regions. To do.

By modulating b / (a + b) in the regions A ₁ and A ₂ , a potential difference (electron affinity difference) can be imparted between the regions. Further, by making the oxygen concentration in the region A ₁ larger than the oxygen concentration in the region A ₂ , a further difference in electron affinity can be given, and carriers can be efficiently concentrated in the potential well portion. At the same time, to suppress a decrease in mobility due to impurity scattering by increasing the oxygen concentration of the region A _1, it is possible to further improve the mobility. In the present invention, b / (a + b) and oxygen concentration may be modulated simultaneously.

The thin film transistor 1 of the first embodiment shown in FIG. 3A is a top gate-top contact type transistor, and the thin film transistor 2 of the second embodiment shown in FIG. 3B is a top gate-bottom contact. The thin film transistor 3 of the third embodiment shown in FIG. 3C is a bottom gate-top contact type transistor, and the thin film transistor 4 of the fourth embodiment shown in FIG. A bottom-gate / bottom-contact transistor.
In the embodiment shown in FIGS. 3A to 3D, the arrangement of the gate, source, and drain electrodes with respect to the active layer (IGZO layer) is different, but the function of each element given the same reference numeral is the same. Similar materials can be applied.

  Hereinafter, each component will be described in detail.

(substrate)
There is no restriction | limiting in particular about the shape of the board | substrate 11 for forming the thin-film transistor 1, a structure, a magnitude | size, It can select suitably according to the objective. The structure of the substrate may be a single layer structure or a laminated structure. As the substrate 11, for example, a substrate made of an inorganic material such as YSZ (yttrium stabilized zirconium) or glass, a resin, a resin composite material, or the like can be used. Among these, a substrate made of a resin or a resin composite material is preferable in terms of light weight and flexibility. Specifically, polybutylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polybutylene naphthalate, polystyrene, polycarbonate, polysulfone, polyethersulfone, polyarylate, allyl diglycol carbonate, polyamide, polyimide, polyamideimide, polyetherimide, Fluorine resin such as polybenzazole, polyphenylene sulfide, polycycloolefin, norbornene resin, polychlorotrifluoroethylene, liquid crystal polymer, acrylic resin, epoxy resin, silicone resin, ionomer resin, cyanate resin, crosslinked fumaric acid diester, cyclic polyolefin, Substrates made of synthetic resins such as aromatic ethers, maleimide-olefins, cellulose, episulfide compounds, A substrate composed of a composite plastic material of the above-mentioned synthetic resin and the like and silicon oxide particles, a substrate composed of a composite plastic material of the above-described synthetic resin and the like and metal nanoparticles, inorganic oxide nanoparticles or inorganic nitride nanoparticles, A substrate made of a composite plastic material of the aforementioned synthetic resin, etc. and carbon fiber or carbon nanotube, a substrate made of a composite plastic material of the aforementioned synthetic resin, etc., and glass fake, glass fiber or glass bead, the aforementioned synthesis A substrate made of a composite plastic material of a resin or the like and particles having a clay mineral or a mica-derived crystal structure, a laminated plastic substrate having at least one bonding interface between a thin glass and any of the aforementioned synthetic resins, inorganic By alternately laminating layers and organic layers (the aforementioned synthetic resins), at least one contact Insulating the surface by subjecting a substrate made of a composite material having a barrier property having an interface, a stainless steel substrate, a metal multilayer substrate in which stainless steel and a dissimilar metal are laminated, an aluminum substrate or a surface to an oxidation treatment (for example, anodization treatment). An aluminum substrate with an improved oxide film can be used.

  The resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, and the like. The resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion with the lower electrode, and the like.

  Moreover, it is preferable that the thickness of a board | substrate is 50 micrometers or more and 500 micrometers or less. When the thickness of the substrate is 50 μm or more, the flatness of the substrate itself is further improved. When the thickness of the substrate is 500 μm or less, the flexibility of the substrate itself is further improved, and the use as a substrate for a flexible device becomes easier. In addition, since the thickness which has sufficient flatness and flexibility changes with the materials which comprise a board | substrate, it is necessary to set the thickness according to board | substrate material, but the range becomes a range of 50 micrometers-500 micrometers in general. .

(Active layer)
The active layer 12 is made of an IGZO film, more specifically a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO), and has first and second electron affinity χ ₁ and χ ₂ , respectively. The first and second regions A ₁ and A ₂ are provided, the first electron affinity χ ₁ is greater than the second electron affinity χ ₂ , and b / a + b in the region A ₂ is b / a + b in the region A ₁ . It is larger than (a + b).

In order to form a well-type potential in the stacking direction, b / (a + b) is modulated between the regions to give an electron affinity difference between the regions. The first region A ₁ and the difference in potential between the second region A ₂ well potential by making the oxygen concentration of the second region A _2, lower than the first oxygen concentration in the region A ₁ An electron affinity difference that forms can be imparted. When each region is configured by a common element and composition ratio, the higher the oxygen concentration, the higher the electron affinity.

  Here, it is preferable that the electron affinity difference by modulating b / (a + b) in the first and second regions and by modulating the oxygen concentration is 0.17 eV or more and 1.3 eV or less. It is desirable that the electron affinity difference in the second region be 0.32 eV or more and 1.3 eV or less.

  When the electron affinity difference between the first and second regions is 0.17 eV or more, carriers efficiently flow from the second region to the first region, and a high carrier concentration and high mobility can be obtained. .

  Further, in the thin film transistor of the present invention, when the difference in electron affinity is increased, the amount of carriers supplied to the first region is increased, and the mobility is increased. When the electron affinity difference is increased by modulating b / (a + b) with the Zn composition ratio being fixed among In, Ga, and Zn in the oxide semiconductor layer, a maximum electron affinity difference of about 1.3 eV is obtained. It is done. In order to obtain an electron affinity difference larger than this, for example, there is a method of greatly modulating the amount of Zn in the active layer. However, if the amount of Zn is significantly modulated, the amorphous structure in the oxide semiconductor layer becomes unstable, and the TFT Since the instability and non-uniformity of the characteristics are caused, the difference in electron affinity is preferably 1.3 eV or less.

  Specifically, the oxygen concentration is controlled by forming the film in a condition where the oxygen partial pressure is relatively low when forming the second region, and for the first region, the oxygen partial pressure is relatively low when forming the film. Oxidation of the film is promoted by film formation under high conditions or by performing treatment with oxygen radicals or ozone irradiation after film formation in the first region, thereby reducing the amount of oxygen vacancies in the first region. Etc.

  Note that the amount of oxygen vacancies in the first region is preferably extremely small. Conventionally, when an oxide semiconductor layer is used as a channel layer, it is necessary to increase the carrier density to some extent in order to increase mobility, and oxygen vacancies are intentionally formed, that is, the oxygen concentration is lowered. However, when there are many oxygen vacancies, there is a problem that the oxygen vacancies themselves become a scatterer with respect to carriers, leading to a decrease in mobility. In the present invention, since the carrier as the channel layer is supplied from the second region, sufficient carrier density and accompanying mobility can be obtained even when the amount of oxygen vacancies in the first region is extremely small.

The thin film transistor of the present invention is the oxide first region A ₁ of the semiconductor layer b / (a + b), it is preferably smaller than the second region _{A 2 b / (a + b} ). Furthermore, it is desirable that the first area _{A 1} of b / (a + b) is 0.5 or less. More preferably, and in the first region _{A 1} in a / a + b is 0.6 or more, it is desirable that the second region _{A 2} b / a + b is 0.6 or more.

  By increasing the difference of b / (a + b) between the first region and the second region, the energy difference at the lower end of the conduction band increases, and it is possible to efficiently localize electron carriers in the first region. Become.

  In the present invention, Zn / In + Ga (corresponding to 2c / (a + b) in the above general formula) of the first region constituting the active layer is preferably 0.5 or more, and 2c / of the second region. (A + b) is preferably 0.5 or less. As 2c / (a + b) increases, the optical absorption edge shifts to the longer wavelength side, and by increasing 2c / (a + b), the band gap becomes narrower. Therefore, by disposing a relatively large 2c / (a + b) IGZO layer in the first region and disposing a relatively small 2c / (a + b) IGZO layer in the second region, the energy difference at the lower end of the conduction band. And the electron carriers can be localized in the first region. The method of controlling 2c / (a + b) can be applied to a film having a large difference of b / (a + b), so that a deeper well-type potential structure can be formed. It can be used even in the case of the same region.

  A deeper well-type potential structure can be obtained by doping part of Zn in the oxide semiconductor layer made of IGZO with element ions having a wider band gap. Specifically, the band gap of the film can be increased by doping Mg. For example, a deeper well-type potential structure can be formed by doping Mg only in the second region. In addition, by doping Mg in each region with a difference in b / (a + b) and 2c / (a + b) between the first region and the second region, In, Ga Compared with a system in which the composition ratio of only Zn is controlled, the entire band gap can be widened while maintaining the well barrier height.

  Since the blue light-emitting layer used in organic EL exhibits broad light emission having a peak at about λ = 450 nm, if the optical band gap of the IGZO film is relatively narrow and the region has optical absorption, There arises a problem that threshold shift occurs. Therefore, it is preferable that the material used for the channel layer has a larger band gap, particularly for a thin film transistor used for driving an organic EL.

When b / (a + b) is increased in IGZO, the optical absorption edge is shifted to the short wavelength side and the band gap is widened, but at the same time, the electrical conductivity is lowered by using a large composition of b / (a + b). That is, when an IGZO film having a large b / (a + b) is used alone for a thin film transistor, the desired transistor characteristics (specifically, mobility that exceeds several tens to 100 cm ² / Vs) can be obtained. (Refer to FIG. 15C.) In the present invention, a b / (a + b) large IGZO layer (second region) having a wide band gap and a b / (a + b) small IGZO layer (first region) having a relatively narrow band gap are joined. By using this structure, a well-type potential composed of a gate insulating film and an active layer is formed, and carriers can be localized in the first region.

  The carrier density in the first region can be arbitrarily controlled by the second oxygen deficiency control or cation doping. In order to increase the carrier density, the amount of oxygen vacancies in the second region may be increased, or a material (eg, Ti, Zr, Hf, Ta, etc.) that tends to become a cation having a relatively large valence may be doped. However, when doping a cation having a large valence, the number of constituent elements of the oxide semiconductor film increases, which is disadvantageous in terms of simplifying the film formation process and reducing the cost. ) To control the carrier density.

  Note that the oxide semiconductor layer is preferably amorphous in that film formation is possible at a temperature of 300 ° C. or lower. For example, an amorphous IGZO film can be formed at a substrate temperature of 200 ° C. or lower.

  The total film thickness (total film thickness) of the active layer 12 is preferably about 10 to 200 nm.

(Source / drain electrodes)
The source electrode 13 and the drain electrode 14 are not particularly limited as long as they have high conductivity. For example, metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, Al—Nd, tin oxide, and zinc oxide A metal oxide conductive film such as indium oxide, indium tin oxide (ITO), or indium zinc oxide (IZO) can be used as a single layer or a stacked structure of two or more layers.

  Each of the source electrode 13 and the drain electrode 14 is, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as CVD or a plasma CVD method, or the like. The film may be formed according to a method appropriately selected in consideration of suitability with the material to be used.

  When the source electrode 13 and the drain electrode 14 are made of the above metal, the thickness is preferably set to 10 nm or more and 1000 nm or less in consideration of the film forming property, the patterning property by etching or lift-off method, and the conductivity. 50 nm or more and 100 nm or less is more preferable.

(Gate insulation film)
The gate insulating film 15 is preferably one having high insulating properties, for example, an insulating film such as SiO ₂ , SiN _x , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , HfO ₂ , or the like. It can be composed of an insulating film containing at least two compounds.

  The gate insulating film 15 is a material used from a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as a CVD or plasma CVD method. The film may be formed according to a method appropriately selected in consideration of the suitability of

  Note that the gate insulating film 15 needs to have a sufficient thickness in order to reduce leakage current and improve voltage resistance. On the other hand, if the thickness is too large, the driving voltage increases. Although the thickness of the gate insulating film 15 depends on the material, it is preferably 10 nm to 10 μm, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.

(Gate electrode)
The gate electrode 16 is not particularly limited as long as it has high conductivity. For example, a metal such as Al, Mo, Cr, Ta, Ti, Au, Ag, Al—Nd, tin oxide, zinc oxide, indium oxide, A metal oxide conductive film such as indium tin oxide (ITO) or zinc indium oxide (IZO) can be used as a single layer or a stacked structure of two or more layers.

  The gate electrode 16 is a material used from, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. The film may be formed according to a method appropriately selected in consideration of the suitability of

  When the gate electrode 16 is made of the above metal, the thickness is preferably 10 nm or more and 1000 nm or less in consideration of film forming properties, patterning properties by etching or lift-off methods, conductivity, and the like, preferably 50 nm or more, More preferably, it is 200 nm or less.

(Thin Film Transistor Manufacturing Method)
A method for manufacturing the top gate-top contact type thin film transistor 1 shown in FIG. A substrate 11 is prepared, and an active layer (IGZO film) 12 is formed on the substrate 11 in the order of the second region A ₂ and the first region A ₁ by a film forming method such as sputtering. The active layer 12 is then patterned. Patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed on the remaining portion by photolithography, and the pattern is formed by etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid.

  Next, a metal film for forming the source / drain electrodes 13 and 14 is formed on the active layer 12. Next, the metal film is patterned into a predetermined shape by etching or a lift-off method to form the source electrode 13 and the drain electrode 14. At this time, it is preferable to pattern the source / drain electrodes 13 and 14 and wiring (not shown) connected to these electrodes simultaneously.

  After forming the source / drain electrodes 13 and 14 and the wiring, the gate insulating film 15 is formed. The gate insulating film 15 is patterned into a predetermined shape by photolithography and etching.

  After forming the gate insulating film 15, the gate electrode 16 is formed. After the electrode film is formed, it is patterned into a predetermined shape by etching or a lift-off method to form the gate electrode 16. At this time, it is preferable to pattern the gate electrode 16 and the gate wiring simultaneously.

  Through the above procedure, the thin film transistor 1 illustrated in FIG. 3A can be manufactured.

(Active layer deposition process)
Next, the process for forming the active layer will be described in more detail. The total film thickness (total film thickness) of the active layer 12 is preferably about 10 to 200 nm, and each region is preferably formed continuously without being exposed to the atmosphere. By continuously forming a film without being exposed to the atmosphere, more excellent transistor characteristics can be obtained as a result. In addition, since the number of film forming steps can be reduced, the manufacturing cost can also be reduced.

Here, description will be made on manufacturing a bottom gate type thin film transistor as shown in FIGS. As described above, when the bottom-gate thin film transistor is manufactured, the first region A ₁ and the second region A ₂ are formed in this order. Note that when the top-gate thin film transistor is manufactured, the active layer is formed in the order of the second region A ₂ and the first region A ₁ .

First, the formation of the first region _{A 1.} Here, for example, as the first region _{A 1, Ga / (In +} Ga) = 0.25, is formed to have a Zn / (In + Ga) = IGZO film thickness 10nm is 0.5.

  As a method for forming a film so as to have the composition ratio of the metal element as described above, in the case of sputtering film formation, a combination of In, Ga, Zn, or a combination of these oxides or a composite oxide of these is used. Sputtering may be used, or single sputtering of a complex oxide target in which the composition ratio of the metal elements in the IGZO film formed in advance is as described above may be used. The substrate temperature during film formation may be arbitrarily selected according to the substrate, but when a flexible substrate is used, the substrate temperature is preferably closer to room temperature.

  In the case of increasing the carrier density in the first region, the oxygen partial pressure in the film formation chamber during film formation is relatively lowered to reduce the oxygen concentration in the film. For example, the oxygen partial pressure / argon partial pressure during film formation is set to 0.005. Conversely, when the electron carrier density is lowered, is the oxygen partial pressure in the film formation chamber during film formation relatively high (for example, the oxygen partial pressure during film formation / argon partial pressure is set to 0.05)? The oxygen concentration in the film is increased by irradiating oxygen radicals during or after film formation, or by irradiating ultraviolet rays onto the surface of the film formation substrate in an ozone atmosphere.

  Next, the second region is formed. The film formation in the second region is a method in which the film formation is temporarily stopped after the film formation in the first region, the oxygen partial pressure in the film formation chamber and the power applied to the target are changed, and then the film formation is restarted. Alternatively, the oxygen partial pressure in the deposition chamber and the power applied to the target may be changed quickly or slowly without stopping the deposition. Further, the target may be a method in which the target used at the time of film formation in the first region is used as it is and the input power is changed, and when the film formation is switched from the first region to the second region, the first A method may be used in which power supply to the target used for the region deposition is stopped and power is applied to a different target. In addition to the target used for the deposition of the first region, a plurality of targets may be added. A method of additionally applying power may be used.

  Here, as the second region, for example, an IGZO film having a metal element composition ratio of Ga / (In + Ga) = 0.75 and Zn / (In + Ga) = 0.5 is formed to a thickness of 30 nm.

  The substrate temperature during film formation may be arbitrarily selected according to the substrate, but when a flexible substrate is used, the substrate temperature is preferably closer to room temperature.

  In order to increase the carrier density in the second region, the oxygen partial pressure in the film formation chamber during film formation is relatively lowered to reduce the oxygen concentration in the film. For example, the oxygen partial pressure / argon partial pressure during film formation is set to 0.005. Conversely, when the electron carrier density is lowered, is the oxygen partial pressure in the film formation chamber during film formation relatively high (for example, the oxygen partial pressure during film formation / argon partial pressure is set to 0.05)? The oxygen concentration in the film is increased by irradiating oxygen radicals during or after film formation, or by irradiating ultraviolet rays onto the surface of the film formation substrate in an ozone atmosphere. In the embodiment of the present invention, it is more preferable that the oxygen concentration in the first region is higher than the oxygen concentration in the second region.

Note that when the oxygen concentration in the film is increased by oxygen radical irradiation or ultraviolet irradiation in an ozone atmosphere, it may be performed both during and after the formation of the first region and the second region. Alternatively, it may be performed only after the second region is formed. The substrate temperature at the time of oxygen radical irradiation may be arbitrarily selected according to the substrate, but when a flexible substrate is used, the substrate temperature is preferably closer to room temperature.

  Further, annealing may be performed after the oxide semiconductor layer is formed. The annealing atmosphere can be arbitrarily selected according to the film, and the annealing temperature may be arbitrarily selected according to the substrate. However, when a flexible substrate is used, the annealing temperature is lower (for example, 200 ° C. or lower). ) Is preferably annealed. On the other hand, when a substrate having high heat resistance is used, annealing may be performed at a high temperature close to 500 ° C.

  FIG. 4 is a cross-sectional STEM image of a laminated film in which five layers of an IGZO film with Ga / (In + Ga) = 0.75 and an IGZO film with Ga / (In + Ga) = 0.25 are laminated. FIG. 4B shows the result of treatment at an annealing temperature of 250 ° C. immediately after lamination (before annealing treatment), and FIG. From FIG. 4, it can be confirmed that the laminated structure is maintained even if the annealing process is performed at 500 ° C.

  Note that the inventors of the present invention have made it possible to change the electron affinity of the IGZO layer according to the composition ratio of the cation and / or the oxygen concentration, and to make the IGZO layer having a small energy gap a well layer by adopting a well-type potential structure. It was confirmed by performing the following experiment that it can be used as

  As described above, the electron affinity χ is determined by the difference between the ionization potential I and the band gap energy Eg. The band gap energy Eg can be calculated using a Tauc plot by measuring the reflectance and transmittance of light. Here, the band gap energy Eg indicates a direct transition value. The ionization potential I can be obtained from photoelectron spectroscopy measurement.

(Dependence of electron affinity χ on cation composition ratio)
Samples 1 to 5 having different cation composition ratios were prepared, and the above measurements were performed to examine the dependence of the electron affinity χ on the cation composition ratio.

  First, IGZO film samples 1 to 5 having different cation composition ratios were prepared using an IGZO film as a measurement target. In samples 1 to 5, IGZO films having different cation composition ratios of Ga / (In + Ga) are formed on the substrates, respectively. In each sample, a synthetic quartz glass substrate (manufactured by Covalent Materials, product number T-4040) was used as the substrate.

Sample 1 is obtained by forming an IGZO film of Ga / (In + Ga) = 0 and Zn / (In + Ga) = 0.5 on a substrate so as to have a thickness of 100 nm. The oxygen partial pressure at the time of film formation / argon partial pressure was set to 0.01, and co-sputtering using an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target was performed. The substrate temperature in film formation was set to room temperature, the deposition chamber pressure during the deposition was maintained at all times 4.4 × 10 ^-1 Pa by automatically controlling the opening of the exhaust valve.

  Samples 2 to 5 were produced by the same production procedure as Sample 1 except that the value of Ga / (In + Ga) was different. Sample 2 is Ga / (In + Ga) = 0.25, Sample 3 is Ga / (In + Ga) = 0.5, Sample 4 is Ga / (In + Ga) = 0.75, Sample 5 is Ga / (In + Ga) ) = 1.

The control of the Ga / in each sample 1~5 (In + Ga) and Zn / (In + Ga) was performed by adjusting the power value to be put into _{In 2 O 3, Ga 2 O} 3, ZnO each target.

  FIG. 5 shows Tauc plots obtained from the results of the reflectance and transmittance measurements for each of Samples 1 to 5. It can be seen that the band gap energy increases as Ga / (In + Ga) increases.

  FIG. 6 shows the band gap energy of each sample derived from the Tauc plot shown in FIG. From this result, it was clarified that when Ga / (In + Ga) is increased from 0 to 1, the band gap energy is increased by about 1.2 to 1.3 eV.

  FIG. 7 shows the excitation light energy and the normalized photoelectron yield by photoelectron spectroscopy measurement for each sample 1-5. In the graph of FIG. 7, the excitation light energy at the rising edge of each curve, that is, the energy value at which photoelectron emission starts is the ionization potential.

  FIG. 8 is a graph showing the ionization potential of each sample 1 to 5 obtained from the graph of FIG. From FIG. 8, it is clear that the ionization potential takes the maximum value when Ga / (In + Ga) is around 0.5, and the ionization potential decreases as the distance from it becomes far.

The electron affinity χ of each sample 1 to 5 was determined from the difference between the previously obtained band gap energy Eg and the ionization potential I. Table 2 shown below lists the composition ratio, oxygen partial pressure / argon partial pressure, energy gap Eg, ionization potential I, and electron affinity χ of each sample.

  FIG. 9 shows the Ga / (In + Ga) dependence of the electron affinity obtained from the above results. It can be seen that the electron affinity χ has a maximum value when Ga / (In + Ga) is around 0.25, and decreases with increasing distance from it, and when Ga / (In + Ga) is increased from 0.25 to 1, the electron affinity is increased. It was found to be about 1.2 to 1.3 eV smaller.

As described above, it has become clear that the electron affinity can be changed by changing Ga / In + Ga. Therefore, in the oxide semiconductor layer made of IGZO, for example, when oxygen concentration modulation of the regions A ₁ and A ₂ is not performed, Ga / (In + Ga) in the region A ₁ is set to 0.25, and Ga in the region A ₂ is set. It can be seen that by setting / In + Ga to 0.75, a well structure having a potential difference of 0.48 eV between the regions A ₁ and A ₂ can be obtained.

(Dependence of electron affinity χ on oxygen concentration)
Samples 6 to 9 having different oxygen concentrations were prepared, and the dependence of the electron affinity χ, which was measured in the same manner, on the oxygen concentration was examined.

Samples 6 to 9 were obtained by forming an IGZO film as a measurement object in the same manner as described above, and forming the film on a similar substrate and a similar substrate. In Sample 6, Ga / (In + Ga) = 0.75, Zn / (In + Ga) = 0.5, and oxygen partial pressure / argon partial pressure during film formation = 0. Sample 7 was the same as Sample 6 except that the oxygen partial pressure at the time of film formation / argon partial pressure was 0.01. In sample 8, Ga / (In + Ga) = 0.25, Zn / (In + Ga) = 0.5, and oxygen partial pressure / argon partial pressure during film formation = 0. Sample 9 is the same as sample 8, but the oxygen partial pressure at the time of film formation / argon partial pressure was set to 0.01. Table 3 shows the composition ratio, oxygen partial pressure / argon partial pressure, energy gap described later, and the like of the manufactured samples 6 to 9.

  FIGS. 10A and 10B show Tauc plots of the results of measuring reflectance and transmittance for each sample 6-9. FIG. 10A is a Tauc plot for samples 6 and 7 with Ga / (In + Ga) of 0.75, and FIG. 10B is a Tauc plot for samples 8 and 9 with Ga / (In + Ga) of 0.25. In any case, it was found that the band gap energy Eg did not change greatly even when the oxygen partial pressure / argon partial pressure during film formation was changed.

  FIG. 11 is a graph in which the band gap energy of each sample derived from the Tauc plot shown in FIGS. 10A and 10B is plotted with the oxygen partial pressure / argon partial pressure on the horizontal axis. From this result, it was clarified that the band gap energy hardly changed even when the oxygen partial pressure / argon partial pressure was changed.

  12A shows the excitation light energy and the normalized photoelectron yield of the samples 6 and 7, and FIG. 12B shows the photoelectron spectroscopy measurement of the samples 8 and 9. FIG. 13 shows the results of FIG. It shows the ionization potential of each sample obtained from the graph of FIG. From the results shown in FIG. 13, it was found that the ionization potential increased as the oxygen partial pressure / argon partial pressure during film formation increased even when the value of Ga / (In + Ga) was different.

  The electron affinity χ of each sample 6 to 9 was determined from the difference between the previously obtained band gap energy Eg and ionization potential I (see Table 3).

  FIG. 14 shows the dependence of electron affinity on oxygen partial pressure / argon partial pressure during film formation, obtained from the above results. It has been clarified that the electron affinity χ increases as the oxygen partial pressure / argon partial pressure during film formation increases. When the oxygen partial pressure / argon partial pressure during film formation is increased from 0 to 0.01, the electron affinity increases by about 0.2 eV in both cases where the value of Ga / (In + Ga) is 0.75 or 0.25. I understood that.

  As described above, the electron affinity can be changed by changing the oxygen partial pressure / argon partial pressure during film formation. More specifically, the electron affinity can be changed by increasing the oxygen partial pressure / argon partial pressure. It became clear that can be increased.

Therefore, in the oxide semiconductor layer made of IGZO, for example, in addition to the electron affinity difference given by modulating b / (a + b) of the region A ₁ and the region A ₂ , the oxygen partial pressure during the formation of the region A ₁ / argon partial pressure, by larger than the oxygen partial pressure / argon partial pressure in region a ₂ deposition, it is possible to obtain a larger electron affinity difference.

  In general, when the oxygen partial pressure / argon partial pressure during film formation is large, the oxygen concentration in the film is high. Conversely, when the oxygen partial pressure / argon partial pressure during film formation is small, the oxygen concentration is low. The above results mean that the electron affinity increases as the oxygen concentration in the film increases.

  In this experiment, a method of increasing the oxygen partial pressure / argon partial pressure during film formation was adopted as a method for increasing the oxygen concentration in the film, but in addition, an ozone atmosphere in which oxygen radicals are irradiated on the film formation surface. Even if a method such as irradiating the film formation surface with ultraviolet rays is employed, the oxygen concentration in the film can be similarly increased.

Modulation of modulation and film oxygen concentration of the above-mentioned Ga / (In + Ga) is applicable at the same time, for example, a first region _{A 1,} Ga / (In + Ga) = 0.25 compositional ratio, and and the oxygen concentration in the film high (oxygen partial pressure / argon partial pressure during film formation = 0.01) IGZO film (sample 9 in Table 3), the second region _{a 2, Ga / (in +} Ga) = 0. By using a structure sandwiched between IGZO films (sample 6 in Table 3) with a composition ratio of around 75 and a low oxygen concentration in the film (oxygen partial pressure at the time of film formation / argon partial pressure = 0), Alternatively, a well-type barrier structure (electron affinity difference Δχ = 0.65) deeper than that obtained when only the oxygen concentration is modulated can be obtained.

  Here, experiments conducted on carrier concentration and mobility in the IGZO film will be described. The carrier concentration and mobility can be obtained by measuring the Hall effect and specific resistance.

  FIGS. 15A to 15C show the Ga / (In + Ga) dependence of the specific resistance, carrier density, and mobility in the IGZO film produced by changing the oxygen partial pressure / argon partial pressure. . In FIG. 15, ● represents the oxygen partial pressure / argon partial pressure of 0.01, ■ represents the oxygen partial pressure / argon partial pressure of 0.005, and ▲ represents the data for the oxygen partial pressure / argon partial pressure of 0. is there.

  The sample used for the measurement was prepared by the same method as described above. A Hall measuring device (manufactured by Toyo Technica, Hall effect / specific resistance measuring device Resett 8300) was used for measuring the Hall effect and the specific resistance.

  FIG. 15B shows that the carrier density can be independently controlled by changing Ga / (In + Ga) or oxygen partial pressure / argon partial pressure. For example, by making Ga / (In + Ga) constant and changing only the oxygen partial pressure / argon partial pressure, only the carrier concentration in the film can be arbitrarily adjusted without changing the band gap of the film. However, when the oxygen partial pressure / argon partial pressure is 0, the carrier concentration can be arbitrarily controlled by changing Ga / (In + Ga), but the mobility is low as shown in FIG. You can see that it remains. From this result, it was found that the mobility improvement that is obtained by simply increasing the amount of oxygen deficiency and increasing the carrier concentration cannot be obtained.

  Next, a result of comparison of carrier concentration and mobility between the IGZO single layer film and the laminated structure will be described.

  As a laminated structure, an IGZO film having a composition ratio of sample 7 (0.25) −oxygen partial pressure / argon partial pressure (0.01) of 10 nm was formed on the substrate, and then the composition ratio of sample 6 ( A Hall element having a film thickness of 0.75) -oxygen partial pressure / argon partial pressure (0) of 50 nm was produced.

  As single films, single film Hall elements of Sample 7 (IGZO-0.25-0.01) and Sample 6 (IGZO-0.75-0) were prepared.

  Compared with the carrier concentration of a single film in each region, or compared with a carrier concentration value expected from a simple average when single films are laminated, the laminated structure has increased carrier density and mobility. This means that a well-type potential has been formed and electrons have moved to the well layer.

  Although the use of the thin film transistor of the present invention described above is not particularly limited, for example, in a display device (for example, a liquid crystal display device, an organic EL (Electro Luminescence) display device, an inorganic EL display device, etc.) as an electro-optical device. It is suitable as a drive element.

  Furthermore, the electronic device of the present invention is a device such as a flexible display that can be manufactured by a low-temperature process using a resin substrate, an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor), an X-ray sensor, or the like. It is suitably used as a drive element (drive circuit) in various electronic devices such as various sensors and MEMS (Micro Electro Mechanical System).

  Both the display device and the sensor of the present invention using the thin film transistor of the present invention exhibit good characteristics due to low power consumption. The “characteristic” referred to here is a display characteristic in the case of a display device, and a sensitivity characteristic in the case of a sensor.

<Liquid crystal display device>
FIG. 16 is a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the present invention, and FIG. 17 is a schematic configuration diagram of the electric wiring.

  As shown in FIG. 16, the liquid crystal display device 5 of this embodiment includes a top gate type thin film transistor 1 shown in FIG. 3A, a pixel lower electrode 55 on the gate electrode 16 protected by the passivation layer 54 of the transistor 1, and A liquid crystal layer 57 sandwiched between the opposing upper electrodes 56 and an RGB color filter 58 for developing different colors corresponding to each pixel are provided, and polarizing plates 59a are provided on the substrate 11 side of the TFT 10 and on the color filter 58, respectively. , 59b.

  In addition, as shown in FIG. 17, the liquid crystal display device 5 of this embodiment includes a plurality of gate lines 51 that are parallel to each other and data lines 52 that are parallel to each other and intersect the gate lines 51. Here, the gate wiring 51 and the data wiring 52 are electrically insulated. The thin film transistor 1 is provided in the vicinity of the intersection between the gate line 51 and the data line 52.

  The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 51, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 52. The drain electrode 14 of the thin film transistor 1 is connected to the pixel lower electrode 55 through a contact hole 19 provided in the gate insulating film 15 (a conductor is embedded in the contact hole 19). The pixel lower electrode 55 and the grounded counter electrode 56 constitute a capacitor 53.

  In the liquid crystal device of this embodiment shown in FIG. 16, the top gate type thin film transistor is provided. However, the thin film transistor used in the liquid crystal device which is the display device of the present invention is not limited to the top gate type, A bottom-gate thin film transistor may be used.

  Since the thin film transistor of the present invention has high mobility, high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, which is suitable for a large screen. In addition, when the active layer IGZO is amorphous, variations in device characteristics can be suppressed, and an excellent display quality with a large screen and no unevenness can be realized. In addition, since the characteristic shift is small, the gate voltage can be reduced, and thus the power consumption of the display device can be reduced. In addition, according to the present invention, a thin film transistor can be manufactured using an amorphous IGZO film that can be formed at a low temperature (for example, 200 ° C. or lower) as a semiconductor layer. Therefore, a resin substrate (plastic substrate) is used as a substrate. Can be used. Therefore, according to the present invention, a flexible liquid crystal display device excellent in display quality can be provided.

<Organic EL display device>
FIG. 18 is a schematic sectional view of a part of an active matrix organic EL display device according to an embodiment of the electro-optical device of the present invention, and FIG. 19 is a schematic configuration diagram of electrical wiring.

There are two types of driving methods for organic EL display devices: a simple matrix method and an active matrix method. The simple matrix method has an advantage that it can be manufactured at low cost. However, since the pixels are emitted by selecting one scanning line at a time, the number of scanning lines and the light emission time per scanning line are inversely proportional. Therefore, it is difficult to increase the definition and increase the screen size. The active matrix method has a high manufacturing cost because a transistor and a capacitor are formed for each pixel. However, since there is no problem that the number of scanning lines cannot be increased unlike the simple matrix method, it is suitable for high definition and large screen.

  In the active matrix type organic EL display device 6 of the present embodiment, the top gate type thin film transistor 1 shown in FIG. 3A is provided as a driving 1a and a switching 1b on a substrate 60 provided with a passivation layer 61a. An organic light emitting element 65 including an organic light emitting layer 64 sandwiched between the lower electrode 62 and the upper electrode 63 is provided on the transistors 1a and 1b, and the upper surface is also protected by the passivation layer 61b.

  Further, as shown in FIG. 19, the organic EL display device 7 of the present embodiment includes a plurality of gate lines 66 parallel to each other, and data lines 67 and drive lines 68 that intersect the gate lines 66 and are parallel to each other. I have. Here, the gate wiring 66, the data wiring 67, and the driving wiring 68 are electrically insulated. The gate electrode 16 a of the switching thin film transistor 1 b is connected to the gate wiring 66, and the source electrode 13 b of the switching thin film transistor 1 b is connected to the data wiring 67. The drain electrode 14b of the switching thin film transistor 1b is connected to the gate electrode 16a of the driving thin film transistor 1a, and the driving thin film transistor 1a is kept on by using the capacitor 69. The source electrode 13 a of the driving thin film transistor 1 a is connected to the driving wiring 68, and the drain electrode 14 a is connected to the organic EL light emitting element 65.

  The organic EL device of this embodiment shown in FIG. 18 includes the top gate type thin film transistors 1a and 1b. However, the thin film transistor used in the organic EL device which is the display device of the present invention is a top gate type. Without limitation, a bottom-gate thin film transistor may be used.

  Since the thin film transistor of the present invention has high mobility, display with low power consumption and high quality is possible. In addition, according to the present invention, a thin film transistor can be manufactured using an amorphous IGZO film that can be formed at a low temperature (for example, 200 ° C. or lower) as a semiconductor layer. Therefore, a resin substrate (plastic substrate) is used as a substrate. Can be used. Therefore, according to the present invention, a flexible organic EL display device having excellent display quality can be provided.

  In the organic EL display device shown in FIG. 18, the top electrode 63 may be a top emission type with a transparent electrode, or the bottom electrode 62 and each TFT electrode may be a transparent electrode.

<X-ray sensor>
FIG. 20 shows a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention, and FIG. 21 shows a schematic configuration diagram of its electric wiring.

  FIG. 20 is an enlarged schematic cross-sectional view of a part of the X-ray sensor array, more specifically. The X-ray sensor 7 of this embodiment includes a thin film transistor 1 and a capacitor 70 formed on a substrate, a charge collection electrode 71 formed on the capacitor 70, an X-ray conversion layer 72, and an upper electrode 73. Composed. A passivation film 75 is provided on the thin film transistor 1.

  The capacitor 70 has a structure in which an insulating film 78 is sandwiched between a capacitor lower electrode 76 and a capacitor upper electrode 77. The capacitor upper electrode 77 is connected to one of the source electrode 13 and the drain electrode 14 (the drain electrode 14 in FIG. 20) of the thin film transistor 1 through a contact hole 79 provided in the insulating film 78.

  The charge collection electrode 71 is provided on the capacitor upper electrode 77 in the capacitor 70 and is in contact with the capacitor upper electrode 77. The X-ray conversion layer 72 is a layer made of amorphous selenium, and is provided so as to cover the thin film transistor 1 and the capacitor 70. The upper electrode 73 is provided on the X-ray conversion layer 72 and is in contact with the X-ray conversion layer 72.

  As shown in FIG. 21, the X-ray sensor 7 of the present embodiment includes a plurality of gate wirings 81 that are parallel to each other and a plurality of data wirings 82 that intersect with the gate wirings 81 and are parallel to each other. Here, the gate wiring 81 and the data wiring 82 are electrically insulated. The thin film transistor 1 is provided in the vicinity of the intersection between the gate wiring 81 and the data wiring 82.

  The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 81, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 82. The drain electrode 14 of the thin film transistor 1 is connected to a charge collecting electrode 71, and the charge collecting electrode 71 constitutes a capacitor 70 together with a grounded counter electrode 76.

  In the X-ray sensor 7 of this configuration, X-rays are irradiated from the upper part (upper electrode 73 side) in FIG. 21, and electron-hole pairs are generated in the X-ray conversion layer 72. By applying a high electric field to the X-ray conversion layer 72 by the upper electrode 73, the generated charges are accumulated in the capacitor 70 and read out by sequentially scanning the thin film transistor 1.

  Since the X-ray sensor of the present invention includes the thin film transistor 1 having a high on-current and excellent reliability, the S / N is high and the sensitivity characteristic is excellent. Therefore, the X-ray sensor has a wide dynamic when used in an X-ray digital imaging apparatus. A range image is obtained. In particular, the X-ray digital imaging apparatus of the present invention is suitable not only for still image shooting but also for an X-ray digital imaging apparatus that can perform fluoroscopy with a moving image and still image shooting. Further, when IGZO of the active layer in the thin film transistor is amorphous, an image with excellent uniformity can be obtained.

  In the X-ray sensor of this embodiment shown in FIG. 20, the top gate type thin film transistor is provided. However, the thin film transistor used in the sensor of the present invention is not limited to the top gate type, and the bottom gate type. A thin film transistor may be used.

Examples 1, 2, and 3 and Comparative Examples 1 and 2 were prepared for the bottom gate type thin film transistor, and the mobility was compared. Table 4 is a table showing Ga / (In + Ga) and oxygen partial pressure / argon partial pressure and mobility during film formation of each transistor.

<Example 1>
A bottom gate, top contact type thin film transistor was manufactured as Example 1. As the substrate, a highly doped p-type silicon substrate (manufactured by Mitsubishi Materials Corporation) having a SiO ₂ oxide film of 100 nm formed on the surface was used. The oxide semiconductor layer is consisted of IGZO, first, as the first region _{A 1, Ga / (In +} Ga) = 0.25, was 5nm sputtering a Zn / (In + Ga) = 0.5 and a InGaZnO film after, the second region _{a 2, Ga / (in +} Ga) = 0.75, was 30nm sputtering an IGZO film of Zn / (in + Ga) = 0.5. The oxide semiconductor layer was continuously formed between the regions without being exposed to the atmosphere. Sputtering of each region was performed by co-sputtering using an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target. The film thickness in each region was adjusted by adjusting the film formation time. The detailed sputtering conditions for each region are as follows.

(First area _{A 1} of the sputtering conditions)
Ultimate vacuum: 6 × 10 ⁻⁶ Pa
Deposition pressure: 4.4 × 10 ⁻¹ Pa
Deposition temperature; room temperature oxygen partial pressure / argon partial pressure; 0.02
Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , ZnO target; 43.0: 38.0: 19.0

(Second sputtering conditions of a region _{A 2)}
Ultimate vacuum: 6 × 10 ⁻⁶ Pa
Deposition pressure: 4.4 × 10 ⁻¹ Pa
Deposition temperature; room temperature oxygen partial pressure / argon partial pressure; 0.005
Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , ZnO target; 14.7: 67.8: 17.5

  After stacking the oxide semiconductor layer by sputtering, an ohmic contact made of Ti (10 nm) / Au (40 nm) was formed on the stacked film by vacuum vapor deposition through a metal mask.

  Thus, Example 1 of bottom-gate thin film transistor 1 having a channel length of 180 μm and a channel width of 1 mm was obtained.

<Example 2>
The element structure is the same as that of Example 1, and only the composition of the oxide semiconductor layer is different. First, as the first area _{A 1,} the Ga / (In + Ga) = 0.375, Zn / (In + Ga) = IGZO film after 5nm sputtering the second region _{A 2} is 0.5, Ga An IGZO film of /(In+Ga)=0.625 and Zn / (In + Ga) = 0.5 was formed by sputtering at 30 nm. The oxide semiconductor layer was continuously formed between the regions without being exposed to the atmosphere. Sputtering of each region was performed by co-sputtering using an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target. The film thickness in each region was adjusted by adjusting the film formation time. The detailed sputtering conditions for each region are as follows.

(First area _{A 1} of the sputtering conditions)
Ultimate vacuum: 6 × 10 ⁻⁶ Pa
Deposition pressure: 4.4 × 10 ⁻¹ Pa
Deposition temperature; room temperature oxygen partial pressure / argon partial pressure; 0.02
Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , ZnO target; 39.5: 50.0: 18.0

(Second sputtering conditions of a region _{A 2)}
Ultimate vacuum: 6 × 10 ⁻⁶ Pa
Deposition pressure: 4.4 × 10 ⁻¹ Pa
Deposition temperature; room temperature oxygen partial pressure / argon partial pressure; 0.005
Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , ZnO target; 20.5: 61.0: 17.0

<Example 3>
The element structure is the same as that of Example 1, and the composition of the oxide semiconductor layer and the oxygen concentration are different. First, as the first area _{A 1,} the Ga / (In + Ga) = 0.0, Zn / (In + Ga) = IGZO film after 5nm sputtering the second region _{A 2} is 0.5, Ga An IGZO film of /(In+Ga)=1.0 and Zn / (In + Ga) = 0.5 was formed by sputtering at 30 nm. The oxide semiconductor layer was continuously formed between the regions without being exposed to the atmosphere. Sputtering of each region was performed by co-sputtering using an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target. The film thickness in each region was adjusted by adjusting the film formation time. The detailed sputtering conditions for each region are as follows.

(First area _{A 1} of the sputtering conditions)
Ultimate vacuum: 6 × 10 ⁻⁶ Pa
Deposition pressure: 4.4 × 10 ⁻¹ Pa
Deposition temperature: room temperature oxygen partial pressure / argon partial pressure; 0.067
Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , ZnO target; 55.0: 0.0: 13.0

(Second area _{A 1} of the sputtering conditions)
Ultimate vacuum: 6 × 10 ⁻⁶ Pa
Deposition pressure: 4.4 × 10 ⁻¹ Pa
Deposition temperature; room temperature oxygen partial pressure / argon partial pressure; 0.005
Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , ZnO target; 0.0: 60.0: 15.0

<Comparative Example 1>
In the film formation of the oxide semiconductor of Example 1, composition in the layer thickness direction and oxygen modulation were not performed, the input power ratio was 31.5: 61.0: 20.0, and the oxygen partial pressure / argon partial pressure was set to 0.00. Comparative Example 1 was obtained by forming a thin film transistor by the same method as in Example 1 except that only an IGZO film was formed to a thickness of 45 nm under the condition of 002. This is a conventional transistor having an IGZO single film of In: Ga: Zn = 1: 1: 1 composition (Ga / (In + Ga) = 0.5) as an active layer, and a well-type potential structure is formed in the layer thickness direction. If not.

<Comparative example 2>
A comparative example in which a thin film transistor was manufactured in the same manner as in Example 1 except that the first region was formed and the second region was not formed in the formation of the oxide semiconductor layer of Example 1 2. In Comparative Example 2, the well-type potential structure is not formed in the layer thickness direction, and the second region serving as the carrier supply layer is not included in the structure.

  With respect to Examples 1, 2, and 3 and Comparative Examples 1 and 2, transistor characteristics (Vg-Id characteristics) and mobility μ were measured using a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies). The measurement results are shown in FIG. Vg-Id characteristics are measured by fixing the drain voltage (Vd) to 10V, changing the gate voltage (Vg) within the range of -15V to + 15V, and measuring the drain current (Id) at each gate voltage (Vg). I went to do it.

As shown in Table 4, in Examples 1, 2, and 3 having a well-type potential structure, a mobility of 20 cm ² / Vs or more is obtained, and in Example 3, the mobility is as high as 57.4 cm ² / Vs. was gotten. On the other hand, in Comparative Example 1 where there is no composition / oxygen concentration modulation in the layer thickness direction, a mobility of about 11 cm ² / Vs, which is an average value as a conventional IGZO single film transistor, was obtained. In Comparative Example 2 in which the second region was not formed, although the transistor was driven, the mobility was 0.029 cm ² / Vs, which was greatly reduced as compared with the laminated TFT element. This means that since the second region is a carrier supply layer, a sufficient carrier concentration could not be obtained in Comparative Example 2 having no carrier supply layer.

FIG. 23 shows the dependence of the mobility μ on the potential depth Δχ in Examples 1, 2, 3 and Comparative Example 1. Here, Δχ is calculated on the assumption that the electron affinity difference due to the oxygen concentration modulation is about 0.1 eV in addition to the modulation of b / (a + b). It can be seen that the mobility increases as the potential depth Δχ is increased. From this figure, by setting Δχ = 0.17 eV or more, a mobility of 20 cm ² / Vs, which is almost twice the mobility of the IGZO single film, can be obtained, and a low power consumption and high-quality display device or A highly sensitive X-ray sensor or the like can be provided. Accordingly, in the transistor of the present invention, the difference in electron affinity between the first and second regions is preferably 0.17 eV or more.

1, 2, 3, 4 Thin film transistor 11 Substrate 12 Oxide semiconductor layer 13 Source electrode 14 Drain electrode 15 Gate insulating film 16 Gate electrode A _First region of oxide semiconductor layer A _{2 Second} region of oxide semiconductor layer

Claims (15)

A thin film transistor having an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate,
The active layer is disposed on the gate electrode side through the gate insulating film, the first region having a first electron affinity, and the first electron disposed on the side far from the gate electrode. A second region having a second electron affinity less than the affinity,
In the film thickness direction of the active layer, a well-type potential is formed in which the first region is a well layer, and the second region and the gate insulating film are barrier layers.
The active layer is an oxide semiconductor layer made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) (where a, b, and c are a ≧ 0 and b ≧, respectively) 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, c + a ≠ 0).
Wherein b / a second region (a + b) is much larger than the b / (a + b) of the first region,
A thin film transistor , wherein an oxygen concentration in the first region is higher than an oxygen concentration in the second region .   2. The thin film transistor according to claim 1, wherein a difference between an electron affinity of the first region and an electron affinity of the second region is 0.17 eV or more and 1.3 eV or less.   The thin film transistor according to claim 2, wherein a difference between an electron affinity of the first region and an electron affinity of the second region is 0.32 eV or more and 1.3 eV or less.   The thin film transistor according to claim 1, wherein the oxide semiconductor layer is amorphous.   5. The thin film transistor according to claim 1, wherein b / (a + b) of the first region is smaller than 0.5 in the oxide semiconductor layer.   In the oxide semiconductor layer, b / (a + b) of the first region is smaller than 0.4, and b / (a + b) of the second region is 0.6 or more. The thin film transistor according to claim 5. Characterized in that said substrate is of a flexible, thin film transistor according to any one of claims 1 6. A thin film transistor having an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate,
The active layer is disposed on the gate electrode side through the gate insulating film, the first region having a first electron affinity, and the first electron disposed on the side far from the gate electrode. A second region having a second electron affinity smaller than the affinity, and in the film thickness direction of the active layer, the first region is a well layer, and the second region and the gate insulating film are barriers As the active layer, an oxide semiconductor layer composed of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) (here, a, b , C, respectively, a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, c + a ≠ 0).
In the film forming step , under the condition that the film forming chamber is set to the first oxygen partial pressure / argon partial pressure so that the oxygen concentration in the first region is larger than the oxygen concentration in the second region. under conditions wherein the first region is formed, and the deposition chamber and the first oxygen partial pressure / argon partial second smaller than pressure of oxygen partial pressure / argon partial pressure, said first region A method of manufacturing a thin film transistor, wherein the second region having a composition ratio of b / (a + b) larger than b / (a + b) is formed. A thin film transistor having an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate,
The active layer is disposed on the gate electrode side through the gate insulating film, the first region having a first electron affinity, and the first electron disposed on the side far from the gate electrode. A second region having a second electron affinity smaller than the affinity, and in the film thickness direction of the active layer, the first region is a well layer, and the second region and the gate insulating film are barriers As the active layer, an oxide semiconductor layer composed of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) (here, a, b , C, respectively, a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, c + a ≠ 0).
The film forming step includes the step of forming the first region and the second region having a composition ratio of b / (a + b) larger than b / (a + b) of the first region, The first region is formed during and / or after the first region is deposited so that the oxygen concentration in the first region is greater than the oxygen concentration in the second region . A method for manufacturing a thin film transistor, comprising a step of irradiating an oxygen-containing radical on a film formation surface in one region. A thin film transistor having an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate,
The active layer is disposed on the gate electrode side through the gate insulating film, the first region having a first electron affinity, and the first electron disposed on the side far from the gate electrode. A second region having a second electron affinity smaller than the affinity, and in the film thickness direction of the active layer, the first region is a well layer, and the second region and the gate insulating film are barriers As the active layer, an oxide semiconductor layer composed of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) (here, a, b , C, respectively, a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, c + a ≠ 0).
The film forming step includes the step of forming the first region and the second region having a composition ratio of b / (a + b) larger than b / (a + b) of the first region, In the ozone atmosphere during the formation of the first region and / or after the formation of the first region so that the oxygen concentration of the first region is higher than the oxygen concentration of the second region. And a step of irradiating the film formation surface of the first region with ultraviolet rays. The method for manufacturing a thin film transistor according to claim 8 , wherein the film formation substrate is not exposed to the atmosphere during the film formation step. Display device characterized by comprising a thin film transistor of claims 1 to 7 any one of claims. Image sensor characterized by comprising a thin film transistor according to claim 1 to 7 any one. X-ray sensor, characterized by comprising a thin film transistor of claims 1 to 7 any one of claims. An X-ray digital imaging apparatus comprising the X-ray sensor according to claim 14 .