KR101616264B1 - Circuit and Method for Generating Control Signal for Static RAM, and Static RAM Comprising the same Circuit - Google Patents

Abstract

A control signal generation circuit for a static random access memory (SRAM), a method thereof, and a static RAM having the generation circuit are disclosed. The control signal generation circuit of the present invention uses at least one cell column selected from the cell arrays of the ram as a tracking cell column. Therefore, it is not necessary to have a separate duplicate or dummy word line. The control signal generation circuit of the present invention is configured such that when one of the word lines is driven to a logic high to start a write operation, the voltage variation in the bit line of the tracking cell column is tracked to generate the tracking signal TRKBL, The timing required for the read or write operation can be controlled.

Description

Technical Field [0001] The present invention relates to a static RAM control signal generating circuit and a static random access memory (SRAM)

The present invention is not limited to the use of actual memory cells that are operated by the original word lines, rather than replicate cells or dummy cells that partially modify the actual memory cells operating by the replicated word lines, A control signal generation circuit for a static RAM that generates various control signals by tracking a voltage variation, a static RAM and a method therefor.

The demand for high-speed access to embedded memory and low power consumption continues to grow. The same is true for the design of static random access memory (SRAM) (hereinafter referred to as "SRAM"). The high-speed access and low-power processing in the SRAM is also related to the precise timing of the sense amplifier enable (SAE) signal for operating the sense amplifier in the read operation, As shown in FIG.

In the memory reading process, if the sense amplifier is enabled too early before the bit line is fully matured, the differential voltage of the bit line pair becomes insufficient , The sense amplifier may not be able to accurately read the data value stored in the corresponding cell. Therefore, the sense amplifier enable signal must be provided in such a state that the difference voltage between the two bit lines is larger than the offset voltage of the sense amplifier.

However, if the sense amplifier is excessively delayed and enabled, not only the access time is prolonged but also the voltage difference in the bit line becomes unnecessarily large, thereby unnecessary power consumption becomes large. Considering the access time, it is good that the sense amplifier is enabled as soon as possible, but it is not desirable to enable it too early, as mentioned above. As such, the precise timing of the sense amplifier enable signal has a decisive influence on not only memory performance but also power consumption.

Of the methods for increasing the accuracy of the sense amplifier enable signal, a technique that has been attracting attention in the past is the 'replica bit line tracking (RBL) using a replica bit line (RBL)' or a 'dummy bit line Method '. In this method, a replica column or a dummy column for tracking the Variation part of the memory operation is added to the cell array, and the bit line of the replica column is referred to as a 'replica bit line (RBL)' .

The specific replica cell in the replica column is activated with a separate control signal (e.g., a separate dummy word line) so that the replica bit line RBL tracks the voltage variation of the original bit line BL as it is. Since the replica cell participating in tracking uses the original memory cell in some modification and operates under the same conditions, it is possible to generate an accurate sense amplifier enable signal despite the so-called process voltage-temperature variation ≪ / RTI > On the other hand, since a separate dummy word line must be used, the remaining replica cells other than the replica cells participating in tracking in the replica column are independent of tracking and are formed through a separate re-routing process in the manufacturing process.

For example, Korean Patent Publication No. 2310-0127276 (entitled " Enhanced Bit Line Tracking in High Performance Memory Compilers ") discloses a method of tracking using dummy bit lines.

Referring to FIG. 1, the memory of the present invention further includes a dummy column connected to the dummy bit line DBL in addition to the original memory cell 114, and a dummy word line DWL, which is a separate control signal, A dummy pull-down device 116, which is operated by the dummy word line DWL and the dummy bit line DBL, is also provided. The dummy pull down device 116 is a replica cell designed to operate identically to the original memory cell 114.

The dummy word line DWL is also activated when one of the word lines is activated so that the corresponding pull down device 116 is activated and the voltage of the precharged dummy bit line DBL is applied to the pull down device 116. [ Lt; / RTI > The control module 120 generates a sense amplifier enable signal at a point of time when a voltage of the dummy bit line DBL falls below a predetermined threshold voltage and a predetermined gate delay is added again. At this time, the predetermined threshold voltage for the dummy bit line is designed to be lower than the offset voltage of the sense amplifier 130, and the gate delay is adjusted to generate an accurate sense enable signal.

However, since the voltage at the bit line BL and the voltage at the dummy bit line DBL do not actually vary equally and it is difficult to match the gate delay for reasons such as the manufacturing process, the accurate timing of the sense amplifier enable signal Tracking is impossible. Meanwhile, in order to solve this problem, the invention of FIG. 1 suggests a method of enabling a dummy word line before an actual word line. However, the same is true for this method, in which a separate dummy pull-down device is used which is operated by a separate dummy word line.

Since the tracking arrangements including the dummy bit line (DBL), the dummy word line (DWL), and the dummy cell are formed by the re-routing process among the recent high-integration SRAM fabrication methods, the shape of the dummy cell is different from that of the original memory cell . Therefore, in the case of the duplicate bit line scheme, there is always a problem that the dummy bit line DBL may not be able to substantially replicate the original bit line BL.

On the other hand, in the write operation, in a state in which the bit line and the bit line bar are precharged, the row decoder operates the word line arranged in the cell in which the data is written, and the write driver supplies the logical value according to the data to be stored in the cell to the data line DL and the data line bar DLB. The voltages of the bit lines and the bit line bars connected to the data line DL and the data line bar DLB are also made logic high or logic low by the column decoder so that the write process is performed while changing the internal node voltage. The write operation ends with the word line again being a logic low.

Various methods for tracking the cell operation for precise timing of the sense amplifier enable signal in the read operation are presented, but the tracking method for timing control of the write process is not adequately presented.

[Related Technical Literature]

1. Korean Patent Publication No. 2310-0127276 (entitled Improved Bit Line Tracking in High Performance Memory Compilers)

It is an object of the present invention to track voltage fluctuations in a bit line or a bit line bar using actual memory cells operated by original word lines without using duplicate cells or dummy cells operated by replicated word lines Thereby generating a control signal, and a method thereof.

In order to achieve the above object, a control signal generation circuit for a static random access memory (SRAM) according to the present invention uses a cell column (hereinafter referred to as a first tracking cell column) selected from among the cell arrays of the RAM. A first tracking cell column is accessed by a plurality of word lines for the cell array.

Accordingly, the control signal generation circuit of the present invention includes one bit line selected from the first bit line pairs arranged in the first tracking cell column, a write tracking section, a tracking signal generation section, And a generating unit.

The write tracking unit is connected to the selected bit line at a common node and operates when one of the plurality of word lines operates and data is written to the data line and the data line bar during the write operation initiated to drop the node voltage to ground .

The tracking signal generator generates a tracking signal when the voltage of the node becomes lower than a predetermined reference voltage. According to an embodiment, the tracking signal generator may be designed to have the reference voltage at a logic threshold voltage.

The control signal generation unit provides the row decoder with a control signal for terminating the operation of the word line being operated using the tracking signal. This completes the write operation.

According to an embodiment, the control signal generation circuit may further utilize at least one other tracking cell column. In this case, a bit line selected from the other bit line pairs arranged in the other tracking cell columns is connected to the node. In this case, the control signal generation circuit further includes a pass gate circuit section for interrupting the connection between the selected bit lines and the node separately from the first bit line pair, It is possible to cope with defective cell column and the like.

As a specific example, the tracking signal generating unit may include a pull-up PMOS transistor having the gate connected to the node and turned on at the reference voltage, and an inverter for inverting the output of the drain terminal of the PMOS transistor to output the tracking signal Can be implemented.

The light tracking unit includes two pull-up PMOS transistors and an NMOS transistor. The two pull-up PMOS transistors are switched by receiving the data line and the data line bar respectively to the gate terminal thereof, so that when the data line and the data line bar are driven, either one of them is turned on. The NMOS transistor has its gate terminal connected to the drain terminal of the two pull-up PMOS transistors, the source terminal connected to the ground, and the drain terminal connected to the node, thereby turning on the transistor of the two pull-up PMOS transistors And provides the discharge path of the node.

The scope of the present invention is also applied to a static RAM having the control signal generating circuit described above.

The method of the present invention is directed to a method of generating a control signal for static random access memory (SRAM). A control signal generating method of the present invention includes: a first step of starting a write operation by operating one of a plurality of word lines of the RAM; A second step of operating the data line and the data line bar to drop the voltage of one bit line selected from the first bit line pairs disposed in the first tracking cell column to ground when the data is used in the data line and the data line bar; A third step of generating a tracking signal when the voltage becomes lower than a preset reference voltage; And a fourth step of terminating the write operation by providing a row decoder with a control signal for terminating the operation of the word line being operated using the tracking signal.

The static-RAM control-signal generating circuit according to the present invention uses the cell column selected from the original cell array of the RAM as it is. Therefore, it is not necessary to have a separate duplicate or dummy word line.

Since the voltage variation of the bit line due to the cell being accessed is used when a specific word line is asserted, the variation according to the position of the cell can be recognized as it is, so that the sense amplifier enable signal has little influence on the processor-voltage-temperature fluctuation.

The control signal generation circuit of the present invention can use a plurality of cell columns, thereby freely adjusting the generation timing of the sense amplifier enable signal.

FIG. 1 is a cross-sectional view of the prior art shown in FIGS. 1 and 2 of Korean Patent Publication No. 2310-0127276,
2 is a conceptual diagram of a static random access memory (SRAM) having a control signal generating circuit according to the present invention,
3 is a circuit diagram of a light tracking unit according to an embodiment of the present invention,
4 is a circuit diagram of a tracking signal generating unit according to an embodiment of the present invention,
5 is a timing diagram provided in an operation description of the generator circuit of FIG. 2,
6 is a circuit diagram of a tracking signal generating unit according to another embodiment of the present invention, and
7 is a conceptual diagram of a static RAM having a control signal generation circuit according to another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the drawings.

2, the static RAM 200 of the present invention includes a cell array 10, a row decoder 20, a column decoder 30, a sense amplifier 30, (Sense Amp) 50, and a write driver (70). The static RAM 200 of the present invention operates in the same manner as a normal static RAM.

In addition, the static RAM 200 of the present invention includes a control signal generation circuit to perform timing control related to a write operation. The control signal generation circuit may be configured so that the actual memory cell that is operated by the original word line is used as the control signal generation circuit without using a separate dummy word line or replica word line as the tracking for generating the sense amplifier enable signal To generate a control signal by tracking the voltage variation in the bit line (or bit line bar). To this end, the control signal generating circuit may comprise at least one tracking cell column and at least one bit line pair arranged in at least one tracking cell column.

Hereinafter, when the cell array 10 has an m x n matrix structure, at least one tracking cell column included in the control signal generation circuit is expressed as selected from n cell columns, but m x n May be a cell column that is not included in the cell array of FIG.

2, the control signal generating circuit includes a first tracking cell column 210 and a first bit line pair BL-T1, a second tracking cell column 210 disposed in the first tracking cell column 210, BLB-T1. In addition, the control signal generation circuit includes a precharger 230, a tracking signal generator 250, a write tracking 270, and a control signal generator 290.

The first tracking cell column 210 is selected from the cell array 10 of the static RAM 200 and tracks the variation in operation of the static RAM 200. Since the first tracking cell column 210 is generated at the same time in the same process as the production of the other cell columns of the manufacturing normal cell array 10, when the cell array 10 has an m × n matrix structure 1 tracking cell column 210 includes m tracking cells including tracking cells 210a through 210m.

Each of the tracking cells 210a to 210m of the first tracking cell column 210 is accessed and operated by the original word lines WL0 to WLm for the cell array 10 so that the tracking cells used for tracking 210k belong to the same row as the cell 11k in which the current write operation is performed, so that tracking of the cell 11k is more practical. For example, the distance between the tracking cell 210k and the tracking signal generator 250 and the distance between the actually operating cell 11k and the light driver 70 are substantially the same, Effectively.

The first bit line pairs BL-T1 and BLB-T1 arranged in the first tracking cell column 210 are not connected to the column decoder 30. [ And is connected to the tracking signal generator 250 via the precharger 230.

However, only one 'selected bit line' among the first bit line pairs (BL-T1 and BLB-T1) of the first tracking cell column 210 is a tracking signal generating And it may be any bit line of the first bit line pair BL-T1, BLB-T1. Accordingly, the remaining one that does not participate in the tracking of the tracking signal generator 250 is always driven to the logic high state. FIG. 2 shows an example in which the first bit line BL-T1 is connected to the tracking signal generator 250. FIG.

The precharger 230 precharges the first bit line pair BL-T1 and BLB-T1 according to the initialization signal. However, the 'selected bit line' among the first bit line pairs BL-T1 and BLB-T1 is precharged in conjunction with the initialization signal, but the remaining one bit line is always kept at a logic high. For example, as shown in FIG. 2, when the first bit line BL-T1 is selected, the first bit line bar BLB-T1 is always driven to logic high without being interlocked with the initialization signal.

Here, the initialization signal may be a so-called equalization signal (BLEQ) or the like. The first bit line BL-T1 is precharged in the same manner as the normal cell column 11 of the cell array 10 is precharged by using the equalization signal BLEQ.

2, the precharger 230 includes a first inverter 231 for inverting the equalization signal BLEQ, a PMOS transistor 233 connected to the first bit line BL-T1, And a PMOS transistor 235 connected to the bar BLB-T1. The output of the first inverter 231 is connected to the gate of the PMOS transistor 233 and the power source voltage Vdd is applied to the source terminal and the first bit line BL- Is coupled such that the first bit line BL-T1 is precharged to logic high only when the equalization signal BLEQ is a logic high. The power source voltage Vss (Vss << Vdd, Vss is generally ground) is connected to the gate of the PMOS transistor 235, the power source voltage Vdd is applied to the source terminal, the first bit line bar (BLB-T1) So that the first bit line bar BLB-T1 is always precharged to a logic high.

The light tracking unit 270 is connected to the node a and drops the voltage of the node a to the ground when data is written to the data line DL and the data line bar DLB during a write operation. This operation reproduces the voltage fluctuation in the bit line BL-i or the bit line bar BLB-i during the write operation to the general cells 11a, 11k and 11m.

3, the light tracking unit 270 includes two pull-up PMOS transistors 301 and 303 and two NMOS transistors 305 and 307. [ The PMOS transistors 301 and 303 receive a data line DL and a data line bar DLB at their respective gate terminals and perform a switching operation. The drain terminals of the PMOS transistors 301 and 303 are commonly connected to the gate of the NMOS transistor 305 do. The source terminal of the NMOS transistor 305 is connected to the power supply voltage Vss and the drain terminal is connected to the node a to provide a discharge path for the node a. The drain terminal of the NMOS transistor 307 is connected to the drain terminal of the PMOS transistors 301 and 303 and the gate terminal thereof is switched to receive the equalization signal BLEQ while the source terminal thereof is connected to the power source voltage Vss.

During a write operation, when data is written to the data line DL and the data line bar DLB, one of the data line DL and the data line bar DLB is written with a logic high value and the other with a logic low value. Thus, one of the two pull-up PMOS transistors 301 and 303 is turned on to provide a logic high value of the NMOS transistor 305 so that the NMOS transistor 305 is turned on and the discharge path for the node a to provide.

At this time, the NMOS transistor 307 maintains the turn-off state because the equalizing signal BLEQ becomes a logic low during a write operation. When the write operation is terminated and the equalization signal BLEQ becomes logic high, the NMOS transistor 307 is turned on again to turn off the NMOS transistor 305, thereby blocking the discharge path for the node a.

The tracking signal generator 250 is connected to the 'selected bit line' via the node a, and the word line is operated during the write operation and the data is driven in the data line DL and the data line bar DLB Lt; RTI ID = 0.0 &gt; (a). &Lt; / RTI &gt;

In the example of FIG. 2, the tracking signal generator 250 is connected to the first bit line BL-T1 through the node a, and supplies the data line DL and the data line bar DLB with data (A) connected to the precharged first bit line (BL-T1) when the first bit line (BL-T1) is driven.

Specifically, when data is driven on the data line DL and the data line bar DLB, the voltage of the first bit line BL-T1 falls to the ground by the write tracking unit 270, The unit 250 generates the tracking signal TRKBL when the voltage of the first bit line BL-T1 falls to a predetermined reference voltage. Here, the reference voltage may be implemented using a threshold voltage of a conventional PMOS or NMOS transistor. In the writing process, the timing of generating the tracking signal TRKBL is set to a voltage difference target value of the bit line pairs BL-T1 and BLB-T1 It is desirable to design it to be a point of time when it arrives.

The tracking signal generator 250 provides the generated tracking signal TRKBL to the control signal generator 270.

FIG. 4 shows the structure of a basic tracking signal generator 250. Referring to FIG. 4, the tracking signal generator 250 includes a pull-up PMOS transistor 401. The selected bit line, that is, the first bit line BL-T1 is connected to the gate of the pull-up PMOS transistor 401 through the node a, and the drain terminal outputs the primary tracking signal TRKBL_N. At this time, the reference voltage tracked by the tracking signal generator 250 becomes the threshold voltage of the PMOS transistor 401. For example, when the voltage difference target value of the bit line is 300V, the threshold voltage of the PMOS transistor 401 is preferably Vdd-300V.

The tracking signal generator 250 may include a second inverter 403 and an NMOS transistor 405a to drive the primary tracking signal TRKBL_N. NPOS transistor 405a is controlled by an initialization signal (e.g., BLEQ) input to the gate terminal. The second inverter 403 inverts the primary tracking signal TRKBL_N to finally output the tracking signal TRKBL.

The control signal generator 290 generates a control signal related to timing control of the write operation using the tracking signal TRKBL. During the write operation, the control signal generator 290 uses the tracking signal TRKBL to control the row decoder 20 to terminate the write operation, which terminates the operation of the word line being operated. The row decoder 20 determines the width of the word line pulse according to a control signal, that is, the word line is again brought to a logic low level, thereby ending the write operation.

<Write Operation of Control Signal Generation Circuit: FIG. 5>

Hereinafter, the operation of the control signal generation circuit will be described focusing on the operation of the tracking signal generation unit 250 in the write operation with reference to FIG. The operation of FIG. 5 will be described mainly on the writing process of the general cell 11k including the cell array 10. FIG.

The bit line BL-i and the bit line bar BLB-i of the general cell 11k are precharged by the equalizing signal BLEQ in the logic high state as in the normal write operation. The first bit line pairs BL-T1 and BLB-T1 are also precharged to a logical high by the precharger 230. However, the first bit line BLB-T1 that is not connected to the node a always maintains the logic high state, and the first bit line BL-T1 returns to the logic high level of the equalizing signal BLEQ Is pre-charged.

Immediately after the equalization signal BLEQ becomes a logical low in the logic high state, the word line WLk operates and the column decoder 30 outputs the data line DL and data And connects the line bar DLB to the bit line BL-i and the bit line bar BLB-i. The write driver 50 writes a value corresponding to the data to be written in the cell 11k into the data line DL and the data line bar DLB. The data on the bit line to which the logical row is assigned falls from the values of the data line DL and the data line bar DLB to the ground and the corresponding data is written to the cell 11k. For example, if the data to be written in the cell 11k is '1', the data line DL becomes logic high and the data line bar DLB becomes logic low. Therefore, while the bit line BL-i maintains the logic high, the voltage '1' is written to the cell 11k as the voltage of the bit line bar BLB-i falls to the ground.

Thereafter, the word line WLk falls back to a logic low, and the write operation is completed. Therefore, since the word line WLk has to be a logic low after the voltage of the bit line BL-i or the bit line bar BLB-i has fallen to the ground, the time point at which the word line WLk becomes a logic low The determination of the width of the line pulse) is related to the timing control of the write operation.

On the other hand, when one of the data line DL and the data line bar DL falls to ground, one of the PMOS transistors 301 and 303 of the light tracking unit 270 is turned on and then the NMOS transistor 305 is turned on. The voltage of the first bit line BL-T1, that is, the voltage of the node a, also begins to drop to the ground. At this time, the NMOS transistor 307 remains turned off by the equalization signal BLEQ.

The PMOS transistor 401 of the tracking signal generator 250 starts to turn on according to the voltage of the first bit line BL-T1, and the voltage of the first bit line BL- And generates a first tracking signal TRKBL_N which is a logic high when the threshold voltage is completely turned on and a second inverter 403 inverts the first tracking signal TRKBL_N to generate a logic low tracking signal TRKBL . Therefore, the tracking signal TRKBL is generated before the voltage of the first bit line BL-T1 falls to the ground.

Thereafter, the control signal generator 290 generates a control signal in accordance with the tracking signal TRKBL and provides the control signal to the row decoder 20 so as to turn off the word line pulse (Word Line Pulse).

Considering that it is difficult to actually adjust the reference voltage with the threshold voltage of the PMOS transistor 401, the tracking reference voltage of the tracking signal generator 250 can be adjusted as shown in FIG. 6 below.

&Lt; Other Embodiments of the Tracking Signal Generation Unit: Fig. 6 &

6, in addition to the pull-up PMOS transistor 401 and the second inverter 403, the tracking signal generator 250 may include at least one of a pull-up PMOS transistor 401 and a second inverter 403 disposed between a drain terminal of the PMOS transistor 401 and a ground. Down NPOS transistor 405 to adjust the logic threshold voltage of the tracking signal generator 250. [

6 shows an example having two cascade-connected NMOS transistors 405a and 405b. NPOS transistors 405a and 405b are controlled by an initialization signal (for example, BLEQ) input to the gate terminal. During the write operation, the pull-down NPOS transistors 405a and 405b are turned off to increase the logic threshold voltage so that the time point when the PMOS transistor 401 is turned on is advanced. Thus, even if the voltage drop rate at the first bit line BL-T1 is the same, the PMOS transistor 401 is turned on earlier and the primary tracking signal TRKBL_N and the tracking signal TRKBL are also generated sooner .

According to an embodiment, PMOS transistors 407 and 409 may be further included between the input of the second inverter 403 and the power supply voltage Vdd. The PMOS transistor 407 is controlled by the equalization signal BLEQ connected to the gate terminal, and the PMOS transistor 409 controls the tracking signal TRKBL by feeding back the signal to the gate terminal. The PMOS transistors 407 and 409 accelerate the time point at which the tracking signal TRKBL is generated.

&Lt; Method of using a plurality of tracking cell columns: Fig. 7 &

As described above, the control signal generation circuit of the present invention can use a plurality of tracking cell columns. In this case, the voltage drop rate at the node (a) becomes faster, and the timing at which the tracking signal TRKBL is generated is advanced.

7, a static RAM 700 includes a first tracking cell column 210 and a second tracking cell column 211 in addition to the first tracking cell column 210.

Similarly to the first tracking cell column 210, the second tracking cell column 211 is also selected from the cell array 10 of the static RAM 700, and a variation portion of the operation of the static RAM 700 Track. Since the second tracking cell column 211 is generated at the same time in the same process as the other cell columns of the manufacturing normal cell array 10 at the same time, when the cell array 10 has an m × n matrix structure 2 tracking cell column 211 includes m tracking cells including tracking cells 211a through 211m. Each of the tracking cells 211a to 211m of the second tracking cell column 211 is also accessed and operated by the original word lines WL0 to WLm for the cell array 10. [ And the second bit line pair BL-T2 and BLB-T2 are arranged in the second tracking cell column 211.

A selected one of the second bit line pairs BL-T2 and BLB-T2 is connected to the node a and is connected to the tracking signal generating unit 250 to contribute to generation of the tracking signal TRKBL. However, if the first bit line BL-T1 is connected to the node a in the first tracking cell column 210, the second bit line BL-T2 of the second tracking cell column 211 is connected to the node a and if the first bit line bar BLB-T1 in the first tracking cell column 210 is connected to the node a, then in the second tracking cell column 211, It is preferable for the operation control that the bar BLB-T2 is connected to the node a.

2, the PMOS transistor 401 of the tracking signal generator 250 is also turned on earlier and the primary tracking signal TRKBL_N is turned on earlier than the voltage at the node a, And the tracking signal TRKBL are generated more quickly.

According to the embodiment, the control signal generation circuit includes pass gate circuit portions 601 and 603 for interrupting the bit lines (bit line bars in accordance with the embodiment) individually connected to the node a, As shown in FIG. The pass gate circuit portions 601 and 603 are controlled by separate control signals Opt 1 and Opt 2. For example, in FIG. 7, when the connection between the second bit line BL-T2 and the node a is cut off by the control signal Opt 2, the second bit line bar BLB- (Flotting) state, and the circuit of Fig. 7 operates in the same manner as the circuit of Fig.

The pass gate circuit units 601 and 603 applied when using a plurality of tracking cell columns can advance or delay the timing of generating the sense amplifier enable signal by controlling the number of tracking cell columns connected to the node a . Alternatively, some tracer cell columns may be reserved, in case some tracer cell columns are defective.

On the other hand, the tracking signal generator 250 tracks the voltage fluctuation at the precharged node a when one of the word lines WL0 to WLm is operated for a read operation, and outputs the sensor amplifier enable (SAE) signal Can contribute to generation.

The tracking cells of the first tracking cell column 210 must first be written with data to provide a discharge path for the 'selected bit line' during a read operation. For example, when the first bit line BL-T1 contributes to the generation of the tracking signal, since the tracking signal generator 250 tracks the voltage variation in the first bit line BL-T1, Each of the tracking cells 210a through 210m of the column 210 must have a logic '0' value before entering a read operation. Conversely, when the first bit line bar BLB-T1 contributes to the generation of the tracking signal, since the tracking signal generator 250 tracks the voltage variation in the first bit line bar BLB-T1, Each of the tracking cells 210a through 210m of the column 210 must have a logical '1' value before entering a read operation.

In the case of the present invention, the data of the tracking cells 210a to 210m are written at necessary values during the write operation in the write tracking unit 270. [ In the example of FIG. 2, data '0' is written in the tracking cells 210a to 210m as the voltage of the first bit line (BL-T1) drops to ground during a write operation.

When the word line WLk operates according to the read control, the first bit line BL-T1 is connected to the tracking cell 210k and the first bit line BL- BL-T1, that is, a voltage drop occurs at the node a. The tracking signal generator 250 generates the tracking signal TRKBL when the voltage of the node a falls to a preset reference voltage.

It is preferable that the reference voltage here is designed so that the time point at which the tracking signal TRKBL is generated during the read operation is the time point at which the voltage difference of the data line reaches the target value (Target Delta DL in FIG. 8), and the threshold voltage of the PMOS or NMOS transistor As shown in FIG.

Accordingly, the control signal generator 270 can generate the sensor amplifier enable signal SAE that drives the sensor amplifier 50 using the tracking signal TRKBL during the read operation .

<Read Operation of Control Signal Generation Circuit: FIG. 8>

Hereinafter, a process of generating the sensor amplifier enable signal SAE based on the operation of the tracking signal generator 250 in the read operation will be described with reference to FIG.

The bit line BL-i and the bit line bar BLB-i of the general cell 11k are precharged by the equalizing signal BLEQ in the logic high state as in the normal reading operation. The first bit line pairs BL-T1 and BLB-T1 are also precharged to a logical high by the precharger 230. However, the first bit line BLB-T1 always maintains a logic high state, and the first bit line BL-T1 is precharged as the equalization signal BLEQ returns to logic high.

To start the read operation, the word line WLk is operated immediately after the equalization signal BLEQ becomes logic low at the logic high state, and the bit line BL-i and the bit line bar BLB-i are connected to the cell And a voltage difference is generated between the bit line BL-i and the bit line BLB-i, as shown in FIG. 8, The voltage difference also occurs in the line DL and the data line bar DLB. It is most preferable if the sensor amplifier enable signal is activated and the sensor amplifier 50 is sensed when the voltage difference target value (Target Delta DL) of the data line is reached.

When the word line WLk is operated, the first bit line BL-T1 of the first tracking cell column 210 is also connected to the tracking cell 210k, and the first bit line BL- The voltage begins to drop as the voltage is distributed to the tracking cell 210k. The PMOS transistor 401 of the tracking signal generator 250 starts to turn on according to the voltage of the first bit line BL-T1, and the voltage of the first bit line BL- And generates a first tracking signal TRKBL_N which is a logic high when the threshold voltage is completely turned on and a second inverter 403 inverts the first tracking signal TRKBL_N to generate a logic low tracking signal TRKBL . At this time, the timing at which the tracking signal TRKBL is generated is determined by the threshold voltage of the PMOS transistor 401 of FIG. 4 or the logic threshold voltage of the tracking signal generator 250 of FIG. As shown in FIG. 7, the generation timing of the tracking signal TRKBL may be adjusted by increasing the rate at which the voltage of the node a falls using a plurality of tracking cell columns.

Thereafter, the control signal generator 290 generates a sensor amplifier enable signal (SAE) to the sensor amplifier 50 so that the sensor amplifier 50 outputs the data signal to the data line DL and the data line DLB Detect the voltage difference (Delta DL). The word line pulse (Word Line Pulse) can also be converted to a logic low according to the tracking signal TRKBL.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention as defined by the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

Claims (8)

1. A control signal generation circuit for a static random access memory (SRAM) having an m × n structure cell array,
One bit line selected from a first bit line pair disposed in a first tracking cell column included in the cell array;
A precharger for precharging a voltage of a common node connected to the selected bit line to a logic high in association with an initialization signal;
And a control circuit for controlling the voltage of the common node by receiving data from the data line and the data line of the static RAM, wherein one of the plurality of word lines of the static RAM is operated, A write tracking unit operative when the data is used in the bar and dropping the voltage of the precharged common node to the ground;
A tracking signal generator for generating a tracking signal when the voltage of the common node drops below a predetermined reference voltage while falling to ground; And
And a control signal generation unit for terminating a write operation by providing a row decoder with a control signal for terminating the operation of the word line being operated using the tracking signal.
The method according to claim 1,
Further comprising a bit line selected from among other bit line pairs disposed in the other trace cell columns and connected to the common node.
3. The method of claim 2,
Further comprising a pass gate circuit portion for interrupting the connection between the selected bit lines of the bit line pair and the common node separately from the first bit line pair.
The method according to claim 1,
Wherein the tracking signal generator comprises:
Wherein the reference voltage is a logic threshold voltage.
5. The method of claim 4,
Wherein the tracking signal generator comprises:
A pull-up PMOS transistor having the gate node connected to the common node and turned on at the reference voltage; And
And an inverter for inverting the output of the drain terminal of the PMOS transistor and outputting the tracking signal.
The method according to claim 1,
The light-
Two PMOS transistors that receive the data line and the data line bar respectively through a gate terminal and turn on when the data line and the data line bar are driven; And
The gate terminal is connected to the drain terminal of the two pull-up PMOS transistors, the source terminal is connected to the ground, and the drain terminal is connected to the common node. The gate terminal is turned on by the transistor of the two pull-up PMOS transistors, And an NMOS transistor for providing a discharge path.
A control signal generating method for a static RAM (SRAM) having an mxn cell array,
The method comprising: a first step of activating one of a plurality of word lines of the RAM to start a write operation;
A second step of dropping a voltage of one bit line selected from a first bit line pair disposed in a first tracking cell column included in the cell array to ground when data is written to the data line and the data line bar of the RAM;
A third step of generating a tracking signal at a time point when the voltage of the selected bit line falls below a predetermined reference voltage while falling to ground; And
And terminating the write operation by providing a row decoder with a control signal for terminating the operation of the word line being operated using the tracking signal.
A static RAM having an m × n structure cell array controlled by a plurality of word lines,
And a control signal generation circuit,
The control signal generation circuit includes:
One bit line selected from a first bit line pair disposed in a first tracking cell column included in the cell array;
A precharger for precharging a voltage of a common node connected to the selected bit line to a logic high in association with an initialization signal;
Wherein when the data is written to the data line and the data line bar during a write operation while one of the plurality of word lines is operated while receiving data from the data line and the data line of the static RAM and controlling the voltage of the common node, A write tracking unit for dropping the common node voltage to ground;
A tracking signal generator for generating a tracking signal when the voltage of the common node drops below a predetermined reference voltage while falling to ground; And
And a control signal generation unit for terminating the write operation by providing a row decoder with a control signal for terminating the operation of the word line being operated using the tracking signal.

Images