JP2004253135A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the capacitive coupling noise between the neighboring bit lines. <P>SOLUTION: This nonvolatile semiconductor memory device has charging transistors (Q02, Q12 ...) to supply the prescribed voltage to the bit lines for reading the data, and discharging transistors (Q01, Q11...) to ground the bit lines not selected when reading. These transistors are controlled by the control signals respectively obtained by detecting the address transitions on every other bit lines for the inputted addresses, and the discharging transistors are maintained conductive to ground the bit lines not selected during the period from before reading the data and through reading the data. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a rewritable nonvolatile semiconductor memory device.

  As a rewritable nonvolatile semiconductor memory device, an electrically rewritable EEPROM has been conventionally known. Above all, a NAND cell type EEPROM in which a plurality of memory cells are connected in series to form a NAND cell block has been attracting attention as being capable of high integration. One memory cell of a NAND cell type EEPROM has an FETMOS structure in which a floating gate and a control gate are stacked on a semiconductor substrate via an insulating film, and a plurality of memory cells adjacent to each other have a source and a drain. The cells are connected in series in a shared manner to form a NAND cell. Such NAND cells are arranged in a matrix to form a memory cell array. The drains on one end side of the NAND cells arranged in the column direction of the memory cell array are commonly connected to a bit line via a selection gate transistor, and the source on the other end is also connected to a common source line via a selection gate transistor. . The control gate of the memory transistor and the gate electrode of the select gate transistor are commonly connected as a control gate line (word line) and a select gate line in the row direction of the memory cell array, respectively.

  The operation of this NAND cell type EEPROM is as follows.

  Data writing is performed sequentially from the memory cell farthest from the bit line. Explaining the case of n-channel, a high potential (for example, 20 V) is applied to the control gate of the selected memory cell, and the control gate of the non-selected memory cell and the gate of the select gate transistor on the bit line side Is applied with an intermediate potential (for example, 10 V). 0 V (for example, “1”) or an intermediate potential (for example, “0”) is applied to the bit line according to data. At this time, the potential of the bit line is transmitted to the drain of the selected memory cell through the selected gate transistor and the unselected memory cell.

  When there is data to be written (when data is "1"), a high electric field is applied between the gate and drain of the selected memory cell, and electrons are tunnel-injected from the substrate to the floating gate. As a result, the threshold value of the selected memory cell moves in the positive direction. When there is no data to be written (when data is "0"), there is no change in the threshold value.

  To erase data, a high potential is applied to the p-type substrate (n-type substrate and p-type well formed in the case of a well structure), and the control gates of all the memory cells and the gates of the select gate transistors are set to 0V. You. Thereby, in all the memory cells, the electrons of the floating gate are emitted to the substrate, and the threshold value moves in the negative direction.

  In data reading, the selected gate transistor and unselected memory cells are turned on, and 0 V is applied to the gate of the selected memory cell. At this time, by reading the current flowing through the bit line, "0" or "1" is determined.

  In such a conventional NAND cell type EEPROM, data reading or writing is usually performed simultaneously for all bit lines. For this reason, capacitive coupling noise between adjacent bit lines is a problem in highly integrated EEPROMs.

  For example, in the case of a 4 Mbit NAND cell type EEPROM, a bit line formed of an Al film has a line width of 1 μm and a line interval of 1.2 μm. As a result, of the bit line capacitance of approximately 0.5 pF, approximately 50% of 0.25 pF is the capacitance between adjacent bit lines.

  Therefore, for example, when a bit line is precharged to Vcc = 5V and then put into a floating state, and when data is simultaneously read out to all the bit lines, the bit line trying to maintain 5V is discharged from both sides by the bit line trying to discharge from 5V to 0V. When the bit line is sandwiched, the bit line that tries to maintain 5 V is lowered to about (1/2) Vcc = 2.5 V by capacitive coupling. Therefore, there is no margin with respect to the circuit threshold value of the sense amplifier for determining “0” or “1”, which causes a read malfunction.

  The same applies to data writing. As described above, the bit line connected to the memory cell in which data is not written (that is, "0" data is written) is set to the intermediate potential VH and then floats, and the bit line connected to the memory cell to which "1" data is to be written is set. 0 V is applied to the connected bit line. Therefore, when a non-selected bit line to which writing is not performed is sandwiched by a bit line to which "1" data is to be written, the intermediate potential of the non-selected bit line to be held at the intermediate potential is reduced by capacitive coupling. This causes erroneous writing to a memory cell connected to an unselected bit line. Even if erroneous writing does not occur, the threshold value of the memory cell changes and reliability is reduced.

  The coupling capacitance noise between the bit lines as described above is not limited to the NAND cell type EEPROM, but also occurs in the NOR type EEPROM and also in the ultraviolet erasing type EPROM. In addition, the problem becomes greater as the degree of integration increases.

  As described above, in conventional EEPROMs, EPROMs, and the like, the coupling capacitance noise between bit lines has become a significant problem in characteristics as the degree of integration increases.

  An object of the present invention is to provide a nonvolatile semiconductor memory device in which the influence of the coupling capacitance between bit lines is reduced.

  In order to solve the above problems, the present invention employs the following configuration.

  That is, the nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of bit lines, a plurality of word lines arranged to intersect these bit lines, and each of the bit lines and the word lines. A rewritable nonvolatile semiconductor memory cell which is arranged at an intersection and is driven by a word line to exchange data with a bit line; and a rewritable nonvolatile semiconductor memory cell provided for every one or two bit lines. A sense amplifier for detecting data of a memory cell selected by a line, a read charge transistor connected to the bit line, for applying a predetermined read potential to the bit line for data read, and a non-selected bit line for reading. Precharge means having a read discharge transistor for bringing the potential to the ground potential, wherein the read charge transistor and the read discharge transistor Every other bit line corresponding to the address input at the start is controlled by a different control signal obtained by detecting the address, so that either one of the odd-numbered bit line and the even-numbered bit line is completely turned off. The selected bit line, any one of which is a non-selected bit line, the non-selected bit line is held at the ground potential, the selected bit line is in a floating state after precharging, connected to the sense amplifier, and selected. The data of all the memory cells arranged at the respective intersections of the word line and the selected bit line are simultaneously read out to the sense amplifier.

  In addition, a nonvolatile semiconductor memory device according to another aspect of the present invention includes a plurality of bit lines, a plurality of word lines provided to intersect these bit lines, A rewritable nonvolatile semiconductor memory cell arranged at each intersection position and driven by a word line to exchange data with a bit line, and a rewritable nonvolatile semiconductor memory cell provided for every two bit lines and provided by the word line. A sense amplifier for detecting data of a selected memory cell; a sense amplifier connected to the bit line for applying a predetermined read potential to a selected bit line for data read and holding a non-selected bit line at a predetermined fixed potential Precharge means, and among the memory cells arranged at each intersection of one word line and the plurality of bit lines, each intersection of all odd-numbered bit lines with the word line. The data of the first memory cell group arranged at the same position and the data of the second memory cell group arranged at each intersection of all the even-numbered bit lines and the word lines are simultaneously read out to the sense amplifier. It is characterized by the following.

In addition, a nonvolatile semiconductor memory device according to another aspect of the present invention includes a plurality of bit lines, a plurality of word lines provided to intersect these bit lines, A rewritable nonvolatile semiconductor memory cell arranged at each intersection position and driven by a word line to exchange data with a bit line; and a rewritable nonvolatile semiconductor memory cell provided for each one or two bit lines. A sense amplifier for detecting data of a memory cell selected by a word line;
A precharge means connected to the bit line for applying a predetermined read potential to a selected bit line for data read and holding an unselected bit line at a predetermined fixed potential; And a first memory cell group arranged at each intersection between the word line and all of the odd-numbered bit lines selected by the address among the memory cells arranged at each intersection with the bit line and Data of any one of the second memory cell group arranged at each intersection of the even-numbered bit line selected by the address and the word line is simultaneously read out to the sense amplifier. .

  According to the present invention, the effect of capacitive coupling noise between adjacent bit lines during data reading or writing can be significantly reduced, and a highly reliable nonvolatile semiconductor memory device can be obtained.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(1st Embodiment)
1 and 2 show the configuration of a core circuit section of an EEPROM according to an embodiment of the present invention.

  A plurality of bit lines BL (BL0, BL1,..., BLn) and a plurality of word lines WL (WL0, WL1,..., WLm) are arranged to cross each other, and a memory cell MCij ( i = 0,1, .about., m, j = 0,1, .about., n) are arranged to form a memory cell array. The memory cell MCij is, for example, an FETMOS-type electrically rewritable nonvolatile semiconductor memory cell in which a floating gate and a control gate are stacked, and the control gate is connected to a word line WL and the drain is connected to a bit line BL. It is connected.

  At one end of each bit line BL, a flip-flop type sense amplifier S / A (S / A0, S / A1,..., S / An) for reading and writing data is provided. The node of the sense amplifier S / A is connected to data input / output lines I / O and I / OB via transfer gates controlled by column selection signals CSL (CSL0, CSL1,..., CSLn). The data input / output lines I / O and I / OB are connected to an external data input / output terminal via a data input buffer and a data output buffer.

  Each bit line BL is a charge transistor for reading Q02, Q22,..., Q12, Q32,... Which is a PMOS transistor, and an NMOS transistor as means for precharging the bit line BL to a predetermined potential for data reading. , Q11, Q31,... Are provided.

  The charge transistors for reading Q02, Q22,..., Q12, Q32,... Are for applying a read potential VR (for example, an external power supply potential) to the bit line BL in advance, and the even-numbered bit lines BL1, BL3 among them are provided. Are simultaneously controlled by the control signal PREA, and the transistors Q02, Q22,... Provided on the odd-numbered bit lines BL0, BL2,... Are simultaneously controlled by another control signal PREB. It is supposed to be. The control signals PREA and PREB are obtained by detecting a transition of the input address. The control signals PREA and PREB change the potential of the bit line BL according to whether the address selects an odd-numbered or even-numbered bit line BL. This is a control signal.

  The read discharge transistors Q01, Q21,..., Q11, Q31,... Are used to set the unselected bit lines to the ground potential in advance, and these transistors are also provided for the even-numbered bit lines BL1, BL3,. Are controlled simultaneously by a control signal SETA, and transistors Q01, Q21,... Provided on odd-numbered bit lines BL0, BL2,... Are simultaneously controlled by another control signal SETA. Has become. These control signals SETA and SETB are also signals for controlling the potential of the bit line BL according to whether the address selects an odd-numbered or even-numbered bit line BL.

  The bit line potential control circuit for writing data is not shown in FIGS. This part will be described later.

  The data read operation of the EEPROM having the above-described structure will be described below.

  FIGS. 3 and 4 are the first half and the second half of a timing chart showing a read cycle. Of these, FIG. 3 in the first half shows a state in which odd-numbered bit lines are selected, and FIG. 4 in the second half shows a state in which even-numbered bit lines are selected.

  In the initial state, the control signals PREA and PREB are both at the "H" level of Vcc, so that the read charge transistors Q02, Q22,..., Q12, Q32,. The control signals SETA and SETB are both at Vcc, so that the read discharge transistors Q01, Q21,..., Q11, Q31,... Are all on, and all the bit lines BL are at the source power supply potential Vss (normal ground potential). Is set to

  The chip enable / CE changes from “H” level to “L” level, and a row address and a column address are fetched from outside the chip. Inside the chip, an address transition detection circuit operates to generate a row address transition detection pulse and a column address transition detection pulse.

  When the odd-numbered bit line is selected by the fetched row address by operating the address transition detection circuit in this manner, among the control signals SETA and SETB, SETA changes from Vcc to Vss, thereby setting the odd-numbered bit line. The read discharge transistors Q01, Q21,... Provided for the bit lines BL0, BL2,. At the same time, of the control signals PREA and PREB, PREA becomes Vss, whereby the read charge transistors Q12, Q32,... Provided on the odd-numbered bit lines BL0, BL2,. The bit lines BL0, BL2,... Are precharged to the read potential VR. The even-numbered bit lines BL1, BL3,... Are kept at Vss because the discharging transistors Q11, Q31,.

  After the odd-numbered bit lines BL0, BL2,... Are precharged to the read potential VR, when the word line WL0 selected by the row address changes from Vss to Vcc, the odd-numbered bit lines BL0, BL2,. Data is read only from the memory cells MC00, MC02,..., MC0n-1 along the connected word line WL0. The data of the memory cells MC01, MC03,..., MC0n connected to the even-numbered unselected bit lines BL1, BL3,..., Driven by the same word line WL0 are set such that the unselected bit lines BL1, BL3,. It is not read because it is fixed. This is because the memory cell is a non-destructive read type nonvolatile semiconductor memory unlike a DRAM or the like.

  The data read to the odd-numbered bit lines BL0, BL2,... Are detected by the sense amplifiers S / A0, S / A2,. When one of the column selection signals CSL0 selected by the column address becomes "H" level, the data latched in the sense amplifier S / A0 is output to the output buffer via the input / output lines I / O and I / OB. Output to the outside via When the column address changes and the column address transition detection circuit detects this, and the next column selection line CSL2 goes to "H" level, the data latched by the sense amplifier S / A2 is output. Hereinafter, similarly, the column continuous reading for the odd-numbered bit lines is performed. This is shown in FIG.

  When the row address further changes, the row address transition detection circuit detects this, and generates an address transition detection pulse. Then, the process is performed again from the selection of the even-numbered bit line or the odd-numbered bit line. FIG. 4 shows a case where even-numbered bit lines are selected. At this time, odd-numbered bit lines BL0, BL2,... Are fixed to Vss, and data of the memory cells of even-numbered bit lines BL1, BL3,. FIG. 4 shows a case where the word line WL0 is also selected at this time. At this time, the data of the memory cells MC01, MC03,... Is read to the even-numbered bit lines BL1, BL3,. When the column selection signal CSL1 goes to "H" level, the data of the sense amplifier S / A1 is output. Then, when the row address changes and the column selection signal CSL3 goes to "H" level, the sense The data of the amplifier S / A3 is output. Similarly, in this case as well, continuous column reading is performed for even-numbered bit lines.

  As described above, in this embodiment, when the even-numbered bit line is selected according to the address, the odd-numbered non-selected bit line is set to Vss before the word line is selectively driven. Similarly, when the odd-numbered bit line is selected, the even-numbered bit line is set to Vss in advance as a non-selected bit line. Therefore, as in the conventional case, when the unselected bit line transitions from the precharge potential Vcc to 0 V during data reading, the precharge potential of the selected bit line sandwiched between the unselected bit lines does not decrease due to capacitive coupling. Malfunction is reliably prevented.

(Second embodiment)
5 and 6 show the configuration of a core circuit section of an EEPROM according to another embodiment of the present invention. In this embodiment, odd-numbered bit lines BL0A, BL1A,..., BLnA and even-numbered bit lines BL0B, BL1B,. , S / A1,..., S / An. The configurations of the memory cells MCijA, MCijB and the cell array are the same as in the previous embodiment. As in the previous embodiment, the read discharge transistors Q01A, Q11A,..., Qn1A and Q01B, Q11B,. , Qn1B.

  The sense amplifier side end of each bit line BL is collectively connected to two sense amplifiers S / A via select gate transistors Q03A, Q13A,..., Qn3A and Q03B, Q13B,. A0, S / A1, ..., S / An. The select gate transistors Q03A, Q13A, ..., Qn3A and Q03B, Q13B, ..., Qn3B are controlled by different control signals SELA, SELB determined by addresses. Read charge transistors Q02, Q12,..., Qn2, which are PMOS transistors, are provided at positions where the bit lines are grouped by two.

  FIG. 7 and FIG. 8 are operation timing charts of the read cycle of the EEPROM of this embodiment.

  In the initial state, the charge transistor control signal PRE is Vcc "H" level, the select gate control signals SELA and SELB are Vss "L" level, and the discharge transistor control signals SETA and SETB are Vcc "H" level. Level, and all the bit lines BL are set to the source power supply potential Vss (normal ground potential) as in the previous embodiment.

  The chip enable / CE changes from “H” level to “L” level, and a row address and a column address are fetched from outside the chip. Inside the chip, an address transition detection circuit operates to generate a row address transition detection pulse and a column address transition detection pulse.

  When the odd-numbered bit line is selected by the fetched row address by operating the address transition detection circuit in this manner, among the control signals SETA and SETB, SETA changes from Vcc to Vss, thereby setting the odd-numbered bit line. The read discharge transistors Q01, Q21,... Provided on the bit lines BL0A, BL1A,. At the same time, the control signal PRE becomes Vss, and among the control signals SELA and SELB of the selection gate, SELA becomes "H" level. .. Provided in the odd-numbered bit lines BL0A, BL1A,... Are turned on, and the odd-numbered bit lines BL0A, BL1A,. The even-numbered bit lines BL0B, BL1B,... Are kept at Vss.

  After the odd-numbered bit lines BL0A, BL1A,... Are precharged to the read potential VR, when the word line WL0 selected by the row address changes from Vss to Vcc, the odd-numbered bit lines BL0A, BL1A,. The data of the memory cells MC00A, MC01A,..., MC0nA along the connected word line WL0 is read. The data of the memory cells MC00B, MC01B,..., MC0nB connected to the even-numbered unselected bit lines BL0B, BL1B,... Driven by the same word line WL0 is not read.

  The data read to the odd-numbered bit lines BL0A, BL1A,... Is detected by the sense amplifiers S / A0, S / A1,. When the column selection signal CSL0 goes to "H" level, the data latched by the sense amplifier S / A0 is output to the outside via the input / output lines I / O and I / OB and the output buffer. . When the column address changes and the column address transition detection circuit detects this and the next column selection line CSL1 goes to "H" level, the data latched by the sense amplifier S / A1 is output. Thereafter, in the same manner as in the previous embodiment, continuous column reading is performed for the odd-numbered bit lines.

  When the row address further changes, the row address transition detection circuit detects this and generates a pulse. Then, the process is performed again from the selection of the even-numbered bit line or the odd-numbered bit line. FIG. 8 shows a case where an even-numbered bit line is selected. At this time, odd-numbered bit lines BL0A, BL1A,... Are fixed at Vss, and data of the memory cells of even-numbered bit lines BL0B, BL1B,. At this time, if WL0 is selected as the selected word line, the data of the memory cells MC00B, MC01B,... Is read to the even-numbered bit lines BL0B, BL1B,. Then, when the column selection signal CSL0 goes to "H" level, the data of the sense amplifier S / A0 is output. Similarly, in this case as well, continuous column reading can be performed on even-numbered bit lines.

(Third embodiment)
FIGS. 9 and 10 show an embodiment in which a circuit necessary for writing data is added to the EEPROM of the embodiment shown in FIGS. In this embodiment, in addition to the embodiments shown in FIGS. 5 and 6, charge transistors Q04A,..., Qn4A and Q04B,. These write transistors Q04A,..., Qn4A and Q04B,. (An intermediate potential between the potentials Vcc). The transistors Q04A,..., Qn4A provided on the odd-numbered bit lines are simultaneously controlled by the control signal WSEA, and the transistors Q04B,. Is controlled by

  The write control signals WSEA and WSEB respectively control the charge transistors Q04A,..., Qn4A and Q04B,..., Qn4B for writing, so that all the bit lines are set at the intermediate potential VH before write data is sent from the sense amplifier to the bit lines. During data writing, the selected bit line (eg, odd-numbered bit line) is kept floating, and the non-selected bit line (eg, even-numbered bit line) is continuously supplied with the intermediate potential VH. .

  FIGS. 11 and 12 show the first half and the second half of the timing chart of the data write cycle of the EEPROM of this embodiment. Using this, a specific write operation will be described.

  The chip enable / CE and the write enable / WE change from “H” level to “L” level, and the write operation is started. First, data is written from the input / output buffer to the sense amplifiers S / A0, S / A1,..., S / An via the input / output lines I / O, I / OB. This is because the column selection signals CSL0, CSL1,... Sequentially become "H" level in accordance with the column address as shown in FIG. 11, and in synchronization with this, serial data is sequentially written to the sense amplifier. . If there are (n + 1) sense amplifiers, this is repeated until data is written to the nth sense amplifier.

  During the data writing to the sense amplifier, both of the write control signals WSEA and WSEB are changed from Vss to VH + α (α is a voltage corresponding to the threshold voltage of the write charge transistors Q04A,..., Qn4A and Q04B,. ), And all the bit lines BL are precharged to the intermediate potential VH.

  Then, after data is written to the last n-th sense amplifier S / An, one of the write control signals WSEA and WSEB becomes Vss according to the row address. FIG. 12 shows a case where data is written to the odd-numbered bit lines BL0A,..., BLnA. In this case, the control signal WSEA becomes Vss. As a result, the write charge transistors Q04A,..., Qn4A of the odd-numbered bit lines BL0A,. Thereby, the odd-numbered bit lines BL0A,..., BLnA are set to Vss (in the case of "1" data) or VH ("", depending on the data previously transmitted to the sense amplifiers S / A0,. 0 "data).

  Thereafter, when the selected word line WL0 changes from Vss to the write potential Vpp, electrons are injected into the floating gate by the memory cell connected to the bit line of the odd-numbered bit lines BL0A,. Is This is data “1” writing. During this time, the even-numbered bit lines BL0B,..., BLnB are all fixed at the intermediate potential VH instead of floating because the charging transistors Q04B,.

  When data is written to even-numbered bit lines BL0B,..., BLnB, unselected odd-numbered bit lines BL0A,..., BLnA are all fixed to the intermediate potential VH during the writing operation.

  Thus, in this embodiment, every other unselected bit line is fixed at the intermediate potential VH during the write operation. Therefore, as in the prior art, it is precharged to the intermediate potential in advance, but becomes floating during the write operation, and the potential of the bit line sandwiched between the bit lines of “1” data write transitioning to Vss is lowered by capacitive coupling. Will not be.

(Fourth embodiment)
Next, an embodiment in which the present invention is applied to a NAND cell type EEPROM will be described.

  13 to 15 show a core circuit portion of the NAND cell type EEPROM according to the embodiment. FIG. 13 shows an end structure on the opposite side to the sense amplifier, FIG. 14 shows a cell array structure, and FIG. 2 shows the configuration of the amplifier side end.

  As shown in FIG. 14, for example, a plurality of FET cells are connected in series (eight in the figure) so that the source and the drain are shared between adjacent FET MOS type memory cells to constitute a NAND cell. The drain end of the NAND cell is connected to the bit line BL via a select gate controlled by select gate lines SGD0, SGD1,. The source ends of the NAND cells are also connected to a common source line via select gates controlled by select gate lines SGS0, SGS1,. The control gates of the memory cells arranged in a direction intersecting with the bit line BL are commonly connected to each other to form a word line WL.

  As shown in FIG. 13, read discharge transistors Q01A, to Qn1A, Q01B, to Qn1B are provided at the end of the bit line opposite to the sense amplifier in the cell array as shown in FIG. Charge transistors Q04A,..., Qn4A, Q04B,.

  As shown in FIG. 15, the bit line ends on the sense amplifier side of the cell array are grouped together by select gate transistors Q03A,..., Qn3A, Q03B,. Are provided with read charge transistors Q02, Qn2.

  Each of the sense amplifiers S / A0,..., S / An is constituted by a flip-flop in which two clocked CMOS inverters are combined as shown in FIG.

  16 to 19 are timing charts of the read cycle of the NAND cell type EEPROM of this embodiment. 16 and 17 show the first half of the read cycle, and FIGS. 18 and 19 show the second half. For ease of understanding the timing, each figure shows the waveforms of the chip enable / CE, row address and column address signals. The read operation will be described below with reference to this timing chart.

  When the chip enable / CE changes from “H” level to “L” level and a row address and a column address are taken in the chip from outside, an address transition detection circuit operates inside the chip, as shown in FIG. , A row address transition detection pulse and a column address transition detection pulse are generated.

  When reading the data of the memory cells connected to the odd-numbered bit lines BL0A,..., BLnA by the fetched row address, the even-numbered bit lines BL0B,. It is kept at Vss. That is, according to the row address, among the control signals SETA and SETB, SETA changes from Vcc to Vss, thereby turning off the read discharge transistors Q01A,..., Qn1A provided on the odd-numbered bit lines BL0A, BL0A, BLnA. Become. At the same time, the control signal PRE becomes Vss, and among the control signals SELA and SELB of the bit line selection gate, SELA becomes "H" level. This turns on the select gate transistors Q03A,..., Qn3A provided on the odd-numbered bit lines BL0A,..., BLnA, and precharges the odd-numbered bit lines BL0A,. The even-numbered bit lines BL0B,..., BLnB are kept at Vss.

  The sense amplifiers S / A0,..., S / An are inactivated before the data of the memory cell is read out to the bit line. This is performed by changing the control signals SEN and RLCH of the sense amplifier from Vcc to Vss and the control signals SENB and RLCHB from Vss to Vcc. After the odd-numbered bit lines BL0A,..., BLnA are precharged to the read potential VR, the control signal SEN is temporarily changed from Vss to Vcc, then to Vss again to initialize the sense amplifier, and the control signal RLCHB May be changed from Vcc to Vss and Vcc in synchronization with this.

  Next, the non-selected word lines determined by the row address, WL01 to WL07 in the case shown, and the selection gate lines SGS0 and SGD0 are changed from Vss to Vcc, and the selected word line WL00 is maintained at Vss. The threshold voltage of the memory cell is set to, for example, 0.5 V or more and 3.5 V or less for “1” data, and −0.1 V or less for “0” data. Then, the selected word line WL00 is set to Vss = 0V, and the non-selected word lines WL01 to WL07 and the selection gate lines SGS0 and SGD0 are set to Vcc = 5V, so that the memory cells MC00A, MC00B, to MC0nA along the selected word line WL00. , MC0nB, the data of the memory cells MC00A,..., MC0nA connected to the odd-numbered bit lines BL0A,. Since the even-numbered unselected bit lines BL0B,..., BLnB are fixed at Vss, the data of the memory cells MC00B,..., MConB at the intersection of these selected word lines WL00 is not read.

  The data read to the odd-numbered bit lines BL0A,..., BLnA in this manner is obtained by activating the sense amplifiers S / A0,..., S / An, that is, when the control signals SEN, RLCH are Vcc, SENB, RLCHB. Become Vss, and are latched by the sense amplifiers S / A0,..., S / An respectively.

  When the column selection signal CSL0 goes to "H" level, the data latched by the sense amplifier S / A0 is output to the outside via the input / output lines I / O and I / OB and the output buffer. . When the column address changes and the column address transition detection circuit detects this and the next column selection line CSL1 goes to "H" level, the data latched by the sense amplifier S / A1 is output. Thereafter, in the same manner as in the previous embodiment, continuous column reading is performed for the odd-numbered bit lines.

  When the row address further changes, the row address transition detection circuit detects this and generates a pulse. Then, the process is performed again from the selection of the even-numbered bit line or the odd-numbered bit line. FIGS. 18 and 19 show the case where the even-numbered bit line is selected. At this time, odd-numbered bit lines BL0A,..., BLnA,... Are fixed to Vss, and data of the memory cells of even-numbered bit lines BL0B,. At this time, if WL00 is selected as the selected word line, the data of the memory cells MC00B,..., MC0nB is read out to the even-numbered bit lines BL0B,. Then, when the column selection signal CSL0 goes to "H" level, the data of the sense amplifier S / A0 is output. Similarly, in this case as well, continuous column reading can be performed on even-numbered bit lines.

  During the above read operation, the "H" level potential BITH and the "L" level potential BITL of the sense amplifier may be Vcc and Vss, respectively.

  Next, a data write operation in this embodiment will be described with reference to FIGS. 20 and 21 show the first half of the write cycle, and FIGS. 22 and 23 show the second half. The chip enable / CE, the write enable / WE, the input data Din, the row address and the column address are shown in all figures to make the timing easy to understand.

  The chip enable / CE and the write enable / WE change from “H” level to “L” level, and the write operation is started. First, data is written from the input / output buffer to the sense amplifiers S / A0,..., S / An via the input / output lines I / O and I / OB. This is because the column selection signals CSL0, CSL1,... Sequentially become "H" level in accordance with the column address as shown in FIG. 21, and serial data is sequentially written to the sense amplifier in synchronization with this. . If there are (n + 1) sense amplifiers, this is repeated until data is written to the nth sense amplifier.

  During the data writing to the sense amplifier, the write control signals WSELA and WSELB both change from Vss to VH + α, and all the bit lines BL are precharged to the intermediate potential VH higher than Vcc.

  After data is written to the last nth sense amplifier S / An, one of the write control signals WSELA and WSELB becomes Vss according to the row address. FIG. 22 shows a case where data is written to odd-numbered bit lines BL0A,..., BLnA. In this case, the control signal WSELA becomes Vss. As a result, the write / charge transistors Q04A,..., Qn4A of the odd-numbered bit lines BL0A,. Thereby, the odd-numbered bit lines BL0A,..., BLnA are set to Vss (in the case of "1" data) or VH ("", depending on the data previously transmitted to the sense amplifiers S / A0,. 0 "data).

  Thereafter, the selected word line WL00 changes from Vss to the writing potential Vpp, and the other word lines WL01 to WL07 and the selection gate line SGD0 on the drain side change from Vss to VH + α. Of the odd-numbered bit lines BL0A, BL0A,..., BLnA, electron injection ("1" writing) is performed on the floating gate in the memory cell connected to the bit line set to Vss. During this time, the even-numbered bit lines BL0B,..., BLnB are all fixed at the intermediate potential VH instead of floating because the charging transistors Q04B,.

  When writing data to the even-numbered bit lines BL0B,..., BLnB, conversely, all of the unselected odd-numbered bit lines BL0A,..., BLnA are fixed to the intermediate potential VH during the writing operation. become.

  During the above data write operation, the low potential side BITL of the sense amplifier may be Vss.

  In the above embodiment, the electrically rewritable EEPROM is exclusively described, but the present invention is also effective for an ultraviolet erasing type EPROM.

FIG. 1 is a diagram showing a configuration of a part of a core circuit of an EEPROM according to an embodiment of the present invention. The figure which shows the structure of the remainder of the same core circuit. FIG. 4 is a timing chart showing the first half of a read cycle of the EEPROM of the embodiment. FIG. 7 is a timing chart showing the latter half of the read cycle. FIG. 6 is a diagram illustrating a configuration of a part of a core circuit of an EEPROM according to another embodiment. The figure which shows the structure of the remainder of the same core circuit. FIG. 4 is a timing chart showing the first half of a read cycle of the EEPROM of the embodiment. FIG. 7 is a timing chart showing the latter half of the read cycle. FIG. 7 is a diagram illustrating a configuration of a part of a core circuit according to an embodiment in which a data write control circuit unit is added to the EEPROM of FIGS. 5 and 6; The figure which shows the structure of the remainder of the same core circuit. FIG. 4 is a timing chart showing the first half of a write cycle according to the first embodiment; FIG. 4 is a timing chart showing the latter half of the write cycle. FIG. 11 is a diagram illustrating a configuration of a part of a core circuit of an EEPROM according to still another embodiment. FIG. 3 is a diagram showing a configuration of a cell array unit of the core circuit. The figure which shows the structure of the remainder of the same core circuit. FIG. 4 is a timing chart showing the first half of a read cycle of the EEPROM of the embodiment. FIG. 3 is a timing chart showing the first half of a read cycle. FIG. 4 is a timing chart showing the latter half of the read cycle of the EEPROM of the embodiment. FIG. 9 is a timing chart showing the latter half of the read cycle. FIG. 4 is a timing chart showing the first half of a write cycle of the EEPROM of the embodiment. FIG. 9 is a timing chart showing the first half of the write cycle. FIG. 4 is a timing chart showing the latter half of the write cycle of the EEPROM of the embodiment. FIG. 9 is a timing chart showing the latter half of the write cycle.

Explanation of reference numerals

MC: memory cell BL: bit line WL: word line S / A: sense amplifier Q01, Q21,-, Q (n-1) 1, Q11, Q31,-, Qn1-read discharge transistor Q02, Q22,-, Q (n-1) 2, Q12, Q32, ..., Qn2 ... charge transistor for reading Q04A, Q04B, ..., Qn4A, Qn4B ... charge transistor for writing

Claims (10)

Multiple bit lines,
A plurality of word lines intersecting these bit lines;
A rewritable nonvolatile semiconductor memory cell which is arranged at each intersection of the bit line and the word line, is driven by the word line, and exchanges data with the bit line,
A sense amplifier provided for every one or two of the bit lines and detecting data of a memory cell selected by the word line;
A precharge means connected to the bit line and having a read charge transistor for applying a predetermined read potential to the bit line for data read and a read discharge transistor for setting an unselected bit line to the ground potential at the time of read;
With
The read charge transistor and the read discharge transistor are controlled by different control signals obtained by detecting an address for every other bit line corresponding to the address inputted at the start of the read operation. All of one of the even-numbered bit lines are selected bit lines, all of the other are unselected bit lines, the unselected bit lines are held at the ground potential, and the selected bit lines are floating after precharge. A non-volatile semiconductor device connected to the sense amplifier, wherein data of all memory cells arranged at respective intersections of a selected word line and the selected bit line are simultaneously read out to the sense amplifier. Storage device.   In a data read cycle, data read to the odd-numbered bit line or the even-numbered bit line as the selected bit line is simultaneously detected by the sense amplifier, and the data latched by the sense amplifier is applied to the column. 2. The non-volatile semiconductor memory device according to claim 1, wherein the data is continuously read in accordance with the address.   2. The non-volatile semiconductor memory device according to claim 1, wherein the odd-numbered bit lines and the even-numbered bit lines form two pairs, and each pair shares a sense amplifier.   4. The nonvolatile semiconductor memory according to claim 3, wherein said read charge transistor is provided at a position where two bit lines are grouped, and said read discharge transistor is provided for each bit line. apparatus.   2. The nonvolatile semiconductor memory cell according to claim 1, wherein the nonvolatile semiconductor memory cell is an electrically rewritable nonvolatile semiconductor memory cell, and a plurality of the nonvolatile semiconductor memory cells are connected to form a cell block. Non-volatile semiconductor storage device.   6. The nonvolatile semiconductor memory device according to claim 5, wherein said cell block is a NAND cell formed by connecting a plurality of electrically rewritable nonvolatile semiconductor memory cells in series. Multiple bit lines,
A plurality of word lines intersecting these bit lines;
A rewritable nonvolatile semiconductor memory cell which is arranged at each intersection of the bit line and the word line and is driven by the word line to exchange data with the bit line;
A sense amplifier provided for every two bit lines and detecting data of a memory cell selected by the word line;
A precharge means connected to the bit line, for applying a predetermined read potential to a selected bit line for data read, and for holding an unselected bit line at a predetermined fixed potential;
With
Among the memory cells arranged at each intersection of one word line and the plurality of bit lines, a first memory arranged at each intersection of all odd-numbered bit lines and the word line A nonvolatile semiconductor memory wherein data of a second memory cell group arranged at each intersection of a cell group and all even-numbered bit lines and the word lines are simultaneously read out to the sense amplifier, respectively. apparatus. Multiple bit lines,
A plurality of word lines intersecting these bit lines;
A rewritable nonvolatile semiconductor memory cell which is arranged at each intersection of the bit line and the word line, is driven by the word line, and exchanges data with the bit line,
A sense amplifier provided for every one or two of the bit lines and detecting data of a memory cell selected by the word line;
A precharge means connected to the bit line, for applying a predetermined read potential to a selected bit line for data read, and for holding an unselected bit line at a predetermined fixed potential;
With
Of the memory cells arranged at each intersection between the selected word line and the bit line, a first cell arranged at each intersection between the word line and all of the odd-numbered bit lines selected by the address. Data of any one of the second memory cell group arranged at each intersection of the word line with all of the even-numbered bit lines selected by the memory cell group and the address are read out to the sense amplifier simultaneously. A nonvolatile semiconductor memory device characterized by the above-mentioned.   9. A serial data read for successively reading data read by said sense amplifier corresponding to a column address is performed for each of a first memory cell group and a second memory cell group. Nonvolatile semiconductor memory device.   8. When one of the odd-numbered bit line and the even-numbered bit line is selected, the other is set to the ground potential before the word line is selectively driven. Or a nonvolatile semiconductor memory device according to item 8.

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