KR101472183B1 - Method for heat-treating silicon wafer - Google Patents

Abstract

A method for heat treatment of a silicon wafer capable of increasing the in-plane uniformity of BMD density in a radial direction of a bulk portion of a wafer grown by the CZ method. In addition, it is possible to provide a method for heat treatment of a silicon wafer which can increase the in-plane uniformity of the BMD size and further reduce the COP in the surface layer portion of the wafer. The silicon wafer sliced from the silicon single crystal ingot grown by the CZ method is heated to a first maximum temperature within a range of 1325 DEG C to 1400 DEG C in an oxidizing gas atmosphere to maintain the first maximum temperature, A step of performing a first heat treatment in which the temperature of the silicon wafer subjected to the first heat treatment is lowered at a temperature lowering rate of not lower than 250 deg. C / second and not higher than 250 deg. C / second; And a step of performing a second heat treatment for raising the temperature to the maximum reaching temperature and maintaining the second maximum reaching temperature.

Description

[0001] METHOD FOR HEAT-TREATING SILICON WAFER [0002]

The present invention relates to a heat treatment method of a silicon wafer for heat-treating a silicon wafer (hereinafter simply referred to as a wafer) sliced from a silicon single crystal ingot grown by a Czochralski method (hereinafter also referred to as a CZ method).

In recent years, due to the high integration of semiconductor devices, quality requirements for silicon wafers used as the substrates have become strict, and COPs in the surface layer portion (for example, a depth region from the surface to 7 mu m in depth) In addition to the reduction of the defect density of the wafer, it is also required to improve the wafer strength against heat treatment with high stress.

As a method of reducing COP, JP-A-6-295912 discloses a method in which a silicon wafer is heated in a hydrogen gas atmosphere or a mixed gas atmosphere of a hydrogen gas and an inert gas at a heat treatment temperature of 1100 to 1300 占 폚, For 1 minute to 48 hours to form a denuded zone (DZ) layer in the surface layer portion of the silicon wafer.

The Balk Micro Defect (hereinafter referred to as BMD) deposited on the bulk portion of the wafer during the heat treatment serves as a gettering site of impurities diffused in the surface layer portion in the subsequent semiconductor device forming step, .

It is preferable that the BMD density in the bulk portion is uniform in the plane in the radial direction of the wafer. If the BMD density fluctuates in the wafer surface, the wafer strength changes in the fluctuating portion. Therefore, slip dislocations tend to occur in the subsequent semiconductor device formation heat treatment or the like starting from this portion there is a problem.

The in-plane distribution of the BMD density in the radial direction of the wafer reflects the in-plane distribution of the grown-in defects introduced at the time of growing the single crystal by the CZ method. Therefore, in order to increase the in-plane uniformity of the BMD density, it is necessary to uniformly control the in-plane distribution of the grown-in defects introduced at the time of growing the single crystal.

However, such a control needs to finely control the crystal thermal history and the growth rate of the hot zone and the like, and there is a problem that the cost is very high.

Further, when an OSF region in which a large number of oxidation-induced stacking faults (hereinafter referred to as OSFs) exist in the single crystal growth, an OSF ring is generated in the diameter direction of the sliced wafer. In this case, it is known that, in the vicinity of the OSF ring of the wafer, there are very few BMD nuclei introduced at the time of growing the single crystal, that is, a BMD low density region where the BMD density greatly decreases after the heat treatment.

Japanese Unexamined Patent Publication (Kokai) No. Hei 8-330316 discloses a method for preventing such an OSF ring from being generated in a wafer surface. In the method for growing a single crystal, the crystal growth rate is lowered, Discloses a technique of growing a defect-free region in which there is a lack of atoms or a small amount of defects due to the balance.

However, the method described in JP-A-8-330316 discloses a method of lowering the crystal growth rate, resulting in lower productivity and higher cost. Since the BMD hardly precipitates in the bulk portion, There is a problem that it is said.

Japanese Unexamined Patent Publication (Kokai) No. 2006-93645 discloses a means for increasing the in-plane uniformity of the BMD density of the wafer even when the OSF region is formed at the time of growing the single crystal. The nitrogen concentration is 2.9x10 ^{14 to} 5.0x10 ^And the OSF ring grown in the oxygen concentration range of 1.27 x 10 ^{18 to} 3.0 x 10 ¹⁸ atoms / cm 3 is maintained at a temperature of 600 ° C to 800 ° C under a reducing gas or an inert gas atmosphere And the temperature rise rate of 0.5 ° C / min to 2.0 ° C / min is maintained until the heat treatment temperature is reached when the heat treatment is performed at 1000 ° C to 1200 ° C.

However, since the method described in JP-A-2006-93645 can increase the BMD density in the BMD low density region, the in-plane nonuniformity of the BMD density due to the presence of the OSF ring is improved to some extent, Leaving behind the influence of poetry.

Even when the crystal growth rate is increased while precisely controlling the crystal thermal history and growth rate of the hot zone and the OSF ring is excluded to the outside and the entire inside of the wafer plane is taken as a V-rich region into which COP is largely absorbed, There is a limit in the convection control of the melt (the number of revolutions of the quartz crucible, the pressure in the furnace, the heater temperature, etc.) at the time of growing, and there is a limitation in uniformly controlling the BMD density in the plane of the wafer in the plane.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a heat treatment method of a silicon wafer capable of increasing the in-plane uniformity of the BMD density in the radial direction of the bulk portion of a wafer grown by the CZ method, do. It is another object of the present invention to provide a heat treatment method of a silicon wafer capable of increasing the in-plane uniformity of BMD size and further reducing the COP in the surface layer portion of the wafer.

A heat treatment method for a silicon wafer according to the present invention is a method for heating a silicon wafer sliced from a silicon single crystal ingot grown by the CZ method to a first maximum temperature within a range of 1325 DEG C to 1400 DEG C in an oxidizing gas atmosphere, A step of performing a first heat treatment in which the temperature is lowered at a temperature lowering rate of 50 ° C / sec or more and 250 ° C / sec or less after the first maximum attained temperature is maintained; and a step of heat treating the silicon wafer subjected to the first heat treatment in a non-oxidizing gas atmosphere, And performing a second heat treatment for raising the temperature to a second maximum temperature within a range of 900 ° C or higher and 1250 ° C or lower to maintain the second highest temperature and then lowering the temperature.

The cooling rate in the first heat treatment is preferably 120 ° C / second or more and 250 ° C / second or less.

The rate of temperature rise to the second maximum temperature in the second heat treatment is preferably 1 ° C / min or more and 5 ° C / min or less.

According to the present invention, there is provided a heat treatment method of a silicon wafer capable of increasing the in-plane uniformity of the BMD density in the radial direction of a bulk portion of a wafer grown by the CZ method. In addition, it is possible to increase the in-plane uniformity of the BMD size, and furthermore to provide a heat treatment method of a silicon wafer capable of reducing the COP in the surface layer portion of the wafer.

1 is a conceptual flowchart (first heat treatment) on a cross section of a wafer for explaining the effect of the present invention.
2 is a conceptual flowchart (second heat treatment) on a cross section of a wafer for explaining the effect of the present invention.
Fig. 3 is a conceptual flowchart of a wafer cross-section for explaining the effect of the present invention in the first heat treatment when the OSF ring exists in the radial direction of the wafer.
Fig. 4 is a conceptual flowchart (first heat treatment) on the wafer cross section for explaining the effect of the present invention when the oxygen concentration of the wafer to be heat-treated is high.
5 is a conceptual flowchart (second heat treatment) on the cross section of the wafer for explaining the effect of the present invention when the oxygen concentration of the wafer to be heat-treated is high.
6 is a schematic cross-sectional view showing an example of an RTP apparatus used in a heat treatment method of a silicon wafer according to the present invention.
7 is a conceptual diagram showing an example of the temperature sequence of the first heat treatment by RTP.
8 is a conceptual diagram showing an example of the temperature sequence of the second heat treatment using the vertical heat treatment apparatus.
9 is a process flow chart showing a first embodiment of a method of manufacturing a silicon wafer including a method for heat treatment of a silicon wafer according to the present invention.
10 is a process flow chart showing a second embodiment of a method of manufacturing a silicon wafer including a method for heat treatment of a silicon wafer according to the present invention.
11 is a process flow chart showing a third embodiment of a method of manufacturing a silicon wafer having a method for heat treatment of a silicon wafer according to the present invention.
12 is a process flow chart showing a fourth embodiment of a method of manufacturing a silicon wafer including a method for heat treatment of a silicon wafer according to the present invention.
13 is a process flow chart showing a fifth embodiment of a method for manufacturing a silicon wafer including a method for heat treatment of a silicon wafer according to the present invention.
14 is an in-plane distribution of the BMD density in the wafer radial direction from the center to the periphery of the wafer in Examples 1 to 3;
Fig. 15 is an in-plane distribution of the BMD density in the wafer radial direction from the center to the periphery of the wafer in Examples 4 to 6. Fig.
16 is an in-plane distribution of the BMD density in the wafer radial direction from the center to the periphery of the wafer in Examples 7 to 9;
17 is an in-plane distribution of the BMD density in the wafer diameter direction from the center to the periphery of the wafer in Comparative Examples 1 to 3 and Conventional Example 1. Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings and the like.

A heat treatment method for a silicon wafer according to the present invention is a method for heating a silicon wafer sliced from a silicon single crystal ingot grown by the CZ method to a first maximum temperature within a range of 1325 DEG C to 1400 DEG C in an oxidizing gas atmosphere, A step of performing a first heat treatment in which the temperature is lowered at a temperature lowering rate of 50 ° C / sec or more and 250 ° C / sec or less after the first maximum attained temperature is maintained; and a step of heat treating the silicon wafer subjected to the first heat treatment in a non-oxidizing gas atmosphere, And a step of performing a second heat treatment for raising the temperature to a second maximum temperature within a range of 900 ° C to 1250 ° C to maintain the second maximum temperature, and then lowering the temperature.

Since the present invention includes such a process, the in-plane uniformity of the BMD density in the radial direction of the bulk portion of the wafer grown by the CZ method can be enhanced. In addition, the in-plane uniformity of the BMD size can be increased, and further, the COP at the surface layer of the wafer can be reduced.

Fig. 1 and Fig. 2 are conceptual flowcharts for explaining the effect of the present invention on the cross section of a wafer. Fig. 1 shows the effect of the first heat treatment, and Fig. 2 shows the effect of the second heat treatment.

In the first heat treatment, the temperature is raised and maintained in the oxidizing gas atmosphere (oxygen (O ₂ ) in FIG. 1) to the maximum reaching temperature in the range of 1325 ° C. to 1400 ° C. (first maximum reaching temperature) , The inner wall oxide film (SiO ₂ ) is dissolved and becomes void (FIG. 1 (b)). Further, the void disappears due to diffusion as a public. And / or the void completely disappears by a large amount of interstitial silicon (not shown) that is injected into the wafer by the oxidizing gas atmosphere (Fig. 1 (c)). Since the BMD nuclei introduced at the time of growing the single crystal are heat-treated within the range of the maximum attained temperature, they dissolve in the wafer and disappear (FIG. 1 (b) to (c)).

In the second heat treatment, the temperature in the non-oxidizing gas atmosphere (argon (Ar) in FIG. 2) is raised to a temperature within the range of 900 ° C. to 1250 ° C., Diffused outward to the bulk portion (FIG. 2 (b)). Therefore, BMD nuclei are not precipitated at the surface layer portion of the wafer, but precipitated at the bulk portion (Fig. 2 (c)).

From the above, the BMD nuclei introduced at the time of monocrystalline growth are dissolved in the wafer by the first heat treatment and disappear. In the second heat treatment, BMD nuclei are newly precipitated in the bulk portion. Therefore, in the second heat treatment, the BMD nuclei can be newly precipitated and grown while the fluctuation of the BMD nuclei introduced at the time of growing the single crystal is excluded (once canceled). Therefore, in addition to the in-plane uniformity of the BMD density in the radial direction of the wafer, the in-plane uniformity of the BMD size can also be increased.

It is preferable that the maximum attained temperature (first maximum attained temperature) in the first heat treatment is in the range of 1325 ° C to 1400 ° C.

When the first maximum attained temperature is a low temperature of less than 1325 ° C, it is difficult to dissolve BMD nuclei introduced at the time of monocrystal growing to disappear. Therefore, it is difficult to exclude the fluctuation of the BMD nuclei introduced at the time of growing the single crystal, and it is difficult to increase the in-plane uniformity of the BMD size in addition to the in-plane uniformity of the BMD density in the diameter direction of the wafer. When the first maximum attained temperature exceeds 1400 DEG C, the temperature becomes high, and slip dislocations are likely to occur, which is not preferable.

The upper limit value of the first maximum attained temperature is more preferably 1380 DEG C or lower in order to make the lifetime of the heat treatment apparatus used longer.

It is preferable that the temperature decreasing rate from the first maximum attained temperature in the first heat treatment is not less than 50 ° C / second and not more than 250 ° C / second.

Since the first heat treatment is performed in an oxidizing gas atmosphere as described above, a large amount of interstitial silicon is generated, and at the same time, pores of thermal equilibrium concentration also occur. This pore forms an O2-V complex with interstitial oxygen. This O2-V complex is a starting point for the generation of BMD nuclei in the subsequent second heat treatment.

In addition, when the cooling rate is less than 50 ° C / second, the vacancy diffuses outwardly during the cooling down and disappears, so that the O 2 -V complex may not be formed.

Therefore, by setting the cooling rate at 50 占 폚 / second or more in the first heat treatment, it is possible to leave a large amount of the generated voids in the bulk portion. Therefore, it is possible to sufficiently generate and grow BMD nuclei (high density BMD density) in the second heat treatment.

In addition, when the temperature lowering rate is too high, a slip dislocation may occur in the wafer in order to abruptly lower the temperature. Therefore, the upper limit value is preferably 250 캜 / second or less.

It is more preferable that the cooling rate in the first heat treatment is not less than 120 ° C / second and not more than 250 ° C / second.

By setting the cooling rate at such a low temperature, the BMD density in the radial direction of the bulk portion of the wafer and the in-plane uniformity of the size can be further increased.

It is preferable that the temperature lowering at the temperature decreasing rate from the first maximum attained temperature is performed from 400 deg. C to 600 deg. C or less from the viewpoints of inhibiting diffusion of the interstitial silicon and productivity.

Further, the heat treatment method of the silicon wafer according to the present invention can increase the BMD density and the in-plane uniformity of its size even when the OSF ring exists in the radial direction of the wafer, that is, the BMD has a low density region in the wafer plane .

Fig. 3 is a conceptual flowchart of a wafer cross-section for explaining the effect of the present invention in the first heat treatment when the OSF ring exists in the radial direction of the wafer.

In the wafer in which the OSF ring is present, as described above, there exists a BMD low density region in which the BMD density is greatly lowered in the vicinity of the OSF ring (Fig. 3 (a)).

In the method of heat treatment of the silicon wafer according to the present invention, even in such a wafer, by performing the first heat treatment, the COP and the BMD nuclei disappear by the same mechanism as described in Fig. 1 (Fig. 3 (b) )).

Therefore, even if the OSF ring exists in the radial direction of the wafer, it is possible to increase the BMD density and the in-plane uniformity of the size of BMD nuclei in the BMD low-density region.

In the method of heat treatment of a silicon wafer according to the present invention, when the oxygen concentration of the wafer to be heat-treated is high, that is, when the oxygen concentration is controlled to be high during the single crystal growth, COP remains in the surface layer portion of the wafer after the first heat treatment .

Figs. 4 and 5 are conceptual flowcharts of wafer cross-sections for explaining the effect of the present invention when the oxygen concentration of the wafer to be heat-treated is high. Fig. 4 shows the effect of the first heat treatment, and Fig. 5 shows the effect of the second heat treatment.

In the first heat treatment, oxygen contained in the oxidizing gas atmosphere is inwardly diffused from the wafer surface to the surface layer portion. Therefore, when the oxygen concentration of the wafer to be heat treated is high, the oxygen concentration in the surface layer portion becomes near the solid melting limit a) to b). Therefore, the inner wall oxide film of the COP is hardly dissolved in the surface layer portion. As a result, even if a large amount of interstitial silicon is introduced, COP can not be filled in the COP, so that COP remains in the surface layer portion. In the BMD nuclei introduced at the time of growing the single crystal, even if the oxygen concentration is high, since the BMD nucleus is small, it dissolves in the wafer and disappears (Figs. 4 (a) to 4 (c)).

However, as shown in Fig. 4 (c), even if COP remains in the surface layer portion in the first heat treatment, in the second heat treatment, in a non-oxidizing gas atmosphere (argon in Fig. 5) The heat treatment is performed. By this heat treatment, oxygen diffuses outwardly from the surface layer portion and further diffuses outward to the bulk portion, so that the oxygen concentration in the surface layer portion decreases near the solid melting limit (FIG. 5 (b)).

Therefore, by performing the second heat treatment, the oxygen concentration in the surface layer portion is lowered, so that the inner wall oxide film of the COP existing in the surface layer portion is dissolved to become a void. Thereafter, the void disappears by rearrangement of the silicon atoms ((b) to (c) of Fig. 5). 2, the BMD nuclei are not precipitated at the surface layer portion of the wafer but precipitated in the bulk portion (FIG. 5 (c)).

As described above, the heat treatment method of the silicon wafer according to the present invention can increase the BMD density of the bulk portion and the in-plane uniformity of the size of the wafer even when the oxygen concentration of the wafer subjected to the heat treatment is high. In addition, can do.

In the present invention, the case where the oxygen concentration is high means that the oxygen concentration of the wafer is 1.2 × 10 ¹⁸ atoms / cm 3 (old-ASTM) or more.

When the first heat treatment is performed in a non-oxidizing gas atmosphere (a reducing gas atmosphere (hydrogen gas, nitrogen gas, etc.) or an inert gas atmosphere (argon gas or the like)) instead of an oxidizing gas atmosphere, BMD The nucleus can not disappear, and the BMD nucleus grows on the contrary. This is because the outward diffusion of oxygen from the surface layer portion to the bulk portion is greatly promoted.

The partial pressure of the oxygen gas in the oxidizing gas atmosphere is preferably 20% or more and 100% or less (preferably 100% oxygen gas).

By setting the partial pressure of the oxygen gas to 20% or more, a large amount of interstitial silicon can be injected into the wafer, and COP can be reliably reduced.

It is preferable that the gas other than the oxygen gas in the oxidative gas atmosphere (except for the case where the partial pressure of the oxygen gas is 100%) is argon gas.

By using argon gas, formation of another film such as a nitride film, chemical reaction, and the like can be more reliably avoided.

It is preferable that the maximum reaching temperature (second maximum reaching temperature) in the second heat treatment is in a range of 900 占 폚 to 1250 占 폚.

When the second maximum attained temperature is lower than 900 캜, since the temperature is low, outward diffusion of oxygen becomes difficult to occur. For this reason, it is difficult to dissolve the inner wall oxide film of COP remaining in the surface layer portion of the wafer, and it is difficult to extinguish the COP at the surface layer portion.

When the second maximum reaching temperature exceeds 1250 占 폚, the outward diffusion of oxygen from the surface layer portion of the wafer becomes large. As a result, the oxygen concentration in the surface layer is significantly lowered, and the pinning effect of the slip dislocation caused by oxygen is lowered, so that a slip dislocation may occur in the wafer.

When the second heat treatment is performed in the oxidizing gas atmosphere instead of the non-oxidizing gas atmosphere, oxygen is inwardly diffused into the surface layer portion of the wafer. Therefore, in the case of a silicon wafer having a high oxygen concentration, the oxygen concentration in the surface layer portion is kept high. Therefore, in the second heat treatment, the inner wall oxide film of the COP remaining on the surface layer portion of the wafer is difficult to dissolve, so that it may be difficult to eliminate the COP in the surface layer portion.

The non-oxidizing gas atmosphere is preferably a non-oxidizing gas containing argon gas (preferably argon 100% gas).

By using argon gas, heat treatment can be performed without forming other films such as a nitride film or chemical reaction.

The first heat treatment is preferably performed by RTP using a known rapid thermal annealing (RTP) apparatus. The term RTP as used herein refers to a high-speed lift-on heat treatment in which the temperature increase rate and the temperature decrease rate are 1 deg. C / sec or more.

6 is a schematic cross-sectional view showing an example of an RTP apparatus used in a heat treatment method of a silicon wafer according to the present invention.

The RTP apparatus 10 shown in Fig. 6 includes a reaction chamber 20 for accommodating a wafer W and performing a heat treatment, a wafer holding unit (not shown) provided in the reaction chamber 20 for holding the wafer W 30 for heating the wafer W, and a heating unit 40 for heating the wafer W. The first space 20a and the second space 20b are formed in a state in which the wafer W is held by the wafer holding portion 30. [ The first space 20a is a space surrounded by the inner wall of the reaction chamber 20 and the surface of the wafer W (device formation surface) W1. The second space 20b is a space surrounded by the inner wall of the reaction chamber 20 and the back surface W2 of the wafer W opposed to the surface W1 side.

The reaction chamber (20) has a supply port (22) and an outlet port (26). The supply port 22 supplies atmosphere gas F _A (solid line arrow) into the first space 20a and the second space 20b. The outlet 26 discharges the supplied atmospheric gas F _A from the first space 20a and the second space 20b. The reaction chamber 20 is made of, for example, quartz.

The wafer holding section 30 includes a susceptor 32 for holding the outer peripheral portion of the back surface W2 of the wafer W in a ring shape and a susceptor 32 for holding the susceptor 32, And a rotating body 34 that rotates the susceptor 32. The susceptor 32 and the rotating body 34 are made of, for example, SiC.

The heating section 40 is constituted by a plurality of halogen lamps 50. A plurality of halogen lamps 50 are arranged above the surface W1 of the wafer W held by the wafer holding section 30 and outside the reaction chamber 20 below the back surface W2, The wafer W is heated from both surfaces by lamp heating by light irradiation of the wafer 50.

The heat treatment using the RTP apparatus 10 shown in Fig. 6 is performed as follows. The wafer W is introduced into the reaction chamber 20 from a wafer inlet not shown in the reaction chamber 20 so that the outer peripheral portion of the back surface W2 of the wafer W is held by the susceptor (32). The atmosphere gas F _A is supplied from the supply port 22 and the wafer W is heated by the heating unit 40 while the wafer W is being rotated.

7 is a conceptual diagram showing an example of the temperature sequence of the first heat treatment by RTP.

As shown in Fig. 7, a silicon wafer is held on a rotatable susceptor provided in a reaction space of a well-known RTP apparatus maintained at a temperature T0 (preferably 400 deg. C or more and 600 deg. C or less) And supplies the oxidizing gas. Next, the temperature is rapidly raised from the temperature T0 to the first maximum temperature 1325 DEG C to 1400 DEG C (temperature T1) at a temperature rise rate DELTA Tu1 (DEG C / sec.), (t1 (sec)). Thereafter, the temperature is rapidly reduced from the temperature T1 to the temperature decreasing rate DELTA Td1 (DEG C / sec), and the temperature is reduced to, for example, the temperature T0.

The temperatures T0 and T1 are set in such a manner that the temperatures T0 and T1 are set in the same manner as in the case where the wafers W are placed in the reaction chamber 20 of the RTP apparatus 10 as shown in Fig. (The average temperature in the case where a plurality of radiation thermometers are arranged in the radial direction of the wafer W) measured by a radiation thermometer that is not used.

It is preferable that the holding time t1 for maintaining the first maximum reached temperature is 1 second or more and 60 seconds or less.

When the holding time t1 is less than 1 second, it may be difficult to completely eliminate the BMD nuclei or COP introduced at the time of growing the single crystal. If the holding time t1 exceeds 60 seconds, the productivity may be lowered, and other problems (impurity diffusion, slip, etc.) may occur.

It is preferable that the second heat treatment is performed by heat treatment using a vertical heat treatment apparatus. As the vertical type heat treatment apparatus, a well-known one (for example, a vertical type heat treatment apparatus described in Japanese Patent Application Laid-Open No. 2001-85349) is used. The term "heat treatment using the longitudinal heat treatment apparatus" as used herein means a low speed heat treatment in which the temperature raising rate and the temperature raising rate are 15 ° C./minute or less.

8 is a conceptual diagram showing an example of the temperature sequence of the second heat treatment using the vertical heat treatment apparatus.

As shown in Fig. 8, a well-known vertical boat holding a plurality of silicon wafers in a reaction space of a well-known vertical heat treatment apparatus maintained at a temperature T0 (preferably 400 DEG C or higher and 600 DEG C or lower) A non-oxidizing gas (for example, argon gas) is supplied into the reaction space. Next, the temperature is raised from the temperature T0 to the second maximum temperature of 900 DEG C to 1200 DEG C (temperature T2) at a temperature increase rate DELTA Tu2 (DEG C / min) The temperature is decreased from the temperature T2 to the temperature decreasing rate DELTA Td2 (DEG C / min), for example, to the temperature T0.

It is preferable that the holding time t2 for maintaining the second maximum reached temperature is 1 minute or longer and 120 minutes or shorter.

When the holding time t2 is less than 1 minute, it may be difficult to sufficiently precipitate and grow the BMD nuclei in the bulk portion of the wafer. Further, when the oxygen concentration of the silicon wafer is high, the disappearance of the COP in the surface layer portion in this second heat treatment may not be sufficiently achieved. If the holding time t2 exceeds 120 minutes, the productivity may be lowered, and other problems (impurity diffusion, slip, etc.) may occur.

The rate of temperature rise (? Tu2 in FIG. 8) to the second maximum temperature in the second heat treatment and the rate of temperature decrease (? Td2 in FIG. 8 in FIG. 8) from the second maximum temperature are 5 ° C / Deg.] C / minute or less.

By setting the temperature raising rate and the temperature lowering speed, it is possible to suppress the generation of the slip dislocation at the time of raising the temperature of the second heat treatment, and furthermore, the BMD density can be improved.

The temperature raising rate (? Tu1 in Fig. 7 in Fig. 7) at the time of the temperature elevation in the first heat treatment is preferably not less than 10 占 폚 / second and not more than 250 占 폚 / second in order to improve the productivity and further reduce the occurrence of slip.

The growth of the silicon single crystal ingot by the CZ method is controlled by controlling the V / G value (V: pulling rate, G: average value of the temperature gradient in the crystal axis in the pulling axis direction in the temperature range from the melting point of silicon to 1300 캜) It is preferable to grow a silicon single crystal ingot including a V-rich region into which a large amount of vacancies (COP) have been blown.

Specifically, by using a well-known single crystal pulling device, a seed crystal is brought into contact with a liquid surface of a silicon melt, and the seed crystal is pulled up while rotating the seed crystal and the quartz crucible to form a neck portion and a diameter Thereby forming an extension. Thereafter, the linear body portion is formed by controlling the V / G value to a predetermined value (e.g., 0.25 mm 2 / ° C min to 0.35 mm 2 / ° C min) so as to become the V-rich region while maintaining the desired diameter, , And a diameter reduction portion which is reduced in diameter from a desired diameter is formed and separated from the silicon melt.

By carrying out this method, the productivity can be further improved at the time of growing the single crystal.

Incidentally, the term " including the V-rich region " here does not exclude the above-described OSF region.

Next, a method of manufacturing a silicon wafer including the aforementioned heat treatment method of the silicon wafer will be described.

9 is a process flow chart showing a first embodiment of a method of manufacturing a silicon wafer including a method for heat treatment of a silicon wafer according to the present invention.

(S101) of growing a silicon single crystal ingot by the CZ method, a step (S102) of producing a disk-shaped wafer by slicing the silicon single crystal ingot, and a step (S104) of mirror-polishing the surface of the wafer subjected to the planarization treatment to be a surface on which the semiconductor device is to be formed, and performing the first heat treatment (S105) and the second heat treatment And performing a second heat treatment (S106).

That is, in the first aspect, the above-described heat treatment method for a silicon wafer is performed on a mirror-polished wafer whose surface is at least a semiconductor device forming surface.

By including such a process, a silicon wafer having the above-described effect can be obtained more reliably.

The planarization treatment may be performed by a known lapping process, a one-side grinding process, a two-side grinding process, an etching process (mainly, hydrofluoric acid (HF), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH) H ₂ O) are mixed at a predetermined ratio in an acid etch solution to immerse the entire surface of the planarized wafer. The mirror polishing includes known one-side polishing and two-side polishing.

That is, the mirror surface polishing (S104) from the flattening process (S103) is, for example, a double-side grinding process after lapping the front and back surfaces of the slice wafer. Thereafter, a step of double-side polishing, a step of etching after the lapping process, and a process of double-side polishing are performed.

10 is a process flow chart showing a second embodiment of a method of manufacturing a silicon wafer including a method for heat treatment of a silicon wafer according to the present invention.

(S201) of growing a silicon single crystal ingot by the CZ method, a step (S202) of manufacturing a disk-shaped wafer by slicing the silicon single crystal ingot, and a step (S203) of subjecting the flattened wafer to a planarization process; subjecting the flattened wafer to the first heat treatment (S204) and the second heat treatment (S205); (S206) of polishing the surface to be polished.

That is, in the second aspect, the above-described heat treatment method of the silicon wafer is performed on the wafer subjected to the planarization treatment.

By including such a process, in addition to the above-mentioned effects, even when the outward diffusion of oxygen from the surface layer portion during the second heat treatment is small and COP remains in the surface layer portion, the surface layer portion can be removed in the subsequent polishing step Therefore, it is preferable.

The planarized wafer subjected to the heat treatment in the second aspect includes a wafer subjected to a lapped process or a wafer subjected to an etched process.

11 is a process flow chart showing a third embodiment of a method of manufacturing a silicon wafer including a heat treatment method of a silicon wafer according to the present invention.

The third aspect of the present invention provides a method of manufacturing a slice wafer, comprising the steps of: (S301) growing a silicon single crystal ingot by a CZ method; (S302) slicing the silicon single crystal ingot to form a disk- (S305) of flattening the front and back surfaces of the sliced wafer subjected to the second heat treatment; and a step (S305) of performing a second heat treatment (S306) polishing the surface to be polished.

That is, in the third aspect, the heat treatment method of the silicon wafer is performed on the sliced wafer.

By including such a process, the same effects as those of the second embodiment described above can be obtained.

12 is a process flow chart showing a fourth embodiment of a method for producing a silicon wafer including a heat treatment method for a silicon wafer according to the present invention.

(S401) a step of growing a silicon single crystal ingot by the CZ method, a step (S402) of producing a disk-shaped wafer by slicing the silicon single crystal ingot, and a step (S403) of performing the first heat treatment on the wafer subjected to the planarization treatment, a step (S404) of polishing the surface serving as the semiconductor device formation surface of the first heat treated wafer, (S405); and a step (S406) of performing the second heat treatment on the mirror polished wafer.

That is, in the fourth aspect, the first heat treatment is performed after the planarizing treatment in the above-described heat treatment method of the silicon wafer, and the second heat treatment is performed after the mirror polishing.

By including such a process, in addition to the above effect, even if COP remains in the surface layer portion after the first heat treatment, it can be removed in the subsequent polishing step. As a result, the burden of the second heat treatment can be reduced (for example, the heat treatment temperature and the heat treatment time can be shortened).

13 is a process flow chart showing a fifth embodiment of a method for producing a silicon wafer including a heat treatment method for a silicon wafer according to the present invention.

The fifth aspect of the present invention provides a method of manufacturing a sliced wafer, comprising: a step (S501) of growing a silicon single crystal ingot by the CZ method; a step (S502) of slicing the silicon single crystal ingot to form a disk-shaped wafer; A step (S503) of performing the first heat treatment; a step (S504) of smoothing the front and back surfaces of the first heat treated wafer; a step of polishing at least a surface serving as a semiconductor device formation surface of the flattened wafer (S505); and a step (S506) of performing the second heat treatment on the mirror polished wafer.

That is, in the fifth aspect, the first heat treatment is performed on the slice wafer in the heat treatment method of the silicon wafer described above, and the second heat treatment is performed after the mirror polishing.

By including such a process, the same effect as that of the fourth aspect can be obtained.

[Example]

Hereinafter, the present invention will be described more specifically based on examples, but the present invention is not limited to the following examples.

(Test 1)

By controlling the V / G value (V: pulling rate, G: average value of the temperature gradient in the crystal axis in the pulling axis direction in the temperature range from the melting point of silicon to 1300 ° C) by the CZ method, And a silicon single crystal ingot including a V-rich region in which an OSF ring is generated in a part of the surface of the wafer when it was sliced was grown. A mirror-polished silicon wafer (300 mm in diameter, 775 μm in thickness, and an oxygen concentration of 1.2 to 1.3 × 10 ¹⁸ atoms / cm 3) sliced from the above-mentioned region was placed in a reaction space of a well-known RTP apparatus maintained at 400 ° C. . The temperature sequence shown in Fig. 7 was carried out in an atmosphere of 100% oxygen gas (flow rate 20 slm), a temperature raising rate of 50 캜 / sec and a holding time of 15 seconds at the maximum reaching temperature Sec), the first heat treatment was performed by changing the maximum reaching temperature and the temperature decreasing speed, and a plurality of wafers having different heat treatment conditions were fabricated.

Thereafter, the wafer subjected to the first heat treatment was placed in a reaction space of a well-known vertical heat treatment apparatus maintained at 600 ° C. 8, in a 100% argon gas atmosphere (flow rate 30 slm), the temperature raising rate was 1 to 5 deg. C / min, the maximum reaching temperature was 1200 deg. C, the holding time was 1 hour, And the second heat treatment was performed at a cooling rate of 1 to 5 占 폚 / minute and then cooled down to 600 占 폚.

As a conventional example, the wafer subjected to only the second heat treatment without the first heat treatment was produced.

Next, the wafer subjected to the second heat treatment was subjected to BMD precipitation heat treatment (4 hours at 800 占 폚 and 16 hours at 1000 占 폚) in a 100% gas atmosphere of oxygen. The wafer subjected to the above-described BMD precipitation heat treatment was measured by IR topography (MO-441 manufactured by Latex Corporation), and a bulk portion (7 mu m to 300 mu m in depth from the wafer surface in the radial direction from the center to the periphery, Mu m) were evaluated for the BMD density and the scattered light intensity. (0 mm) from the center of the wafer, 110 mm in the radial direction (in the BMD low density region) and 145 mm in the radial direction (in the BMD low density region) from the center of the wafer The BMD size at three points was calculated.

BMD size = scattered light intensity ^(1/6) x 20 (1)

Further, the number of defects in the surface layer portion from the surface of the wafer subjected to the second heat treatment to the depth of 5 탆 area was evaluated using an LSTD scanner MO601 manufactured by Latex, and the defect density thereof was calculated.

Further, the slip length occurring on the back surface of the wafer subjected to the second heat treatment was evaluated by X-ray topography (XRT300 manufactured by Kabushiki Kaisha Pharmaceutical Co., Ltd.).

Test conditions and evaluation results (surface layer defect density and BMD average size) in this test are shown in Table 1, and BMDs in the wafer diameter direction from the center to the periphery of the wafer in each condition of this test are shown in Figs. In-plane distribution of density.

As can be seen from Table 1 and Figs. 14 to 17, by performing the first heat treatment before the second heat treatment as compared with the case of performing only the second heat treatment (Conventional Example 1), the in-plane uniformity of the BMD size in the radial direction of the wafer It is recognized that it can raise sex.

Further, in the case where the maximum temperature reached in the first heat treatment is 1300 占 폚 or lower (Comparative Examples 1 and 2), and the temperature decreasing rate is 25 占 폚 / sec even at 1350 占 폚 (Comparative Example 3), the BMD density And the in-plane uniformity of the size is insufficient.

On the other hand, it is recognized that the BMD density in the radial direction of the wafer and the in-plane uniformity of the size thereof are increased when the temperature is 1325 ° C or higher and the cooling rate is 50 ° C / sec or more (Examples 1 to 9). Further, it is recognized that the BMD density and its size together with the temperature-decreasing rate of 120 DEG C / sec or more (Examples 2, 3, 5, 6, 8, and 9)

It is recognized that the defect density of the surface layer portion is low at any condition.

Further, the slip dislocations on the back surface of the wafer were not confirmed under all the conditions.

(Test 2)

The maximum temperature reached in the first heat treatment was 1325 占 폚, 1350 占 폚, and 1380 占 폚, and the rate of temperature decrease (占 폚 / second) was set to 50 占 폚 / sec. Further, the second maximum temperature was changed, and the second heat treatment was carried out under the same conditions as those of Test 1 except for the above.

Next, for the wafer subjected to the second heat treatment, the number of defects in the surface layer portion from the surface of the wafer subjected to the second heat treatment to the depth of 5 탆 was measured using an LSTD scanner MO601 manufactured by Latex, And the defect density was calculated.

Further, the slip length occurring on the back surface of the wafer subjected to the second heat treatment was evaluated by X-ray topography (XRT300 manufactured by Kabushiki Kaisha Pharmaceutical Co., Ltd.).

Table 2 shows test conditions and evaluation results (surface layer defect density) in this test.

Further, in Comparative Examples 5, 7, and 9, slip dislocations having a length of 5 mm to 10 mm were found on the back surface of the wafer, but other conditions were not confirmed.

As can be seen from the above results, it is recognized that, in the case of the second heat treatment, when the maximum reaching temperature is 800 캜 (Comparative Examples 4, 6, and 8), the defect density in the surface layer portion becomes high. Further, in the case where the maximum reaching temperature is 1300 占 폚 (Comparative Examples 5, 7, and 9), occurrence of slip is recognized.

On the other hand, in the second heat treatment, when the maximum reaching temperature is 900 占 폚 to 1250 占 폚, it is recognized that the defect density in the surface layer portion is also less than 1.0 / cm2.

10 RTP device 20 Reaction chamber
30 Wafer holding part 40 Heating part
T1 First peak temperature T2 Second peak temperature
T3 intermediate temperature

Claims (4)

A silicon wafer sliced from a silicon single crystal ingot grown by the Czochralski method is heated at a rate of 10 占 폚 / min to a first maximum attainable temperature in a range of 1325 占 폚 to 1400 占 폚 in an oxidizing gas atmosphere by using a rapid- Sec or higher and 250 ° C / sec or lower to maintain the first maximum temperature for 1 second or longer and 60 seconds or lower, and thereafter rapidly lowering the temperature at a cooling rate of 50 ° C / A step of performing a first heat treatment which is a heat treatment,
The silicon wafer subjected to the first heat treatment is heated at a rate of 1 ° C / minute or more to 5 ° C / minute or less up to the second maximum temperature in the range of 900 ° C to 1250 ° C in a non-oxidizing gas atmosphere using a vertical heat treatment apparatus And a second step of performing a second heat treatment in which the second maximum temperature is maintained for 1 minute to 120 minutes and then the temperature is lowered at a rate of 1 DEG C / min or more and 5 DEG C /
And a heat treatment step of heat-treating the silicon wafer. The method of heat-treating a silicon wafer according to claim 1, wherein the rate of temperature decrease in the first heat treatment is 120 ° C / second or more and 250 ° C / second or less. delete delete

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