KR101204924B1 - Internal voltage generating circuit - Google Patents

Abstract

Embodiments of the present invention relate to an internal voltage generation circuit, and a technique for generating a stable internal voltage corresponding to a level of a power supply voltage. The embodiment of the present invention detects the level of the substrate bias voltage and outputs a detection signal, an oscillator for outputting an oscillation signal according to the detection signal, and performing a pumping operation according to the oscillation signal to output the substrate bias voltage. And a pumping unit configured to clamp the pumping voltage supplied to the pumping node in response to the power supply voltage level during the pumping operation.

Description

Internal voltage generating circuit

Embodiments of the present invention relate to an internal voltage generation circuit, and more particularly to an internal voltage generation circuit supplied to an internal circuit of a semiconductor device.

In general, a semiconductor memory device receives power such as an external power supply (VDD) and a ground power supply (VSS) from the outside of a chip, and internally generates internal voltages such as a high voltage (VPP) and a substrate bias voltage (VBB) having a predetermined target value. Create and use as

In addition, the negative wordline scheme is a method of using negative voltages VBB and VBBW, which are lower than the ground voltage VSS, instead of the ground voltage VSS as the inactive voltage of the word line WL. Say

When the negative word line scheme is used, the time taken to store data is controlled by using the Vgs (gate-source-to-source) relationship of the transistor T to control the leakage current without increasing the threshold voltage of the transistor T. This has the advantage of preventing this growing problem.

At this time, the semiconductor memory device sets a target level of the internal voltage to detect whether the current internal voltage exceeds the target level, and controls the internal voltage to maintain a constant target level by pumping the internal voltage when the target voltage is not reached.

To this end, the semiconductor memory device includes an internal voltage generation circuit, and the internal voltage generation circuit includes a voltage sensing unit, an oscillation unit, and a voltage pumping unit.

Among the internal voltages of the semiconductor memory devices listed above, the substrate bias voltage VBB is mainly used as the bulk voltage of the NMOS transistor to reduce the leakage current.

In addition, the substrate bias voltage VBB may be applied to the gate terminal of the PMOS transistor to be used to overcome the threshold voltage of the PMOS transistor.

Such a technique is utilized in circuits such as sub word line drivers of semiconductor memory devices. As the level of the substrate bias voltage VBB is stable, the overall stability of the semiconductor memory device may be secured.

However, when the level of the power supply voltage VDD is increased, the capability of the voltage pumping unit driven by the power supply voltage VDD is increased. Accordingly, there is a problem that the voltage pumping unit performs an excessive pumping operation so that the level of the substrate bias voltage VBB changes.

That is, when the level of the power supply voltage VDD increases, the charge supplied during one pumping operation increases, and as the power supply voltage VDD increases, the level of the substrate bias voltage VBB becomes lower. .

1 is an operating waveform diagram illustrating a change in the substrate bias voltage VBB according to the level of the power supply voltage VDD.

Referring to the operation waveform diagram of FIG. 1, when the level of the power supply voltage VDD is high, the swing width of the substrate bias voltage VBB increases, so that the voltage level of the substrate bias voltage VBB becomes lower. Can be.

In order to suppress the level of the substrate bias voltage VBB from being lowered, the sensitivity of the voltage sensing unit should be increased to immediately transmit the level detection signal of the substrate bias voltage VBB to the oscillator to stop the output of the oscillator.

However, if the performance of the voltage sensing unit is increased, the standby current is increased and another problem occurs that the area is increased.

In addition, when the performance of the voltage sensing unit, that is, the response speed is increased, the substrate bias voltage VBB may exceed the target value, causing excessive pumping. In this case, the pump may be stopped, but the level of the substrate bias voltage VBB is increased by reacting the pump excessively to the noise portion flowing into the power supply terminal of the substrate bias voltage VBB to operate the pump even for a slight noise. Can be excessively low.

That is, if the response speed of the voltage detector is too slow, the substrate bias voltage VBB is lowered due to excessive pumping operation. On the other hand, if the response speed of the voltage sensing unit is too fast, the substrate bias voltage VBB may be lowered by reacting too sensitively to noise, thereby controlling the response speed of the voltage sensing unit to keep the substrate bias voltage VBB stable. Is very difficult.

In addition, there is a method of increasing the period of the oscillation part in order to prevent the level of the substrate bias voltage VBB from decreasing because the level of the power supply voltage VDD is increased. Even if the response speed of the voltage sensing unit is slow, it is a method of preventing excessive pumping by disabling the oscillator before generating an excessive pulse in the oscillator.

However, when the power supply voltage VDD is lowered, the cycle of the oscillation unit becomes longer and the charge supplied during one pumping operation decreases, which may cause a problem in supplying the necessary pumping current.

Embodiments of the present invention have the following features.

First, the embodiment of the present invention is characterized by limiting the pumping voltage by the clamp diode when the power supply voltage rises so that the average value of the substrate bias voltage can be kept constant even if the power supply voltage is increased.

Second, an embodiment of the present invention is characterized in that the peak-to-peak value of the substrate bias voltage is limited to a predetermined level when the power supply voltage rises to maintain the substrate bias voltage stably.

An internal voltage generation circuit according to an embodiment of the present invention, a voltage detector for detecting a level of the substrate bias voltage and outputting a detection signal; An oscillator for outputting an oscillation signal according to the detection signal and being driven by a core voltage level; And a pumping unit configured to output a substrate bias voltage by performing a pumping operation according to the oscillation signal, and to clamp the pumping voltage supplied to the pumping node according to the power supply voltage level during the pumping operation, and the pumping unit performs the pumping operation according to the oscillation signal. A substrate bias voltage generator configured to output a substrate bias voltage; And a clamping unit configured to clamp the pumping voltage supplied to the pumping node corresponding to the power supply voltage level during the pumping operation.

An embodiment of the present invention has the following effects.

First, the embodiment of the present invention is to limit the pumping voltage by the clamp diode when the power supply voltage rises so that the average value of the substrate bias voltage can be kept constant even if the power supply voltage is increased.

Secondly, the embodiment of the present invention limits the peak-to-peak value of the substrate bias voltage to a predetermined level when the power supply voltage rises, thereby stably maintaining the substrate bias voltage.

Third, the embodiment of the present invention provides an effect of improving the deterioration of refresh of the DRAM cell by maintaining a constant variation in the substrate bias voltage even when the power supply voltage increases.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1 is an operation waveform diagram showing a change in the substrate bias voltage VBB according to the power supply voltage VDD.
2 is a block diagram of an internal voltage generation circuit according to an embodiment of the present invention.
FIG. 3 is a detailed circuit diagram of the pumping part of FIG. 2. FIG.
4A and 4B are waveform diagrams comparing levels of the substrate bias voltage VBB in the prior art and the embodiment of the present invention.
FIG. 5 is a diagram comparing levels of substrate bias voltages according to a power supply voltage VDD in an embodiment of the present invention. FIG.
6 is a view comparing peak-to-peak values of substrate bias voltages according to a power supply voltage VDD in an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an internal voltage generation circuit according to an exemplary embodiment of the present invention.

The internal voltage generation circuit according to the embodiment of the present invention includes a voltage detector 100, an oscillator 200, a pumping unit 300 and an output rod unit 400.

Here, the voltage detector 100 detects the level of the substrate bias voltage VBB according to the reference voltage VREF and outputs the detection signal DET. The voltage detector 100 operates between a power supply voltage VDD level and a ground voltage VSS level.

The oscillator 200 outputs an oscillation signal OSC that toggles with a predetermined period in response to the detection signal DET of the voltage detector 100. The oscillator 200 is driven by the core voltage VCORE and the ground voltage VSS.

There are circuits that need to use an internal clock as well as an external clock in memory devices and IC chips. In particular, in a nonvolatile memory such as a flash memory, an internal clock is used without input of an external clock to a microcontroller, a pump circuit, or the like. An oscillator circuit is a circuit that generates this clock.

The basis of the circuit used as an oscillator is a ring oscillator that connects an odd number of inverters in series so that the output of the final stage is fed back to the input of the first inverter.

That is, the oscillator circuit periodically generates an output signal of high or low level depending on the combination of transistors. In addition, an oscillator circuit is formed by connecting a few driving units of an inverter structure composed of a complementary metal-oxide-semiconductor (CMOS).

In addition, the pumping unit 300 increases the level of the substrate bias voltage VBB by performing a charge pumping operation in response to the oscillation signal OSC. The pumping unit 300 operates between a power supply voltage VDD level and a ground voltage VSS level.

The output load unit 400 includes the capacitor C and the resistor R to control the output load of the substrate bias voltage VBB by the RC delay effect. Here, the capacitor C and the resistor R are connected in parallel between the substrate bias voltage VBB output terminal and the ground voltage terminal.

Referring to the operation of the internal voltage generation circuit according to an embodiment of the present invention based on the above configuration as follows.

First, when the power supply voltage VDD is applied, the voltage detector 100 compares the level of the substrate bias voltage VBB with the level of the reference voltage VREF and determines the level of the detection signal DET according to the comparison result.

For example, when the level of the substrate bias voltage VBB inputted to the feedback becomes higher than the level of the reference voltage VREF input to the voltage detector 100, the level of the detection signal DET is set to logic 'high'. And print out.

Similarly, when the level of the substrate bias voltage VBB becomes lower than the level of the reference voltage VREF input to the voltage detector 100, the level of the detection signal DET is shifted to a logic 'low' and output. do.

In this case, the reference voltage VREF is a voltage generated in a band gap circuit of the semiconductor device, and is a voltage that maintains a stable voltage level at all times regardless of variations in PVT (PROCESS, VOLTAGE, TEMPERATURE) of the semiconductor device.

The oscillator 200 outputs an oscillation signal OSC that toggles with a predetermined period in response to the level of the detection signal DET of the voltage detector 100.

In addition, the pumping unit 300 generates a substrate bias voltage VBB by performing a charge pumping operation in response to toggling of the oscillation signal OSC.

For example, when the detection signal DET level of the voltage detector 100 is logic 'low', the oscillation signal OSC output from the oscillator 200 does not oscillate at a predetermined period, but the logic 'low' or logic. Fixed to 'High'.

Therefore, the pumping unit 300 does not perform the charge pumping operation, and as a result, the level of the substrate bias voltage VBB decreases.

On the other hand, when the level of the detection signal DET of the voltage detector 100 is logic 'high', the oscillation signal OSC output from the oscillator 200 oscillates at a predetermined period.

Therefore, the pumping unit 300 performs a charge pumping operation, thereby raising the level of the substrate bias voltage VBB.

3 is a detailed circuit diagram illustrating the pumping unit 300 of FIG. 2.

The pumping unit 300 includes a clamping unit 310 and a substrate bias voltage generation unit 320.

Here, the clamping unit 310 includes a plurality of NMOS transistors N1 to N4.

NMOS transistors N1 and N2 are connected in series between the pumping nodes ND1 and ND2. NMOS transistors N3 and N4 are connected in series between the pumping nodes ND1 and ND2.

In addition, the NMOS transistors N1 and N2 include a diode device in which a gate terminal and a source terminal (or drain terminal) are commonly connected to the pumping node ND1. The NMOS transistors N3 and N4 are formed of diode devices in which a gate terminal and a drain terminal (or source terminal) are commonly connected to the pumping node ND2.

In addition, the substrate bias voltage generation unit 320 includes a plurality of NMOS transistors N5 and N6, MOS capacitors MC1 and MC2, a plurality of inverters IV1 to IV3, and a plurality of PMOS transistors P1 to P4.

NMOS transistors N5 and N6 are connected between pumping nodes ND1 and ND2. The NMOS transistor N5 has its gate terminal connected to the pumping node ND2, and the NMOS transistor N6 has its gate terminal connected to the pumping node ND1.

The MOS capacitors MC1 and MC2 may be PMOS capacitors. The MOS capacitor MC1 amplifies and outputs the oscillation signal OSC driven inverted by the inverter IV1. The MOS capacitor MC2 amplifies and outputs the oscillation signal OSC driven by the inverted inverters IV2 and IV3.

The PMOS transistors P1 and P2 are connected between the NMOS transistors N5 and N6 and the ground voltage terminal and are cross-coupled between the pumping nodes ND1 and ND2 and the nodes ND3 and ND4.

The PMOS transistors P3 and P4 are connected between the pumping nodes ND1 and ND2 and the ground voltage terminal, and a gate terminal thereof is connected to the ground voltage terminal. The PMOS transistors P3 and P4 are always turned on by applying a ground voltage through the gate terminal.

Referring to the operation of the pumping unit 300 having such a configuration as follows.

The clamping unit 310 is connected to both ends of the pumping nodes ND1 and ND2 to adjust the electric charge supplied during the pumping operation to an appropriate value.

The charge supplied in the pumping operation by the diode-type clamping part 310 is limited to a predetermined value.

That is, when the power supply voltage VDD is low, the clamping unit 310 does not operate. When the power supply voltage VDD is high, the clamping unit 310 operates.

Accordingly, the charge supplied during the pumping operation is limited to a specific value to prevent the level of the substrate bias voltage VBB from being lowered in the high power supply voltage VDD state.

On the other hand, when the PMOS transistors P3 and P4 are turned on, the ground voltage is supplied to the pumping nodes ND1 and ND2 so that the PMOS transistors P1 and P2 are turned on.

At this time, the oscillation signal OSC of the square wave pulse that toggles at a level between 0 V and the power supply voltage VDD is supplied from the oscillator 200.

When the oscillation signal OSC transitions from 0V to the power supply voltage VDD level, the potential of the pumping node ND2 is momentarily raised by the MOS capacitor MC2. On the other hand, the potential of the pumping node ND1 drops instantaneously by the MOS capacitor MC1.

At this time, the potential of the pumping node ND2 may rise to the power supply voltage VDD level, but the increase of the potential is limited by the forward diode turn-on operation of the junction-well of the PMOS transistor P2.

Similarly, although the potential of the pumping node ND1 may drop to −VDD, the drop of the potential is limited by the forward diode turn-on operation of the junction-well of the NMOS transistor N6.

Thereafter, while the oscillation signal OSC is maintained at the high level, the pumping node ND2 is discharged by the PMOS transistor P2 so that the potential gradually decreases. On the other hand, the pumping node ND1 gradually increases in potential as the charge transfer (from the output terminal of the substrate bias voltage VBB to the pumping node ND1) is generated by the NMOS transistor N5.

Next, the voltage difference between the pumping node ND1 and the pumping node ND2 gradually decreases to reach the threshold voltage Vt of the PMOS transistor P2 and the voltage drop of the pumping node ND2 stops.

In addition, when the voltage difference between the voltage of the pumping node ND1 and the pumping node ND2 reaches the threshold voltage Vt of the NMOS transistor N5, the NMOS transistor N5 is turned off to stop the voltage rise of the pumping node ND1. That is, the charge transfer operation by the NMOS transistor N5 is stopped.

Subsequently, when the oscillation signal OSC, which is a square wave pulse, transitions from the power supply voltage VDD level to 0 V, the potential of the pumping node ND2 is dropped momentarily, and the potential of the pumping node ND1 is raised instantaneously.

The charge transfer is generated by the NMOS transistor N6, and the above process is repeated. At this time, the discharge transistor is changed from the PMOS transistor P2 to the PMOS transistor P1. The charge transfer transistor is then changed from NMOS transistor N5 to NMOS transistor N6.

When the oscillation signal OSC transitions from 0V to the power supply voltage VDD level and then from the power supply voltage VDD to 0V level, the charge transfer phenomenon occurs alternately at the pumping nodes ND1 and ND2.

Accordingly, charge is discharged from the output terminal of the substrate bias voltage VBB to the ground voltage terminal, thereby gradually lowering the voltage of the substrate bias voltage VBB node to a negative value.

When the level of the power supply voltage VDD is increased, the charge that is transferred during one pumping is increased. That is, as the level of the power supply voltage VDD increases, more current can flow than when the NMOS transistor N5 or the NMOS transistor N6 is turned on, thereby increasing the charge transfer phenomenon.

Since the gate-source voltage that can be instantaneously applied to the NMOS transistor N5 and the NMOS transistor N6 is 2 × power supply voltage VDD, the charge transfer capacity increases as the power supply voltage VDD increases.

In the embodiment of the present invention, two series diodes are provided between the pumping nodes ND1 and ND2 in order to limit the moving charge in one pumping operation.

For example, this diode type NMOS transistor N1, N2 or NMOS transistors N3, N4 has a clamping voltage characteristic of about 2 x 0.7V = 1.4V.

Accordingly, the voltage difference between the pumping nodes ND1 and ND2 can be prevented from spreading beyond ± 1.4V.

That is, even if the power supply voltage VDD increases, the voltage difference between the pumping nodes ND1 and ND2 is fixed to the turn-on voltage of up to two diodes. Accordingly, the phenomenon in which the level of the substrate bias voltage VBB is lowered due to excessive transfer of charges can be prevented, so that the substrate bias voltage VBB can be stably maintained.

In the embodiment of the present invention, the NMOS transistor is formed as a diode type in the clamping unit 310 as an example, but the embodiment of the present invention is not limited to this, but the diode of the clamping unit 310 is a PMOS transistor type or other It may be made of a diode element.

The number of connections of the diode elements connected in series in the clamping unit 310 may be appropriately selected in consideration of the threshold voltage value. That is, in the exemplary embodiment of the present invention, two NMOS transistors N1 and N2 (or NMOS transistors N3 and N4) of the clamping unit 310 are described as an example. However, three diode elements instead of two according to the threshold voltage are described. It can be connected in series or more.

4A and 4B are waveform diagrams comparing levels of the substrate bias voltage VBB with time according to the prior art and the exemplary embodiment of the present invention.

FIG. 4A illustrates a waveform in which the level of the substrate bias voltage VBB is pumped by changing the level of the power supply voltage VDD in the prior art, and FIG. 4B illustrates a change in the level of the power supply voltage VDD in the embodiment of the present invention. The level of the substrate bias voltage VBB represents a waveform to be pumped.

(A), (B), and (C) in FIG. 4A show prior art substrate bias voltage (VBB) levels at 1.3 V, 1.6 V, and 2.0 V, respectively, and (D) and (E) in FIG. 4B. (F) shows the substrate bias voltage (VBB) level according to the embodiment of the present invention at 1.3V, 1.6V, 2.0V, respectively.

The load of the substrate bias voltage VBB used in the simulations of FIGS. 4A and 4B is modeled as a series resistor connected to the ground voltage terminal so that a constant current is continuously discharged.

As can be seen by comparing the waveforms of FIGS. 4A and 4B, as the level of the power supply voltage VDD increases, charges that move during one pumping operation increase to gradually increase the variation of the substrate bias voltage VBB. It can be seen that.

As shown in the simulation result of FIG. 4B, this phenomenon is greatly improved in the embodiment of the present invention, and it can be seen that the fluctuation of the substrate bias voltage VBB does not increase much even when the power supply voltage VDD is increased.

5 is a view comparing the level of the substrate bias voltage (VBB) according to the change in the power supply voltage (VDD) in the embodiment of the present invention.

As shown in FIG. 5, it can be seen that the embodiment of the present invention does not increase the median value of the substrate bias voltage VBB according to the change of the power supply voltage VDD.

FIG. 6 is a view comparing peak-to-peak values of substrate bias voltages according to a change in power supply voltage VDD according to an exemplary embodiment of the present invention.

As shown in FIG. 6, it can be seen that the embodiment of the present invention does not increase the peak-to-peak of the substrate bias voltage VBB according to the change of the power supply voltage VDD. have.

Claims (9)

A voltage detector for detecting a level of the substrate bias voltage and outputting a detection signal;
An oscillator which outputs an oscillation signal according to the detection signal and is driven by a core voltage level; And
A pumping unit configured to output the substrate bias voltage by performing a pumping operation according to the oscillation signal, and to clamp a pumping voltage supplied to a pumping node in response to a power supply voltage level during the pumping operation;
The pumping unit
A substrate bias voltage generation unit configured to output the substrate bias voltage by performing a pumping operation according to the oscillation signal; And
And a clamping unit configured to clamp the pumping voltage supplied to the pumping node in response to a power supply voltage level during the pumping operation. delete delete Claim 4 has been abandoned due to the setting registration fee. The method of claim 1, wherein the clamping portion
And a plurality of diode elements connected in series with both ends of the pumping node. Claim 5 was abandoned upon payment of a set-up fee. The internal voltage generation circuit of claim 4, wherein the voltage difference across the pumping node is fixed to the turn-on voltage of the diode element when the level of the power supply voltage increases. Claim 6 has been abandoned due to the setting registration fee. The method of claim 1, wherein the clamping portion
And a plurality of first NMOS transistors of a diode type connected in series with both ends of the pumping node, the gate terminals being commonly connected with the source terminals. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, wherein the clamping portion
And a plurality of second NMOS transistors of a diode type connected in series with both ends of the pumping node, the gate terminals of which are commonly connected to the drain terminals. Claim 8 was abandoned when the registration fee was paid. 8. The internal voltage generation circuit of claim 7, wherein the plurality of first NMOS transistors are connected in parallel with the plurality of second NMOS transistors. Claim 9 has been abandoned due to the setting registration fee. The internal voltage generation circuit of claim 1, wherein the clamping unit operates only when the power supply voltage is higher than a predetermined voltage.

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