KR101182085B1 - Semiconductor memory device - Google Patents

Abstract

An object of the present invention is to obtain a semiconductor memory device which can be manufactured by a MOS process and which can realize stable operation. The storage transistor has an impurity diffusion region, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to the gate line, and the impurity diffusion region is connected to the source line, respectively. The storage transistor stores data " 1 " and data " 0 ", respectively, by generating a state where holes are accumulated in a charge storage node and a state where holes are not accumulated. The access transistor has an impurity diffusion region, a channel formation region, a gate oxide film and a gate electrode. The impurity diffusion region is connected to the bit line.

Memory cell, storage transistor, access transistor, impurity diffusion region, channel formation region, word line, word line, bit line, source line

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which memory cells are formed by two transistors.

Stacked and trenched memory capacitors and DRAMs containing switching MOS transistors have been mainstream as high density semiconductor memory devices. However, since the miniaturization of memory capacitors is difficult, new miniaturization of DRAM is also reaching its limit. . Under such a situation, instead of using the stack-type or trench-type memory capacitors described above, a semiconductor memory device of a type in which a memory cell is constituted by only one memory transistor has been developed by using a switching transistor as a capacitor element. . For example, the following non-patent document 1 discloses a semiconductor memory device which accumulates electric charges in a floating body region of an SOI transistor.

[Non-Patent Document 1] DIGEST OF TECHNICAL PAPERS pp152-153, "9.1 Memory Design Using One-Transistor Gain Cell on SOI", Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi, 2002 IEEE International Solid-State Circuits Conference, February 5, 2002

Similarly to Non-Patent Document 1, another example of a semiconductor memory device in which a memory cell is composed of only one transistor is disclosed in Patent Document 1 below.

Patent Document 1: Japanese Patent Application Laid-Open No. 2002-260381

However, according to the semiconductor memory device disclosed in the non-patent document 1, it is necessary to form a polysilicon pillar having a special structure, which leads to a problem that the process becomes complicated, resulting in an increase in manufacturing cost.

Further, in the semiconductor memory device disclosed in Patent Document 1, by applying a high voltage between the source and the drain, impact ionization occurs in the vicinity of the drain, and the holes generated thereby are accumulated in the body, whereby data " 1 " State) is written. Further, by applying a negative voltage to the source and discharging the hole from the body, data "0" (state of high threshold voltage) is written. However, there is a limit to the generation of holes due to impact ionization, and there is a problem in that the difference between the threshold voltages cannot be increased in the state of data "1" and the state of data "0". In addition, since the control of reading and writing requires a very wide variety of power supply voltages, and in addition, a driver for supplying three voltages is required to control word lines and bit lines. There is also a problem that the generation is complicated. In the case where the memory cell is composed of only one memory transistor, the potential of the body may be kept at a very low state when the power is turned on. In such a situation, the current due to impact ionization does not flow, and the data " 1 " "There is a literary system that I cannot fill out. In order to avoid such a situation, there is a problem that an extra procedure of initializing all memory cells is required once more, and in addition, a power supply voltage higher than normal operation needs to be generated for initialization.

<Start of invention>

The present invention has been made to solve such a problem, and can be manufactured by a general-purpose M0S process without requiring a special process, and furthermore, the threshold voltage in the state of data "1" and the state of data "0". It is an object of the present invention to obtain a semiconductor memory device capable of realizing a stable operation by making the difference greatly.

A first aspect of the semiconductor memory device according to the present invention includes a plurality of memory cells arranged in a matrix, a gate line and a word line shared by the plurality of memory cells arranged in a first direction, and a second direction. A bit line and a source line shared by the plurality of memory cells arranged, each of the plurality of memory cells comprising: first and second impurity diffusion regions facing each other with a first channel formation region therebetween; A storage transistor including a first gate electrode formed above the first channel formation region, a charge accumulation node formed below the first channel formation region, and connected in series with the storage transistor, wherein the first impurity diffusion A third impurity diffusion region facing the first impurity diffusion region with a region interposed therebetween and a second channel formation region, and the second channel formation region An access transistor comprising a second gate electrode formed above the second impurity diffusion region to the source line, the third impurity diffusion region to the bit line, and the first gate electrode to the gate line And the second gate electrode is connected to the word line, respectively, and the potential of the first impurity diffusion region is switched to a constant potential or a floating state by on / off of the access transistor, thereby providing The potential is controlled, thereby setting the threshold voltage of the storage transistor to a high level or a low level.

According to the first aspect of the semiconductor memory device according to the present invention, manufacture can be performed without requiring a special process, and furthermore, stable operation can be realized.

A second aspect of the semiconductor memory device according to the present invention has a main surface on which a first element isolation insulating film extending in a first direction is formed, and an element formation region extending along the first direction is formed in the first element isolation insulating film. A substrate defined by the substrate, a bit line extending along the first direction, a plurality of gate lines, a plurality of word lines, and a plurality of source lines, all extending along a second direction, within the element formation region. Two memories including a plurality of memory cells arranged and arranged along the first direction, wherein the bit lines are shared by the plurality of memory cells and adjacent to each other along the first direction among the plurality of memory cells; One source line of the plurality of source lines is shared by the cell.

According to the second aspect of the semiconductor memory device according to the present invention, it is possible to reduce the area of the memory cell array region.

The objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

1 is a block diagram showing an overall configuration of a semiconductor memory device according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram showing part of the memory array shown in FIG.

3 is a sectional view showing a structure of a memory cell.

4 is an equivalent circuit diagram of a memory cell.

5 is a timing chart for explaining the operation of the semiconductor memory device.

FIG. 6 is a diagram showing a result of simulating a change in potential of a storage node when the gate line is raised from a low level to a high level. FIG.

FIG. 7 is a diagram showing a result of simulating a change in potential of a storage node when the gate line is raised from a low level to a high level. FIG.

FIG. 8 is a circuit diagram showing the configuration of a sense amplifier circuit included in the sense amplifier shown in FIG. 1. FIG.

Fig. 9 is a circuit diagram showing the structure of a voltage application circuit to a bit line in a data write operation.

FIG. 10 is a block diagram showing the configuration of an internal power generation circuit for generating the negative power supply potential shown in FIG. 8; FIG.

FIG. 11 is a circuit diagram showing a configuration of an internal power generation circuit for generating each high level of the word line and bit line shown in FIG.

FIG. 12 is a circuit diagram corresponding to FIG. 8 and showing a configuration of a sense amplifier circuit included in a sense amplifier. FIG.

FIG. 13 is a circuit diagram corresponding to FIG. 9 and showing a configuration of a voltage application circuit to a bit line. FIG.

FIG. 14 is a timing chart for explaining the operation of the semiconductor memory device in correspondence with FIG.

FIG. 15 is a sectional view corresponding to FIG. 3 and showing the structure of the memory cell. FIG.

Fig. 16 is a top view showing the top layout of a semiconductor memory device according to the fourth embodiment of the present invention.

Fig. 17 is a top view showing the top layout of a semiconductor memory device according to the fourth embodiment of the present invention.

Fig. 18 is a top view showing a top layout of a semiconductor memory device according to the fourth embodiment of the present invention.

19 is an equivalent circuit diagram corresponding to the layout shown in FIG.

20 is a sectional view of a sectional structure relating to a position along a line XX-XX shown in FIG. 16.

FIG. 21 is a sectional view of a sectional structure relating to a position along a line XXI-XXI shown in FIG. 16; FIG.

FIG. 22 is a cross-sectional view showing a sectional structure relating to a position along a line XXII-XXII shown in FIG. 16. FIG.

Fig. 23 is a top view schematically showing the structure of an IC chip in which a semiconductor memory and a logic circuit are configured as one chip.

FIG. 24 is a diagram schematically showing the structure of a basic array of the memory cell array regions shown in FIG.

FIG. 25 is a cross-sectional view illustrating the IC chip manufacturing method illustrated in FIG. 23 in a process order. FIG.

FIG. 26 is a cross-sectional view illustrating a method of manufacturing the IC chip illustrated in FIG. 23 in a process order. FIG.

FIG. 27 is a sectional view of a method of manufacturing the IC chip illustrated in FIG. 23, in order of process; FIG.

FIG. 28 is a cross-sectional view illustrating a method of manufacturing the IC chip illustrated in FIG. 23 in a process order. FIG.

FIG. 29 is a cross-sectional view illustrating a method of manufacturing the IC chip illustrated in FIG. 23 in a process order. FIG.

30 is a cross-sectional view illustrating a method of manufacturing the IC chip illustrated in FIG. 23 in a process order.

FIG. 31 is a cross-sectional view showing a modification of the structure shown in FIG. 30. FIG.

<Code description>

1: semiconductor memory

8: memory array

9: sense amplifier

11: silicon substrate

12: buried oxide layer

13: silicon layer

14: SOI substrate

20, 22, 24, 58, 60, 62: impurity diffusion region

16, 18, 54, 56: gate oxide film

17, 19, 55, 57: gate electrode

21, 23a, 59, 61a: channel forming region

23b, 61b: charge accumulation node

50: P-type silicon substrate

51: N well

52: P well

STr: storage transistor

ATr: access transistor

SN: storage node

MC, MCH, MCL: Memory Cells

BL: bit line

RBLH, RBLL: Reference Bit Line

SL: source line

GL: gate line

WL: word line

Tr1, Tr2: Transistor

<The best form to perform invention>

(Embodiment 1)

1 is a block diagram showing the overall configuration of a semiconductor memory device 1 according to Embodiment 1 of the present invention. Referring to FIG. 1, the semiconductor memory device 1 includes an address decoder 2, an input / output circuit 3, an address buffer 4, a clock buffer 5, a control signal buffer 6, and a control circuit 7. , A memory array 8, a sense amplifier 9, and a power supply circuit 10.

FIG. 2 is a circuit diagram showing part of the memory array 8 shown in FIG. Referring to FIG. 2, a plurality of memory cells MC are arranged in a matrix in the memory array 8. In the memory array 8, a plurality of gate lines GL and a plurality of word lines WL extending along the row direction, a plurality of bit lines BL and a plurality of source lines SL extending along the column direction are disposed. The gate line GL and the word line WL are shared by the plurality of memory cells MC arranged in the row direction, and the bit line BL and the source line SL are shared by the plurality of memory cells MC arranged in the column direction. The memory cell MC is disposed at the intersection of the gate line GL and the word line WL with the bit line BL and the source line SL.

Referring to Fig. 1, the address decoder 2 has a row address decoder and a column address decoder. The row address decoder selects and drives one word line WL and a gate line GL, respectively, from among the plurality of word lines WL and the plurality of gate lines GL based on the row address signal supplied from the address buffer 4. The column address decoder selects and drives one bit line BL from among the plurality of bit lines BL based on the column address signal supplied from the address buffer 4.

The sense amplifier 9 has a plurality of sense amplifier circuits formed for each column of the memory array 8. The configuration and operation of the sense amplifier circuit will be described later.

In the data output operation, the input / output circuit 3 outputs the output of the sense amplifier circuit selected by the column address decoder to the outside of the semiconductor memory device 1 as output data. In the data input operation, the input / output circuit 3 amplifies the input data supplied from the outside of the semiconductor memory device 1 and then inputs it to the memory cell MC via the bit line BL selected by the column address decoder. Write the data.

The address buffer 4, the clock buffer 5, and the control signal buffer 6 respectively store an address signal, a clock signal, and a control signal supplied from the outside of the semiconductor memory device 1 to the control circuit 7. To pass.

The power supply circuit 10 generates a voltage (such as a voltage applied to the word line WL, the bit line BL, etc.) necessary for the operation of the semiconductor memory device 1 such as reading or writing, and supplies the same to the memory array 8.

3 is a cross-sectional view showing the structure of the memory cell MC, and FIG. 4 is an equivalent circuit diagram of the memory cell MC. Referring to FIG. 4, the memory cell MC has a structure in which a storage transistor STr having a storage node SN and an access transistor ATr are connected in series through a node PN. That is, one memory cell MC is composed of two transistors.

Referring to FIG. 3, the SOI substrate 14 has a structure in which a silicon substrate 11, a buried oxide film layer 12, and a silicon layer 13 are stacked in this order. The storage transistor STr has N-type impurity diffusion regions 22 and 24, a channel formation region 23a, a charge accumulation node 23b, a gate oxide film 18, and a gate electrode 19. The impurity diffusion regions 22 and 24 extend from the top surface of the silicon layer 13 to the top surface of the buried oxide film layer 12 and intersect the channel formation region 23a defined in the top surface of the silicon layer 13. Put on, they are facing each other. The impurity diffusion region 22 corresponds to the node PN shown in FIG. 4. The gate oxide film 18 is formed on the channel formation region 23a, and the gate electrode 19 is formed on the gate oxide film 18. The charge accumulation node 23b corresponding to the storage node SN shown in FIG. 4 is formed below the channel formation region 23a. The charge accumulation node 23b is electrically separated from other adjacent memory cells MC by the element isolation insulating film 15. That is, the charge accumulation node 23b is configured by the floating body of the SO transistor. The gate electrode 19 is connected to the gate line GL, and the impurity diffusion region 24 is connected to the source line SL.

The storage transistor STr generates a state where holes are accumulated in the charge accumulation node 23b (a state in which the threshold voltage of the storage transistor STr is low) and a state in which holes are not accumulated (a state in which the threshold voltage is high). , Data "1" and data "0" are stored, respectively.

The access transistor ATr has N-type impurity diffusion regions 20 and 22, a channel formation region 21, a gate oxide film 16, and a gate electrode 17. The impurity diffusion region 20 extends from the top surface of the silicon layer 13 to the top surface of the buried oxide film layer 12, with the channel formation region 21 defined within the top surface of the silicon layer 13 interposed therebetween. It faces the impurity diffusion region 22. The gate oxide film 16 is formed on the channel formation region 21, and the gate electrode 17 is formed on the gate oxide film 16. The gate electrode 17 is connected to the word line WL, and the impurity diffusion region 20 is connected to the bit line BL.

5 is a timing chart for explaining the operation of the semiconductor memory device 1. Eight operation modes exist in total, and it demonstrates sequentially below. In addition, the power source potential VDD is supplied to the source line SL.

(1) Write operation (0W) of data "0"

With bit line BL set to low level GND, word line WL is raised from low level GND to high level (1 / 2VDD), and gate line GL is raised from high level (VDD) to low level (GND). Decreases to). As a result, the node PN is lowered from the high level VDD to the low level GND, and the storage node SN is at the high level VDD due to gate coupling (capacity coupling occurring between the gate and the body). To the low level GND. As a result, a state (data "0") in which no holes are accumulated in the storage node SN is generated.

Next, while maintaining the bit line BL at the low level, the gate line GL is raised from the low level to the high level. At this time, since the bit line BL is at the low level and the word line WL is at the high level, the access transistor ATr is on and the node PN is kept at the low level. Therefore, when the potential of the gate line GL rises slightly and a channel is formed in the storage transistor STr, the gate coupling is prevented by the channel (channel block), so that the potential of the storage node SN is no longer increased even when the potential of the gate line GL rises. Does not rise. That is, the holes supplied from the source line SL to the node PN through the storage transistor STr are discharged to the bit line BL through the access transistor ATr, so that the state where no holes are accumulated in the storage node SN is maintained (data "0"). do.

Thereafter, by lowering the word line WL from the high level to the low level, the access transistor ATr is turned off and the node PN rises from the low level to the high level.

(2) Reading operation of data "0" (0R)

The access transistor ATr is turned on by setting the bit line BL to the low level and the word line WL to the high level. In this state, the gate line GL is set to high level. In a state where holes are not accumulated in the storage node SN (data "0"), the threshold voltage of the storage transistor STr is high, so that the current flowing from the source line SL to the bit line BL through the storage transistor STr and the access transistor ATr. The amount is small.

The potential of the node PN decreases slightly by turning on the access transistor ATr. However, if the word transistor WL is turned low and the access transistor ATr is turned off after that, the potential of the node PN rises again to a high level.

(3) Holding operation of data "0" (0H)

The bit line BL is raised from the low level to the high level (1 / 2VDD). As a result, even when the word line WL is at a high level, since the potential difference does not occur between the bit line BL and the word line WL, the access transistor ATr is not turned on. Therefore, no current flows from the source line SL to the bit line BL, so that data "0" is maintained.

(4) Refresh operation (0Ref) of data "0"

The execution of the refresh operation requires twice as long as a normal command such as writing or reading. First, the above read operation is performed on the memory cell MC to be refreshed, and the resultant data "0" is stored in the write buffer included in the input / output circuit 3 shown in FIG. Thereafter, the above write operation is executed, and the same data as the data stored in the write buffer (that is, data "0") is written into the memory cell MC to be refreshed.

(5) Write operation (1W) of data "1"

With the bit line BL set at the low level, the word line WL is raised from the low level to the high level, and the gate line GL is lowered from the high level to the low level. As a result, the node PN is lowered from the high level to the low level, and the storage node SN is lowered from the high level to the low level by gate coupling. As a result, a state (data "0") in which no holes are accumulated in the storage node SN is generated. The operation up to this point is the same as the writing operation of the data "0".

Next, after raising the bit line BL from the low level to the high level, the gate line GL is raised from the low level to the high level. At this time, since the bit line BL and the word line WL are both at a high level, the access transistor ATr is turned off and the potential of the node PN is in a floating state. In this state, even if the gate line GL rises, no channel is formed in the storage transistor STr, and thus the channel block is not formed. Therefore, when the potential of the gate line GL rises, the potential of the storage node SN also rises by gate coupling. That is, the holes supplied from the source line SL to the storage node SN are accumulated in the storage node SN without being discharged to the bit line BL, so that the state of data "1" is generated. In addition, the potential of the node PN in the floating state rises from the low level to the high level in conjunction with the increase of the potential of the storage node SN.

(6) Reading operation (1R) of data "1"

The access transistor ATr is turned on by setting the bit line BL to the low level and the word line WL to the high level. In this state, the gate line GL is set to high level. In a state where holes are stored in the storage node SN (data "1"), the threshold voltage of the storage transistor STr is low, and therefore, the current flowing from the source line SL to the bit line BL through the storage transistor STr and the access transistor ATr is used. The amount is large.

(7) Holding operation (1H) of data "1"

Similarly to the operation of holding data "0", the bit line BL is raised from the low level to the high level. As a result, even when the word line WL is at a high level, since the potential difference does not occur between the bit line BL and the word line WL, the access transistor ATr is not turned on. Therefore, no current flows from the source line SL to the bit line BL, so that data " 1 " is maintained.

(8) Refresh operation (1Ref) of data "1"

Similar to the refresh operation of the data "0", first, the above-described read operation is performed on the memory cell MC to be refreshed, and the input and output circuit 3 shown in FIG. 1 includes the data "1" obtained as a result. Save to write buffer. Thereafter, the above write operation is executed, and the same data as the data stored in the write buffer (that is, data "1") is written into the memory cell MC to be refreshed.

6 and 7 show the results of simulating the change in the potential of the storage node SN when the gate line GL is raised from the low level (0V) to the high level (1.2V) in the write operation. FIG. 6 corresponds to the write operation of data "0", and FIG. 7 corresponds to the write operation of data "1". Regarding X (μm) in the horizontal axis, the vicinity where X is zero corresponds to the body region of the storage transistor STr (the charge accumulation node 23b shown in FIG. 3, that is, the storage node SN), and the region where X is negative is the storage transistor. The region corresponding to the source region of the STr (the impurity diffusion region 22 shown in FIG. 3, that is, the node PN), and the region where X is positive is the drain region of the storage transistor STr (the impurity diffusion region 24 shown in FIG. 3). Corresponds to In addition, the channel length of the storage transistor STr is 0.1 mu m. Potential (V) of the vertical axis is a potential near the deepest part of each region.

Referring to FIG. 6, in the write operation of data "0", as a result of turning on the access transistor ATr, the potential of the source region of the storage transistor STr is fixed to 0V. However, since the built-in potential is added, it is fixed at 0.53V instead of 0V in FIG. In this case, even when the gate line GL is raised from the low level (0V) to the high level (1.2V), it can be seen that the potential of the body region of the storage transistor STr only rises from 0V to about 0.2V.

On the other hand, with reference to Fig. 7, in the write operation of data " 1 ", as a result of the access transistor ATr being turned off, the potential of the source region of the storage transistor STr is in a floating state. In this case, when the gate line GL is raised from the low level (0V) to the high level (1.2V), it can be seen that the potential of the body region of the storage transistor STr is greatly increased from 0V to about 0.7V. In addition, it is understood that the potential of the source region of the storage transistor STr also increases from 0.4V to 1.2V in conjunction with the increase of the potential of the body region.

FIG. 8 is a circuit diagram showing the configuration of a sense amplifier circuit included in the sense amplifier 9 shown in FIG. 1. In the memory array 8 shown in Fig. 1, memory cells MCH and MCL are formed in addition to the normal memory cell MC having the storage transistor STr and the access transistor ATr. The memory cell MCH has a storage transistor STrH whose threshold voltage is set to a low level by writing data "1" at the time of a write operation, and an access transistor ATr connected in series thereto. The memory cell MCL has a storage transistor STrL in which a threshold voltage is set to a high level by data “0” being always written during a write operation, and an access transistor ATr connected in series thereto. The memory cell MCH is connected to the reference bit line RBLH, and the memory cell MCL is connected to the reference bit line RBLL.

The memory cells MC, MCH, and MCL are all connected to a positive power supply potential VDD (for example, 1.2V). The memory cells MC, MCH, and MCL are all connected to the negative power supply potential VBB (-VDD, for example, -1.2V) through the transistors Tr1 and Tr2. For example, between the power supply potential VDD and the power supply potential VBB, the storage transistor STr, the access transistor ATr, the transistor Tr1, and the transistor Tr2 are connected in series from the power supply potential VDD side in sequence. The transistor Tr1 has a drain and a gate connected to each other, and constitutes a so-called threshold connection. The same applies to the transistor Tr2. The transistors Tr1 and Tr2 are arranged for the purpose of setting each of the read voltages of the bit line BL and the reference bit lines RBLH and RBLL to around 0V.

In addition, the memory cell circuit includes a differential amplifier circuit having two pairs of parallel inputs, and the potential Vblh of the reference bit line RBLH and the potential Vbll of the reference bit line RBLL are input to one parallel input. The potential Vbl of the bit line BL is input to the parallel input. Since the storage transistor STrH has a low threshold voltage and the storage transistor STrL has a high threshold voltage, it is relatively Vblh> Vbll. In addition, when the memory cell MC stores data "0", that is, when the threshold voltage of the storage transistor STr is at a high level, Vbl = Vbll, and conversely, the memory cell MC stores the data "1". In the case where the threshold voltage of the storage transistor STr is at the low level, Vbl = Vblh. In the differential amplifier circuit, Vblh, Vbll and Vbl are compared, and when Vbl = Vbll, a high level signal is output from the differential amplifier circuit, and when Vbl = Vblh, a low level signal is output from the differential amplifier circuit. That is, when the threshold voltage of the storage transistor STr is at a high level, a high level signal is output from the differential amplifier circuit. On the other hand, when the threshold voltage of the storage transistor STr is at a low level, a signal of a low level is transmitted from the differential amplifier circuit. Is output.

With this configuration, the data stored in the memory cell MC can be detected without error by the sense amplifier circuit.

9 is a circuit diagram showing the configuration of a voltage application circuit (write circuit) to the bit line BL in the data write operation. As shown in Fig. 5, it is necessary to set the bit line BL to a low level when writing data "0", and to set the bit line BL to a high level when writing data "1". Referring to Fig. 9, when the write permission signal WE is at a high level, GND (0V) is applied to the bit line BL when the write data WD is "0", and a bit line when the write data WD is "1". VBL (0.6V) is applied to BL. In the data read operation, as a result of the write permission signal WE being at a low level, the output of the voltage application circuit is in a high impedance state.

By such a configuration, the voltage application circuit can reliably change the potential of the bit line BL in accordance with the write data WD, thereby preventing the wrong data from being written into the memory cell MC.

FIG. 10 is a block diagram showing a configuration of an internal power generation circuit for generating the negative power supply potential VBB (for example, -1.2 V) shown in FIG. The internal power generation circuit shown in FIG. 10 is a part of the power supply circuit 10 shown in FIG. The detector 80 compares the reference voltage of −1.2 V with the output voltage VBB of the charge pump 82, and based on the detection result of the detector 80, the ring oscillator 81 generates a pulse. Control the charge pump (82).

FIG. 11 is a circuit diagram showing the configuration of an internal power supply generating circuit (step-down circuit) for generating each high level (1 / 2VDD) of the word line WL and bit line BL shown in FIG. The internal power generation circuit shown in FIG. 11 is a part of the power supply circuit 10 shown in FIG. 1 / 2VDD obtained by dividing the power supply potential VDD by the transistors 90 and 91 is input to the error amplifier 92 as a reference voltage. A driver transistor 93 composed of a PMOS transistor is connected to the output of the error amplifier 92, and 1 / 2VDD is output from the driver transistor 93, and this 1 / 2VDD is negative feedback to the error amplifier 92. It is.

As described above, according to the semiconductor memory device 1 according to the first embodiment, since the memory cell MC can be configured by the storage transistor STr and the access transistor ATr, the memory capacitor required in the conventional DRAM becomes unnecessary. In addition, the dimensions (layout size and shape) of the storage transistor STr and the access transistor ATr are the same as those of the normal NMOS transistor, and do not require a special structure. Therefore, the number of manufacturing steps and the required number of photomasks can be reduced, and the manufacturing cost can be reduced and the chip area can be reduced.

In addition, since the semiconductor memory device 1 can be manufactured by a general-purpose MOS process without requiring a special process, the manufacturing process is simplified compared with the semiconductor memory device disclosed in the non-patent document 1 above. And reduction of manufacturing cost can be aimed at.

In addition, since the threshold voltage of the storage transistor STr can be significantly different in the state of storing the data "1" and the state of storing the data "0", compared with the semiconductor memory device disclosed in Patent Document 1 above. This makes it possible to realize stable operation.

In addition, since the storage transistor STr and the access transistor ATr are constituted by the SOI transistor and the parasitic capacitance is small, the operation speed and the power consumption can be reduced as compared with the case of using a bulk substrate. In addition, since the storage node SN is electrically isolated from the access transistor ATr and the like, the resistance to noise is high. In addition, since the storage node SN is largely surrounded by the element isolation insulating film 15, the storage node SN has a large effect due to the gate coupling, and the storage node STr in the state of data " 1 " The effect of increasing the difference of the threshold voltages is also obtained.

(Embodiment 2)

FIG. 12 is a circuit diagram corresponding to FIG. 8 showing the configuration of a sense amplifier circuit included in the sense amplifier 9. The overall configuration of the semiconductor memory device 1 according to the second embodiment and the configuration of the memory cell MC are the same as in the first embodiment. With reference to FIG. 12, the storage transistor STr, the access transistor ATr, the transistor Tr1, and the transistor Tr2 are connected in series between the power supply potential VDD and the ground potential GND sequentially from the power supply potential VDD side. The same applies to the storage transistors STrH and STrL. Each gate of the transistors Tr1 and Tr2 is connected to the drain of the transistor Tr1 in common and constitutes a so-called threshold connection.

FIG. 13 is a circuit diagram corresponding to FIG. 9 showing the configuration of a voltage application circuit to the bit line BL. Instead of VBL (0.6V) in FIG. 9, VDD (1.2V) is adopted, which is different from the first embodiment.

FIG. 14 is a timing chart for explaining the operation of the semiconductor memory device 1 in correspondence with FIG. 5. In FIG. 5, the high level of each of the word line WL and the bit line BL is 1 / 2VDD, whereas the VDD in FIG. 14 differs from the first embodiment.

As described above, according to the semiconductor memory device 1 according to the second embodiment, since the use of negative power supply potential VBB (-1.2 V) can be avoided, the internal voltage generation circuit shown in FIG. 10 becomes unnecessary. In addition, since the high levels of the word line WL and the bit line BL become VDD instead of 1 / 2VDD, the internal voltage generation circuit shown in FIG. 11 is also unnecessary. Therefore, as compared with the first embodiment, it is possible to reduce the manufacturing cost and reduce the chip area.

In the configuration shown in FIG. 8, wiring connection between the gate and drain is required for each of the transistors Tr1 and Tr2. However, in the configuration shown in FIG. 12, the wiring connection between the gate and drain is not necessary. Transistors Tr1 and Tr2 can be configured by transistors of the same shape. Therefore, since variations in the characteristics of the memory cell transistors and transistors Tr1 and Tr2 due to process variations can be suppressed, more stable read operation can be realized.

(Embodiment 3)

FIG. 15 is a cross-sectional view showing the structure of the memory cell MC corresponding to FIG. 3. The overall configuration of the semiconductor memory device 1 according to the third embodiment is the same as that of the first and second embodiments. In the first embodiment, the storage transistor STr and the access transistor ATr are formed by using the SOI substrate 14, but in the third embodiment, the storage transistor STr and the access transistor ATr are different from the first embodiment in that the bulk transistor is used.

Referring to FIG. 15, an N well 51 is formed on the P-type silicon substrate 50, and a P well 52 is formed on the N well 51. The P well 52 is electrically separated from the P-type silicon substrate 50 by the N well 51. Adjacent memory cells MC are electrically separated from each other by STI (Shallow Trench Isolation) 53 extending from the upper surface of the P well 52 to the upper surface of the N well 51. For this reason, it is not necessary to enlarge the separation width of STI 53, and the increase of a chip area is avoided.

The storage transistor STr has N-type impurity diffusion regions 60 and 62, a channel formation region 61a, a charge accumulation node 61b, a gate oxide film 56, and a gate electrode 57. The impurity diffusion regions 60 and 62 oppose each other with the channel formation region 61a defined in the upper surface of the P well 52 interposed therebetween. The gate oxide film 56 is formed on the channel formation region 61a, and the gate electrode 57 is formed on the gate oxide film 56. The charge accumulation node 61b is formed below the channel formation region 61a. The charge accumulation node 61b is electrically separated from other adjacent memory cells MC by the STI 53. The gate electrode 57 is connected to the gate line GL, and the impurity diffusion region 62 is connected to the source line SL.

The access transistor ATr has N-type impurity diffusion regions 58 and 60, a channel formation region 59, a gate oxide film 54, and a gate electrode 55. The impurity diffusion region 58 opposes the impurity diffusion region 60 with the channel formation region 59 defined in the upper surface of the P well 52 interposed therebetween. The gate oxide film 54 is formed on the channel formation region 59, and the gate electrode 55 is formed on the gate oxide film 54. The gate electrode 55 is connected to the word line WL, and the impurity diffusion region 58 is connected to the bit line BL.

In addition, the storage transistors STr and the access transistor ATr can be formed of PMOS transistors by using the N-type silicon substrate by reversing the conductivity types of the respective units.

As described above, according to the semiconductor memory device 1 according to the third embodiment, the storage transistor STr and the access transistor ATr are formed using a bulk substrate rather than an SOI substrate. Therefore, compared with the case of using the SOI substrate which is generally more expensive than a bulk substrate, cost can be reduced.

(Fourth Embodiment)

16 to 18 are top views showing the top layout of the semiconductor memory device according to the fourth embodiment of the present invention. In order to make the layout of each layer clear, the bit line BL is abbreviate | omitted from FIG. 16, and the word line WL, the gate line GL, and the source line SL are omitted from FIG. 19 is an equivalent circuit diagram corresponding to the layout shown in FIG. 20, 21, and 22 are cross-sectional views showing the cross-sectional structure of positions along the lines XX-XX, XXI-XXI, and XXII-XXII shown in FIG. 16, respectively.

Referring to FIG. 18, both the element isolation region IR and the element formation region AR extend along the first direction. In the element formation region IR, an element isolation insulating film 15 shown in FIGS. 21 and 22 is formed. That is, by forming the element isolation insulating film 15 extending in the first direction, the element forming region AR extending in the first direction is defined by the element isolation insulating film 15. The element formation region AR extends continuously along the first direction without being segmented by the element isolation insulating film 15.

Referring to FIG. 17, the word line WL, the gate line GL, and the source line SL are all formed along the second direction. The second direction is a direction perpendicular to the first direction. Gate lines GL are formed on both sides of the source line SL, and word lines WL are formed on the outer side of the gate line GL (opposite to the source line SL). Adjacent word lines WL are formed outside the word lines WL (opposite to the gate lines GL). Source line SL is formed as a 1st layer wiring in a multilayer wiring structure, and is connected to element formation area | region AR via contact plug CP2.

Referring to FIG. 16, the bit line BL is formed extending in the first direction above the element formation region AR. The bit line BL is formed as a 2nd layer wiring in a multilayer wiring structure, and is connected to the element formation area AR through the contact plug CP1. It is also possible to form the bit line BL as the first layer wiring and to form the source line SL as the second layer wiring.

A plurality of memory cells MC (MCa to MCf) are disposed along the bit line BL. The bit line BL is shared by the plurality of memory cells MC arranged in the first direction. In addition, one source line SL is shared by two memory cells MC adjacent to each other along the first direction. In the example shown in FIG. 16, the source line SL is shared by the memory cell MCa of the left end, and the memory cell MCb of the center, for example. The word line WL, the gate line GL, and the source line SL are shared by the plurality of memory cells MC arranged in the second direction.

Referring to Fig. 19, similarly to the first to third embodiments, the memory cell MC has a storage transistor STr and an access transistor ATr. The structure and operation of the storage transistor STr and the access transistor ATr are the same as those of the first to third embodiments.

Referring to FIG. 20, the SOI substrate 14 has a structure in which a silicon substrate 11, a buried oxide film layer 12, and a silicon layer 13 are stacked in this order. The storage transistor STr is formed on the N-type impurity diffusion regions 22 and 24, the channel formation region 23a, the charge accumulation node 23b, the gate oxide film 18, and the gate lines GL shown in FIGS. 16 and 17. It has a corresponding gate electrode 19. The impurity diffusion regions 22 and 24 extend from the top surface of the silicon layer 13 to the top surface of the buried oxide film layer 12, and intersect the channel formation region 23a defined in the top surface of the silicon layer 13. Put on, they are facing each other. The gate oxide film 18 is formed on the channel formation region 23a and the gate electrode 19 is formed on the gate oxide film 18. The charge accumulation node 23b is formed below the channel formation region 23a.

The access transistor ATr has an N-type impurity diffusion region 20, 22, a channel formation region 21, a gate oxide film 16, and a gate electrode 17 corresponding to the word line WL shown in FIGS. 16 and 17. Have The impurity diffusion region 20 extends from the top surface of the silicon layer 13 to the top surface of the buried oxide film layer 12, with the channel formation region 21 defined within the top surface of the silicon layer 13 interposed therebetween. It faces the impurity diffusion region 22. The gate oxide film 16 is formed on the channel formation region 21, and the gate electrode 17 is formed on the gate oxide film 16.

Sidewall spacers 104 made of an insulating film are formed on the side surfaces of the gate electrodes 17 and 19. The silicide layer 100 is formed on the upper surface of the impurity diffusion region 20, the silicide layer 102 is formed on the upper surface of the impurity diffusion region 22, and the silicide layer (on the upper surface of the impurity diffusion region 24). 103 is formed, and the silicide layer 101 is formed on the upper surfaces of the gate electrodes 17 and 19.

In the interlayer insulating film 105, a contact plug 106 connected to the silicide layer 100 and a contact plug 107 connected to the silicide layer 103 are formed. On the interlayer insulating film 105, a metal film 108 connected to the contact plug 106 and a metal wiring 109 connected to the contact plug 107 are formed. The contact plug 107 corresponds to the contact plug CP2 shown in FIG. 17. The metal wiring 109 corresponds to the source line SL shown in FIGS. 16 and 17.

In the interlayer insulating film 110, a contact plug 111 connected to the metal film 108 is formed. On the interlayer insulating film 110, metal wiring 112 connected to the contact plug 111 is formed. The contact plugs 106 and 111 and the metal film 108 correspond to the contact plug CP1 shown in FIG. The metal wiring 112 corresponds to the bit line BL shown in FIG.

21 and 22, a so-called full trench element isolation insulating film 15 extends from the upper surface of the silicon layer 13 to the upper surface of the buried oxide film layer 12. As shown in FIG. That is, the element isolation insulating film 15 has a bottom surface in contact with the top surface of the buried oxide film layer 12.

FIG. 23 is a top view schematically showing the structure of the IC chip 120 in which the semiconductor memory and the logic circuit are configured as one chip. The IC chip 120 includes a memory cell array region 121 in which a semiconductor memory device according to the present invention is formed, an SRAM region 122 in which an SRAM is formed, an analog circuit region 123 in which an analog circuit is formed, and a logic circuit. It has a logic circuit region 124 formed. In addition, a plurality of I / O pads 125 are arranged on the periphery of the IC chip 120.

The memory cell array area 121 corresponds to, for example, the semiconductor memory device 1 shown in FIG. 1. In the memory cell array area 121, the address decoder 2, the input / output circuit 3, the buffer circuit 126, the control circuit 7, the memory array 8, the sense amplifier 9, and the power supply circuit ( 10) is formed. The buffer circuit 126 corresponds to the address buffer 4, the clock buffer 5, and the control signal buffer 6 shown in FIG.

FIG. 24 is a diagram schematically showing the structure of a basic array of 64 kb in the memory cell array region 121 shown in FIG. A total of 64 word lines WL0 to WL63 extending along the row direction (vertical direction in FIG. 24) are arranged in a column direction (horizontal direction in FIG. 24). In addition, a total of 1024 bit lines BL0 to BL1023 extending along the column direction are arranged in a row direction. A plurality of source lines SL shown in FIG. 24 are interconnected at their ends, and a power source potential VDD is applied to the source lines SL. Four bit lines BL are connected to one column selector 131, and the column selector 131 is connected to a circuit 130 including a sense amplifier and a write driver. Further, a mirror memory cell region MMC in which reference bit lines RBLL and RBL0 corresponding to reference bit lines RBLH and RBLL shown in FIG. 8 and transistors Tr1 and Tr2 shown in FIG. 8 are formed is formed.

25-30 is sectional drawing which shows the manufacturing method of the IC chip 120 shown in FIG. 23 in process order. 25-30, the structure of the memory cell array area | region corresponding to FIG. 22, and the structure of the peripheral circuit area | region are shown side by side. Here, the "memory cell array area" corresponds to the memory array 8 shown in FIG. In addition to the SRAM region 122, the analog circuit region 123, and the logic circuit region 124 shown in FIG. 23, the "peripheral circuit region" is located within the memory cell array region 121 shown in FIG. This corresponds to the address decoder 2, the input / output circuit 3, the buffer circuit 126, the control circuit 7, the sense amplifier 9, and the power supply circuit 10.

Referring to FIG. 25, first, a so-called partial trench type device isolation insulating film 140 is formed in the upper surface of the silicon layer 13 in the peripheral circuit region of the SOI substrate 14 by a known trench isolation technique. . In addition, a so-called full trench element isolation insulating film 15 is formed in the upper surface of the silicon layer 13 in the memory cell array region of the SOI substrate 14. The element isolation insulating film 140 is formed in the upper surface of the silicon layer 13 without reaching the upper surface of the buried oxide film layer 12. That is, the element isolation insulating film 140 has a bottom surface which does not contact the upper surface of the buried oxide film layer 12.

Referring to FIG. 26, next, a photoresist 141 having a predetermined opening pattern is formed on the silicon layer 13 by a photolithography method, and then ion implantation of an N-type impurity such as phosphorus or arsenic is performed. An N well 142 is formed in the silicon layer 13 in a portion not covered by the resist 141. Thereafter, the photoresist 141 is removed.

Referring to FIG. 27, next, a photoresist 143 having a predetermined opening pattern is formed on the silicon layer 13 by photolithography, and then ion implanted P-type impurities such as boron to form a photoresist ( The P well 144 is formed in the silicon layer 13 in the portion not covered by the 143. Thereafter, the photoresist 143 is removed.

Referring to FIG. 28, gate oxide films 145 and 18 are formed next by thermal oxidation. Next, after depositing a polysilicon film on the whole surface, the polysilicon film is patterned, and the gate electrodes 146 and 19 are formed. Next, after the silicon nitride film is deposited on the entire surface, the sidewall spacers 104 are formed by etching back the silicon nitride film. Although not shown in FIG. 28, the sidewall spacer 104 is also formed on the side of the gate electrode 19 (see FIG. 20).

29, a P-type impurity diffusion region 148 is formed in the N well 142 by photolithography and ion implantation. Next, an N-type impurity diffusion region 147 is formed in the P well 144 by photolithography and ion implantation. Although not shown in FIG. 29, when the impurity diffusion region 147 is formed, impurity diffusion regions 20, 22, and 24 are also formed in the memory cell array region (see FIG. 20).

Referring to FIG. 30, next, a silicide prevention (protection) film made of a silicon oxide film is formed in a desired region as needed, and then the exposed silicon is silicided using a metal such as titanium or cobalt to form a silicide layer ( 149, 150, 101). Although not shown in FIG. 30, when the silicide layers 149, 150, and 101 are formed, silicide layers 100, 102, and 103 are also formed in the memory cell array region (see FIG. 20).

As is apparent from Figs. 25 to 30, the IC chip 120 according to the fourth embodiment can be manufactured by a general-purpose M0S process without requiring a special process. The semiconductor memory device 1 according to the first embodiment can also be manufactured by the same process as in FIGS. 25 to 30. Therefore, the semiconductor memory device 1 according to the first embodiment can also be manufactured by the general M0S process.

FIG. 31 is a cross-sectional view showing a modification of the structure shown in FIG. 30. The N well 142 is not formed in the peripheral circuit region, and only the P well 144 is formed. In addition, instead of the PMOS having the P-type impurity diffusion region 148 shown in FIG. 30, an NMOS having the N-type impurity diffusion region 147 is formed.

16 to 18, in the semiconductor memory device according to the fourth embodiment, the element formation region AR is formed to extend continuously along the first direction, and the bit line BL extends along the first direction. , The gate line GL, the word line WL, and the source line SL extend along the second direction. The bit line BL is shared by the plurality of memory cells MC arranged and arranged in the first direction, and the source line SL is shared by two memory cells MC adjacent in the first direction.

Therefore, compared with the structure shown in FIG. 3, the area of the memory cell array region can be reduced by the amount that the formation of the element isolation insulating film 15 between the memory cells MC adjacent in the first direction can be omitted. . In addition, since one source line SL is shared by two memory cells MC adjacent in the first direction, the area of the memory cell array region can be further reduced.

2 and 3, according to the structure in which the element isolation insulating film 15 is formed between the memory cells MC adjacent in the first direction, the impurity diffusion region 24 and the element isolation of one memory cell MC are separated. The parasitic capacitor structure is formed by the insulating film 15 and the impurity diffusion region 20 of the other memory cell MC. Therefore, in order to prevent the current leakage through the element isolation insulating film 15, the order in which the source line SL and the bit line BL are arranged so as to widen the separation width of the element isolation insulating film 15 or to adjacent the source lines SL at the equipotential. It is necessary to devise such a replacement. On the other hand, according to the semiconductor memory device according to the embodiment 4, since the element isolation insulating film 15 is not formed between the memory cells MC adjacent in the first direction, such a design does not need to be made.

30 and 31, a full trench device isolation insulating film 15 is formed in the memory cell array region, and a partial trench device isolation insulating film 140 is formed in the peripheral circuit region. It is. Therefore, in the memory cell array region, the memory cells MC adjacent in the second direction are electrically separated completely by the element isolation insulating film 15, while in the peripheral circuit region, the potentials of the body regions of the NMOS and the PMOS are fixed. It becomes possible.

While the present invention has been described in detail, the foregoing description is in all aspects illustrative and the present invention is not limited thereto. Numerous modifications not illustrated are contemplated as being possible without departing from the scope of the present invention.

Claims (10)

A plurality of memory cells arranged in a matrix shape, A bit line selected based on a gate line, a word line, and an address signal, for supplying a write voltage to a memory cell to be written to, and a source line for supplying a power supply voltage / RTI &gt; Each of the plurality of memory cells, A first impurity diffusion region and a second impurity diffusion region facing each other with a first channel formation region interposed therebetween, a first gate electrode formed above the first channel formation region, and formed below the first channel formation region; A storage transistor comprising a charge accumulation node, A third impurity diffusion region connected in series with the storage transistor and opposed to the first impurity diffusion region with the first impurity diffusion region and the second channel formation region interposed therebetween, and above the second channel formation region; An access transistor comprising a second gate electrode formed in the Has, A semiconductor connected to the second impurity diffusion region to the source line, the third impurity diffusion region to the bit line, the first gate electrode to the gate line, and the second gate electrode to the word line store. The method of claim 1, By raising the potential of the first gate electrode from a low level to a high level while the access transistor is turned on, the threshold voltage of the storage transistor is set to a high level, And a threshold voltage of the storage transistor is set at a low level by raising the potential of the first gate electrode from a low level to a high level while the access transistor is turned off. The method of claim 1, The semiconductor substrate, the insulating layer, and the semiconductor layer further comprises a SOI substrate laminated in this order, The first to third impurity diffusion regions and the first and second channel formation regions are all formed in the semiconductor layer, The charge storage node is configured as a part of the semiconductor layer. The method of claim 1, A semiconductor substrate of a first conductivity type, a first well of a second conductivity type, and a second well of the first conductivity type are further stacked in this order; The first to third impurity diffusion regions and the first and second channel formation regions are all formed in an upper surface of the second well, And the charge accumulation node is configured as part of the second well. The method of claim 1, A first memory cell having a threshold voltage of the storage transistor set to a high level; A first reference bit line connected to the first memory cell; A second memory cell having a threshold voltage of the storage transistor set to a low level; A second reference bit line connected to the second memory cell; By comparing the potentials of the first and second reference bit lines with the potentials of the bit lines connected to the read memory cell to be read, it is determined whether the threshold voltage of the storage transistor of the read memory cell is high or low level. Detect sense amplifier circuit The semiconductor memory device further comprising. The method of claim 5, The storage transistor, the access transistor, the first transistor, and the second transistor are connected in series between a power supply potential and a ground potential sequentially from the power supply potential side. Each gate of the first and second transistors is connected to a drain of the first transistor. The method of claim 1, When the threshold voltage of the storage transistor of the write memory cell to be written is set to the high level, a low level potential is applied to a bit line connected to the write memory cell, and the storage transistor of the storage transistor has the write voltage. And a write circuit for applying a high level potential to the bit line connected to the write memory cell when the threshold voltage is set at the low level. The method of claim 1, The semiconductor substrate, the insulating layer, and the semiconductor layer further comprises a SOI substrate laminated in this order, The SOI substrate has a memory cell array region in which the plurality of memory cells are formed, and a peripheral circuit region in which peripheral circuits are formed, In the memory cell array region, a first device isolation insulating film having a bottom surface in contact with an upper surface of the insulating layer is formed. And a second element isolation insulating film having a bottom surface not in contact with an upper surface of the insulating layer in the peripheral circuit region. The method of claim 1, The potential of the charge accumulation node is controlled by switching the potential of the first impurity diffusion region to a constant potential or floating state by turning on / off the access transistor, whereby the threshold voltage of the storage transistor is at a high level. Or a semiconductor memory set at a low level. delete

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