KR101150463B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and has a thickness equal to an upper side of a vertical pillar defined as a source / drain region and a lower side of a vertical pillar defined as a channel region, thereby preventing a vertical filler from breaking. Discuss the technology. To this end, the present invention includes a vertical filler formed on the semiconductor substrate, a spacer formed on the filler sidewall of the source / drain predetermined region, and a vertical surround gate formed on the filler sidewall under the spacer.

Surround Gate, Spacer

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the thickness of the vertical pillars defined as the source / drain regions and the vertical pillars defined as the channel regions is the same to prevent the vertical pillars from being broken. The present invention relates to a semiconductor device and a method of manufacturing the same.

Recently, in the case of semiconductor devices such as DRAMs, a technique for increasing the degree of integration by forming more transistors in a limited area is required. For this purpose, a vertical transistor technology capable of putting a memory cell element in a small area has been proposed. In the case of a memory device, the vertical transistor provides a surrounding gate structure surrounding the vertical channel.

This surround gate structure selectively isotropically etches the channel region to form at 4F2, making the channel region relatively thinner than the source / drain regions. In the surround gate structure, the front surface of the channel region may be surrounded by the gate electrode to maximize the control power of the gate. In addition, the surround gate structure provides not only a short channel effect but also the widest current flow area to provide excellent operating current characteristics. On the other hand, thinner and longer channel structures are required to increase the density of vertical transistors.

1 is a plan view showing a semiconductor device according to the prior art.

Referring to FIG. 1, cylindrical pillars (not shown) including a hard mask pattern 12 are regularly arranged on the semiconductor substrate 10, and spacers 14 are formed on each pillar sidewall.

2A to 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, and are shown along a cutting line AA ′ of FIG. 1.

Referring to FIG. 2A, a pad oxide layer 22 and a hard mask layer (not shown) are formed on the semiconductor substrate 20. Next, the hard mask layer is etched by a photolithography process using a mask defining an active region to form a hard mask layer pattern 24.

Next, the pad oxide layer 22 and a part of the semiconductor substrate 20 are etched using the hard mask layer pattern 24 as an etch mask to form a first pillar 26 predetermined as a source / drain region. Next, an insulating film (not shown) is formed on the semiconductor substrate 20, the first filler 26, and the hard mask layer pattern 24. Next, the insulating layer is selectively etched to form spacers 28 on sidewalls of the first pillar 26, the pad oxide layer 22, and the hard mask layer pattern 24.

Next, a portion of the semiconductor substrate 20 is selectively etched using the first pillar 26 and the spacer 28 as an etch mask to form a second pillar (not shown) extending below the first pillar 26. Then, an isotropic etching process is performed on the second pillar to form a third pillar 30 that is narrower than the first pillar 26 and is defined as a channel region.

Referring to FIG. 2B, a gate insulating layer 32 is formed on the surfaces of the third pillar 30 and the semiconductor substrate 20. Next, a conductive layer (not shown) is formed on the gate insulating layer 32 and the first and third pillars 26 and 30 to fill the gaps between the first and third pillars 26 and 30. Next, the conductive layer is etched using the hard mask layer pattern 24 as an etch mask to form a surround gate 34 surrounding the third pillar 30.

 In general, a memory cell having a line width of 50 nm or less causes a channel structure to be very thin and broken or collapsed. This is a limitation to high integration of a vertical transistor having excellent characteristics. In particular, when the thickness of the vertical transistor is constant, there is structural stability. However, if the thickness of the vertical device is not constant, the structural stability is inferior.

Vertical transistors having such an unstable structure collapse or break in subsequent processing to form impurities on the wafer. Thus, the yield of devices due to such impurities is reduced. In addition, there is a problem that the vertical structure is broken if the uniformity is poor during local isotropic etching.

Meanwhile, in order to form a wide source / drain region formed on the upper portion of the pillar, the surround gate is formed to be spaced apart from the pillar surface by a predetermined distance. In this case, gate-induced drain leakage (GIDL) or junction leakage current may be reduced. In addition, it is possible to prevent the occurrence of a bridge with the surround gate due to misalignment or increase in the line width (CD) of the contact hole during the subsequent contact formation.

However, as the device is highly integrated, the cross-sectional area of the vertical structure is reduced, and it is more difficult to manufacture a structure in which it is formed in an array form and connected to a word line than to manufacture a transistor having a surround gate. In particular, since the spacers formed on the sidewalls of the vertical structure are thinly formed to prevent the vertical structure from being broken, the upper side of the filler is easily exposed when forming a damascene word line connecting the surround gates. There is a problem that a bridge is caused between the source / drain area and the damascene word line.

The present invention has the following object.

First, the vertical pillars defined as the source / drain region and the vertical pillars defined as the channel region have the same thickness to prevent the vertical pillars from being broken.

Second, the spacers formed on the vertical pillar sidewalls of the source / drain regions may be formed to be thick, thereby preventing the bridge between the source / drain regions and the damascene word line.

Third, the vertical filler can be thinned by oxidizing the surface of the vertical filler to form a gate oxide film, and removing the gate oxide film.

The semiconductor device according to the present invention comprises a vertical filler formed on the semiconductor substrate; Spacers formed on the sidewalls of the source / drain predetermined region; And a vertical surround gate formed on the pillar sidewall under the spacer. Here, the gate insulating film formed on the filler surface is characterized in that it further comprises.

In addition, the method of manufacturing a semiconductor device according to the present invention may include forming a filler perpendicular to the upper portion of the semiconductor substrate; Forming a conductive layer pattern partially filling the pillars; Forming a spacer on the sidewall of the pillar above the conductive layer pattern; And etching the conductive layer pattern using the spacer as an etch mask to form a vertical surround gate.

The filler forming step may include forming a hard mask layer pattern defining an active region on the semiconductor substrate; And etching the portion of the semiconductor substrate using the hard mask layer pattern as an etch mask, wherein the hard mask layer pattern is any one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a combination thereof. And the silicon oxide film is formed by a plasma chemical vapor deposition method using a source gas including teos (TEOS (Si (OC ₂ H ₅ ) ₄ )) or silane (SiH ₄ ). .

The silicon nitride film is formed by a low pressure chemical vapor deposition method using a source gas containing dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ), and a first gate insulating film is formed on the surface of the filler after the filler forming step. The method may further include forming a silicon oxide film with a thickness of 30 to 300 kPa, and the first gate insulating film may include oxygen (O ₂ ) and water (H) at a temperature of 200 to 1000 ° C. Formed by using any one selected from the group consisting of ₂ O), hydrogen (H ₂ ), ozone (O ₃ ) and a combination thereof as a source gas.

And removing the first gate insulating film, and then performing a reoxidation process on the filler surface to form a second gate insulating film, wherein the first gate insulating film removing process includes hydrofluoric acid (HF). The wet etching method, the first gate insulating layer removing process may be performed by an isotropic etching method using a remote plasma, and the forming of the conductive layer pattern may include forming a conductive layer filling the gap between the pillars. Doing; Planar etching the conductive layer; And etching the conductive layer to expose a portion of the filler.

In addition, the conductive layer is etched by a thickness of 400 ~ 1000Å from the upper side of the filler, the conductive layer is formed of any one selected from the group consisting of a polycrystalline silicon layer, a metal layer and a combination thereof, the polycrystalline silicon layer formed Forming by injecting any one of phosphorus (Ph), boron (B), and a combination thereof during the process, and performing an oxidation process on the surface of the conductive layer after the conductive layer etching step; And removing the oxidized conductive layer.

In addition, the oxidized conductive layer has a thickness of 20 ~ 60Å, the spacer forming step may include forming an insulating film on the conductive layer and the filler; And dry etching the insulating film, wherein the insulating film is formed of a silicon nitride film, and the insulating film is a low pressure chemical vapor deposition method using a source gas containing dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). Alternatively, the spacer may be formed by an atomic layer deposition method, and the spacer may be formed to a thickness of 50 to 200 kPa.

The present invention provides the following effects.

First, the thickness of the vertical pillars defined as the source / drain region and the vertical pillars defined as the channel region is the same, thereby providing an effect of preventing the vertical pillars from being broken.

Second, the spacers formed on the vertical pillar sidewalls of the source / drain regions may be formed thick, thereby providing an effect of preventing a bridge between the source / drain regions and the damascene word line.

Third, the vertical filler surface is oxidized to form a gate oxide film, and the vertical filler may be thinned through a process of removing the gate oxide film.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 3A, a pad oxide layer 102 and a hard mask layer (not shown) are formed on the semiconductor substrate 100. Here, the hard mask layer is preferably any one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a combination thereof. At this time, the silicon oxide film is preferably formed by a plasma chemical vapor deposition (CVD) method using a source gas containing TEOS (TEOS (Si (OC ₂ H ₅ ) ₄ )) or silane (SiH ₄ ). .

In addition, the silicon nitride film is preferably formed by a low pressure chemical vapor deposition (LPCVD) method using a source gas containing dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). On the other hand, the hard mask layer is preferably formed to a thickness of 500 ~ 5000Å. In addition, the hard mask layer may be formed of a material having an etching rate of less than half that of the semiconductor substrate during etching of the semiconductor substrate 100.

Next, the hard mask layer is etched by a photolithography process using a mask defining an active region to form the hard mask pattern 104. Here, the upper surface of the hard mask pattern 104 is preferably circular or polygonal. Subsequently, the pad oxide layer 102 and a portion of the semiconductor substrate 100 are etched using the hard mask pattern 104 as an etch mask to form a vertical filler 106 to define an active region. Here, it is preferable to form the filler 106 in thickness of 900-3000 kPa.

Referring to FIG. 3B, the gate insulating layer 108 is formed on the surface of the filler 106. Here, the gate insulating film 108 is preferably formed of a silicon oxide film. At this time, the silicon oxide film source gas selected from the group consisting of oxygen (O ₂ ), water (H ₂ O), hydrogen (H ₂ ), ozone (O ₃ ) and combinations thereof at a temperature of 200 ~ 1000 ℃. It is preferable to form using.

Since the silicon oxide film has various crystal planes on the surface of the filler 106, it is preferable to form the silicon oxide film by an oxidation method such as a plasma oxidation method or a radical oxidation method in which the oxidation rate of silicon is independent of the crystal plane of silicon. In addition, the gate insulating film 108 is preferably formed to a thickness of 30 ~ 300Å.

Referring to FIG. 3C, the conductive layer 110 is formed on the gate insulating layer 108, the filler 106, and the hard mask layer pattern 104, and the conductive layer 110 is planarized. The conductive layer 110 may be formed of any one selected from the group consisting of a polycrystalline silicon layer, a metal layer, and a combination thereof. In this case, the polycrystalline silicon layer may be formed by implanting an impurity, and the impurity may be any one of phosphorus (Ph), boron (B), and a combination thereof.

In addition, the metal layer may include a titanium (Ti) layer, a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten (W) layer, a copper (Cu) layer, an aluminum (Al) layer, a tungsten silicide (WSi _x ) layer, and It is preferably any one selected from the group consisting of a combination of these. In addition, the planarization of the conductive layer 110 may be performed by a chemical mechanical polishing (CMP) method.

Referring to FIG. 3D, the conductive layer 110 is selectively etched to form a conductive layer pattern 110a partially filling the pillars 106. Here, the etching process of the conductive layer 110 is preferably performed by a dry etching method. On the other hand, the conductive layer 110 is preferably etched by a thickness of 400 ~ 1000Å from the top of the hard mask layer pattern 104. At this time, the upper portion of the filler 106 exposed by the conductive layer pattern 110a is defined as a source / drain region.

Meanwhile, an oxidation process may be further performed to remove residues remaining on the surface of the gate insulating layer 108 after the conductive layer pattern 110a is formed. This may be applied to the case where the conductive layer 110 is formed of a polycrystalline silicon layer, and the thickness of the conductive layer pattern 110a to be oxidized is preferably 20 to 60 kPa. The oxidized residue is then removed.

Referring to FIG. 3E, an insulating film (not shown) is formed on the conductive layer 110, the gate insulating film 108, and the hard mask layer pattern 104. Next, the insulating layer is dry-etched to form spacers 112 on the sidewalls of the hard mask layer pattern 104 and the gate oxide layer 108.

Here, the insulating film is preferably formed of a silicon nitride film. In this case, the silicon nitride film is a low pressure chemical vapor deposition (LPCVD) method or an atomic layer deposition (ALD) method using a source gas containing dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). It is preferable to form. On the other hand, the insulating film may be formed of a stacked structure of an oxide film, a nitride film and an oxide film in order to reduce the loss in the subsequent surround gate formation. In addition, the spacer 112 is preferably formed to a thickness of 50 ~ 200Å.

Referring to FIG. 3F, the conductive layer 110 is etched using the hard mask layer pattern 104 and the spacer 112 as an etch mask to form a vertical surround gate 110b on the sidewall of the filler 106. Afterwards, word lines and bit line patterning may be performed to complete vertical transistors. Here, since the isotropic etching process is not performed when the vertical surround gate 110b is formed, the thickness of the filler 106 may be fixed to prevent the phenomenon of breaking.

Meanwhile, although not shown in the drawing, the gate insulating film 108 may be removed to thin the filler 106, and the gate insulating film 108 may be formed again by performing a reoxidation process on the surface of the filler 106. As such, when the filler 106 is thinned, short channel effects can be improved. That is, the influence of the source / drain regions can be reduced to reduce off leakage current even at shorter channel lengths.

Here, the removal process for the gate insulating film 108 is preferably performed by a wet etching method including hydrofluoric acid (HF). In this case, the removal process for the gate insulating layer 108 may be performed by a dry etching method having excellent selection characteristics. In addition, the dry etching process is preferably performed by an isotropic etching method using a remote plasma.

1 is a plan view showing a semiconductor device according to the prior art.

2A to 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Claims (23)

delete delete Forming a filler having a vertical shape on the semiconductor substrate; Forming a conductive layer pattern partially filling the pillars; Forming a spacer on the sidewall of the pillar above the conductive layer pattern; And Forming a vertical surround gate by etching the conductive layer pattern using the spacer as an etch mask Method of manufacturing a semiconductor device comprising a. Claim 4 was abandoned when the registration fee was paid. The method of claim 3, wherein the filler forming step Forming a hard mask layer pattern defining an active region on the semiconductor substrate; And Method of manufacturing a semiconductor device comprising a. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein the hard mask layer pattern is formed of any one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a combination thereof. Claim 6 was abandoned when the registration fee was paid. The semiconductor of claim 5, wherein the silicon oxide layer is formed by a plasma chemical vapor deposition method using a source gas including teos (TEOS (Si (OC ₂ H ₅ ) ₄ )) or silane (SiH ₄ ). Method of manufacturing the device. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5, wherein the silicon nitride layer is formed by a low pressure chemical vapor deposition using a source gas containing dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). Claim 8 was abandoned when the registration fee was paid. 4. The method of claim 3, further comprising forming a first gate insulating film on the surface of the filler after the filler forming step. Claim 9 was abandoned upon payment of a set-up fee. 9. The method of claim 8, wherein the first gate insulating film is formed of a silicon oxide film having a thickness of 30 to 300 [mu] s. Claim 10 has been abandoned due to the setting registration fee. The group of claim 8, wherein the first gate insulating layer is formed of oxygen (O ₂ ), water (H ₂ O), hydrogen (H ₂ ), ozone (O ₃ ), and combinations thereof at a temperature of 200 ° C. to 1000 ° C. 10. A method of manufacturing a semiconductor device, characterized in that formed using any one selected from the source gas. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 8, after the forming of the first gate insulating film on the surface of the pillar after the filler forming step, Removing the first gate insulating film; And And forming a second gate insulating film by performing a reoxidation process on the filler surface. Claim 12 is abandoned in setting registration fee. The method of claim 11, wherein the removing of the first gate insulating layer is performed by a wet etching method including hydrofluoric acid (HF). Claim 13 was abandoned upon payment of a registration fee. The method of claim 11, wherein the first gate insulating layer is removed by an isotropic etching method using a remote plasma. Claim 14 has been abandoned due to the setting registration fee. The method of claim 3, wherein the forming of the conductive layer pattern is performed. Forming a conductive layer filling the space between the pillars; Planar etching the conductive layer; And Etching the conductive layer to expose a portion of the filler Method of manufacturing a semiconductor device comprising a. Claim 15 was abandoned upon payment of a registration fee. 15. The method of claim 14, wherein the conductive layer is etched by a thickness of 400 to 1000 microseconds from an upper side of the filler. Claim 16 has been abandoned due to the setting registration fee. The method of claim 14, wherein the conductive layer is formed of any one selected from the group consisting of a polycrystalline silicon layer, a metal layer, and a combination thereof. Claim 17 has been abandoned due to the setting registration fee. The method of manufacturing a semiconductor device according to claim 16, wherein the polycrystalline silicon layer forming step is formed by injecting any one of phosphorus (Ph), boron (B), and a combination thereof. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 16, wherein after the conductive layer etching step Performing an oxidation process on the surface of the conductive layer; And Method of manufacturing a semiconductor device further comprising. Claim 19 was abandoned upon payment of a registration fee. 19. The method of claim 18, wherein the oxidized conductive layer is 20 to 60 microns thick. Claim 20 was abandoned upon payment of a registration fee. The method of claim 3, wherein the spacer forming step Forming an insulating film on the conductive layer and the filler; And Dry etching the insulating film Method of manufacturing a semiconductor device comprising a. Claim 21 has been abandoned due to the setting registration fee. 21. The method of claim 20, wherein the insulating film is formed of a silicon nitride film. Claim 22 is abandoned in setting registration fee. The method of claim 21, wherein the insulating layer is formed by a low pressure chemical vapor deposition method or an atomic layer deposition method using a source gas containing dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). . Claim 23 was abandoned upon payment of a set-up fee. The method of claim 3, wherein the spacer is formed to a thickness of about 50 to about 200 microns.

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