TW434820B - Method for producing self-aligned contact hole - Google Patents

Abstract

The present invention provides a method for producing a self-aligned contact hole on a semiconductor chip. The semiconductor chip comprises a substrate; two adjacent gates installed on the substrate; and a plurality of spacers installed on the periphery of the two gates. The substrate between the two gates is at least formed with a doped region, and the spacers between the two gates are connected to each other and cover the doped region. The method comprises forming a dielectric layer on the surface of the semiconductor chip covering the two gates and the spacers; performing a first etching process to remove the dielectric layer on the doped region to a specified depth to form a hole, the bottom of the hole being formed of a portion of the two gates and a portion of the top portion of the spacers; forming a polysilicon spacer on the inner wall of the hole covering the top regions of the two gates and the spacers; performing a second etching process to downwardly etch the dielectric layer and the spacer between the two gates along the polysilicon spacer in the hole until the surface of the doped region, thereby completing the production of the self-aligned contact hole.

Description

V. Description of the invention (1) Field of the invention The present invention provides a method for making self-aligning contact holes on vehicles, especially a method for making self-aligning contact holes of "Lu ^ 11" body. In the semiconductor process, contact holes are used to make metal interconnects that electrically connect various components in integrated circuits. In the method of making contact holes, photolithography and dry etching are usually used to directly A plurality of vertical holes are formed on the surface of the wafer as contact holes. As the line width in the semiconductor process decreases, the hole diameter of the contact hole also decreases. At present, the semiconductor process uses an etching process for different materials. The etching selectivity is used to perform self-aligned contact etching to form a contact hole on a semiconductor wafer. Please refer to FIGS. 1 to 3, which are familiar to a conductor. A schematic diagram of a method for making self-aligned contact holes 34 on the wafer 10. The semiconductor wafer 10 includes a silicon substrate 12 and two adjacent gate electrodes 24 are disposed on silicon. A predetermined region on the surface of the substrate 12, a doped region 14 is provided on the silicon substrate 12 between the gates 24, and a dielectric layer 28 made of silicon oxide is provided on the silicon substrate 12 and Cover the two gates 24. Each gate 2 4 contains one by the dioxide

Page 5 434820 V. Description of the invention (2) The gate halide layer 16 and a dopant layer 20 are formed. In addition, each gate 24 surface and each gate 20 on the vertical side of the homogeneous layer 20 and the side wall 22 are covered with a nitride stone polycrystalline dream layer 18 and a metal stone surface is covered with a protection The layer 22 is covered with a side wall 26. The method of making the self-aligned contact hole 34 is to coat a photoresist layer 30 on the dielectric layer 28, and then perform a A lithography process forms a pattern 32 in the photoresist layer 30 to contact the position and size of the hole 34, as shown in FIG. Next, the photoresist layer 30 is used as a hard mask to perform a dry etc (dry etcU process, and the dielectric layer 28 is etched vertically downwards along the pattern 32 in the photoresist layer 30, until the substrate is from 1 μM to 1 μM. A contact hole 34 is formed on the surface of the doped region 14 on 12, and finally the photoresist layer 30 is stripped, as shown in Fig. 3. In the conventional self-aligned contact etching process! The etching process is mainly used. The etching selection ratio between silicon oxide and silicon nitride is used for self-alignment. The contact name is engraved to form the contact hole 34. That is, the etching rate of the dielectric layer? 8 and the sidewall 26 is adjusted by adjusting the etching process, so that The etching rate of the dielectric 28 in the etching process is greater than the etching rate of the sidewalls 26, so as to achieve the purpose of only etching the dielectric layer 28. As shown in FIG. 3, due to the reduction of the line width in the semiconductor process, the gate electrode is reduced. The height of 24 is relatively increased, and in order to reduce the contact resistance between the conductive plug and the doped region 4 formed later in the contact hole 34, the contact area between the contact hole 34 and the doped region 14 must be increased to form The side walls 28 are also relatively thin. When forming the contact hole 34, etching

Page 6 V. Description of the invention (3) In the thickness of about 6000-800 0 angstroms (angstrom, Λ), after a long time of etching, the top protection 26 above the gate will be damaged, especially the top protection The most severe damage is to the layer 22 and the side walls. The destruction of the top protective layer 22 and the side walls 26 affects the main structure of the gate electrode 24. For example, the doped polycrystalline silicon silicide 20 may reduce the distance from the contact hole filled in later, causing the material used for insulation barrier to be too thin. The heteropoly silicon layer 18 and the metal silicon 20 'and the filled contact material leak electricity. Or short circuit. SUMMARY OF THE INVENTION Therefore, the main purpose of the present invention is to provide a self-manufacturing method to solve the above-mentioned conventional self-aligning contact hole problem. The present invention provides a method for making a hole on a semiconductor wafer. The semiconductor wafer includes a substrate, two above the substrate, and a plurality of sidewalls disposed on the substrate between the two gates. At least one doped region is generated, and the walls are connected to each other and cover the doping. Above the district. A dielectric layer was formed on the surface of the semiconductor wafer, covering the junction between the dielectric layer 26, the process layer 22, and the side wall 26, which may straighten the conductive material of the silicon layer 18 and the gold 34, thereby causing doping. The method of manufacturing the conductive object alignment contact hole of the hole 34 is such that the self-aligned contact adjacent electrodes are disposed around the electrodes. The method of inventing the side between the two gates is on the two gates above the invention (4) and the side wall. Then, a "first etching process" is performed to remove the dielectric layer above the doped region to a predetermined depth to form a hole, and the bottom of the hole is formed by the two gates and a partial region on the top of the sidewall. β Next, a polycrystalline sidewall is formed on the inner wall of the hole, covering the two gates and the top area of the sidewall. Finally, a second etching process is performed to etch the dielectric layer between the two gates and the sidewalls down to the surface of the doped region along the polycrystalline silicon sidewalls in the hole to complete the self-aligning contact hole process. / As the present invention uses the etching process to form the self-aligned contact hole with a high etching selection ratio between the polycrystalline silicon sidewall and the gasified silicon sidewall, it can effectively avoid covering the top of the gate. The protective layer is damaged by the etching process. In addition, the present invention can also be used in a process below 0.15 microns to avoid over-etching the silicon nitride layer over the gate electrode, thereby ensuring that the gate electrode and the subsequent formation in the self-alignment 2 The conductive plug in the galvanic isolation effect. In addition, the present invention does not need to form a sidewall between the idler electrodes, reduces an etching process, and simplifies the contact hole two. For detailed description of the invention, please refer to FIG. 4 to FIG. 9, which are schematic diagrams of a method for making a self-aligned contact hole (! 68) on a conductor wafer 40 by using the present invention. As shown in FIG. 4, the semiconductor chip 40 includes a silicon substrate 42 and an active region.

434820 V. Description of the invention (5) Set 4 3 on a predetermined area on the surface of the broken substrate 4 2, a shallow trench isolation 4 5 is provided on the surface of the silicon substrate 42 on the periphery of the active area 43, and two adjacent gates 56 are provided on On the surface of the active region 4 3, four side walls 5 8 are disposed around the gate electrode 5 6, a doped region 4 4 is disposed on the broken substrate 4 2 between adjacent closed electrodes 5 6, and The layer 46 is located between the gate 56 and the silicon substrate 42 and the side wall 5 8 to release the thermal stress of the side wall 58 on the semiconductor wafer 40. The side wall 5 8 is made of silicon oxide or nitride nitride. Composition, due to the reduction of the line width in the semiconducting Zhao process, it is very difficult to form the side walls 58 between the gates 56. Therefore, the side walls 58 located between the gates 56 are connected to each other and covered with doping. District 4 4 above. Shallow trench isolation 4 5 is used to electrically isolate the active area 43 from other electronic components on the silicon substrate 42. Fi semiconductors can be used in semiconductor processes with large design rules. Instead of shallow trench isolation 45. The gates 5, 6 include a gate oxide layer 48 made of silicon dioxide on a predetermined area on the surface of the substrate 42. A doped polycrystalline silicon layer 50 is disposed on the gate oxide layer 48, and a metal silicide The layer 52 is disposed on the doped polycrystalline silicon layer 50, and a protective layer 54 composed of a nitrided layer is disposed on the metal silicide layer 52. Please refer to Article 5. The method for making a contact hole according to the present invention is to first perform a low pressure chemical vapor deposition (LPCVD) process to form a dielectric layer 60 on the surface of the semiconductor wafer 40 and cover the gate electrode. 56 and sidewall 58 above. Then, a photoresist layer 62 is formed on the surface of the dielectric layer 60 by the spin method |, and a yellow light process is performed.

43482 〇 5. Description of the invention (6) A pattern 63 is formed in the photoresist layer 62. The process 60 etches the electrical layer 60 down to a predetermined depth vertically along the pattern 63, and then completely removes it to form a hole 64. A part of the area on top of the side wall member 58 may leave a little dielectric layer 60. As shown in FIG. 6, a photolithography process is performed to remove the photoresist removal process located above the doped region 4 4. The bottom of the photoresist layer 62 hole 64 is composed of the gate electrode 56 and the photoresist layer. The bottom is as shown in Figure 27. After the holes 64 are formed, another process is performed to form a polycrystalline silicon layer 65 with a uniform thickness on the surface of the semiconductor wafer 40, covering the dielectric layer 60 and the inner and bottom surfaces of the holes 64. As shown in FIG. 8, a dry etching process is performed after k ′ to remove the polycrystalline silicon layer δ 5 located on the bottom surface of the dielectric layer 60 and the hole 64, so as to remain above the top regions of the gate electrode 56 and the side wall 58. The polycrystalline silicon layer 65 forms a polycrystalline silicon sidewall 66, that is, the polycrystalline silicon sidewall 66 covers the top region of the gate 56 and the sidewall 58. The reaction temperature of this LPCVD process is controlled to 600-600 ~ Between 650 ° C, the reaction pressure is controlled between 0.3 and 0.6 (torr) to avoid the formation of amorphous silicon. The thickness (W) of the polycrystalline silicon layer 65 must be less than half the diameter (Y) of the hole 64 That is, W < 0. 5Y (as shown in Figure 7), so that the subsequent dry etching process can be performed on the holes 64. A polycrystalline silicon wall 5 6 is formed on the inner wall »As shown in FIG. 9, an etching process is finally performed, and the polysilicon sidewall 6 6 on the inner wall of the hole 6 4 is etched down to the dielectric layer 60 and the tree between the gates 5 6. The wall 5 8 reaches the surface of the silicon oxide layer 46, and then the etching selection ratio of the etching process is adjusted, and the silicon oxide layer 4 6 is removed to the surface of the doped region 4 4 to form a self

Page 10 4348 2 0 V. Description of the invention (7) _ The row alignment contact hole 68 is used to fill a conductive object φ conductive plug. Since part of the inner wall of the contact hole 68 is located on the surfaces of the non-conductors 58 and 66, the area between the bottom of the contact hole 68 and the antennas is small. In order to prevent the resistance value of the J electrical plug formed in the contact hole 68 from increasing in the future, after the contact hole 68 is completed, an ion doping may be performed to reduce the doped region. The process selects the π etching selection ratio between polycrystalline silicon, silicon nitride, and silicon oxide to form a self-aligned contact hole 68 to prevent the gate top protective layer 54 and the side wall 58 from being damaged during a long etching process. Since the etching selection ratio of polycrystalline silicon, silicon nitride, and silicon oxide is better than the etching selection ratio of silicon nitride to silicon oxide, when the self-aligned etching is performed to form the contact hole 68, the top protective layer 54 and the side walls are covered. The polycrystalline silicon sidewalls 6 6 above 58 can effectively prevent the top protective layer 5 5 and the sidewalls 5 8 from being damaged by the etching process, thereby ensuring that the gate electrode 5 6 and subsequent conductive plugs formed in the contact holes 68 are electrically charged. Isolation effect. In addition, different from the conventional technology thickness, the contact hole 38 and the doped polycrystalline silicon sidewall 66 are used to define the contact and then control the subsequent contact resistance β formed in the contact hole. Because the gate is located at the gate to affect the contact area, the gate uses the gate. On the side between the poles 24, the contact area of the area 14 of the motorcycle 28. The present invention relates to the contact area between the hole 6 8 and the doped region 4 4. The thickness of the sidewall spacer 5 8 between the conductive plug in 68 and the doped region 44 5 6 is not the thickness of the sidewall spacer 5 between 5 6. 8 can phase each other

Page 11 434820 Jade, description of the invention (8) is connected and the back cover is over the doped region 44. The side wall 58 is formed by using gas, chemical deposition and an etching step. Since the thickness of the side wall 58 does not affect the contact area, the etching process for forming the side wall 5 8 can be omitted by using the present invention. Therefore, it is only necessary to perform the nitridation deposition step, as shown in the following embodiment. Please refer to FIGS. 10 to 15. FIGS. 10 to 15 are schematic diagrams of making a self-aligned contact hole 98 on a semiconductor wafer 70 using another embodiment of the present invention. Please refer to Fig. 10 ', which is different from the previous embodiment in that the present embodiment replaces the side wall 58 with a silicon nitride layer 88, which is provided on the surface of the silicon substrate 42 and covers the sides of the gate 56 and above. As shown in Figure Η--, when a contact hole is made on the semiconductor wafer 70 ', a LPCVD process is first performed to form a dielectric layer 90 on the surface of the semiconductor wafer 70 and cover the silicon nitride layer 88. Next, a photoresist layer 92 is formed on the surface of the dielectric layer 90 by a spin coating method, and a yellow light process is performed to form a pattern 93 in the photoresist layer 92. As shown in FIG. 12, a lithography process is then performed to etch down the dielectric layer 90 above the doped region 44 to a predetermined depth along the case 9 3 vertically down to the surface of the silicon nitride layer 88, and then The photoresist layer 92 is completely removed by a photoresist removal process to form a hole 94. The bottom of the hole 94 is composed of a silicon nitride layer 88 on the top of the gate 86. In addition, a small dielectric layer 90 may remain at the bottom of the hole 94. As shown in FIG. 13, after the formation of the hole 94, Then another LPCVD process is performed to form a polycrystalline silicon layer 95 with a uniform thickness on the surface of the semiconductor wafer 70 to cover the dielectric layer 90 and the inner wall and bottom surface of the hole 94. Figure fourteen

Page 12 434820 5. As shown in the description of the invention (9), a dry etching process is subsequently performed to remove the polycrystalline silicon layer 95 ′ located on the bottom surface of the dielectric layer 90 and the hole 9 4 so as to remain on the gate electrode 5 6 and the silicon nitride layer 8 The polycrystalline silicon layer 95 above the top region 8 forms a sidewall 96, that is, the polycrystalline silicon sidewall 96 covers the silicon nitride layer 88 on top of the anode 56. Finally, an etching process is performed along the polysilicon sidewalls 9 6 on the inner wall of the hole 9 4 to etch the remaining dielectric layer 90 and the silicon nitride layer 8 8 between the gate 56 and the silicon oxide layer 46. Then, the etching selection ratio of the etching process is adjusted, and the silicon oxide layer 46 is removed until the surface of the doped region 44 is formed to form a self-aligned contact hole 98, as shown in Fig. 15. As the line width of the semiconductor design and manufacturing continues to shrink, the sidewalls 58 formed between the gates 56 further reduce the contact area between the contact hole 68 and the doped region 44. In the present invention, a silicon nitride layer 8 8 is formed on the surface of the semiconductor wafer and covers the gate electrode 56 to replace the side wall 5 8 as a protective layer of the gate electrode 5 6. The present invention is used to etch to form a contact hole 9. At 8 o'clock, the polycrystalline silicon sidewall 9 6 overlying the silicon nitride layer 8 8 can effectively prevent the silicon nitride layer 8 8 from being over-etched, thereby ensuring that the gate electrode 8 6 and the subsequent formation of the self-aligned contact hole 98 The conductive plug is electrically isolated. Compared with the conventional method of making self-aligned contact holes 38, the present invention uses self-aligned contact holes 98 to form a self-aligned contact hole 98 using a high etching selection ratio between polycrystalline silicon and silicon nitride by an etching process, which can effectively avoid covering the gate electrode. The protective layer 54 above 56 is protected from being damaged by the etching process, which ensures the main structure of the gate electrode 56. In addition, the present invention can also be used in processes below 0.15 micron.

Page 13 434820 5. In the description of the invention (ίο) 'Avoid the silicon nitride layer 8 8 covering the gate 5 6 from being over-etched, thereby ensuring that the gate 56 and the subsequent conductive plug formed in the contact hole 98 Electrical isolation effect. In addition, the present invention does not need to form a sidewall between the gate electrodes 56, which reduces an etching process, and simplifies the process of contact holes. The description in Ling is only a preferred embodiment of the invention, and all equivalent changes and modifications made in accordance with the application of the invention should fall within the scope of the invention patent.

Page 14 43482 0 Schematic illustrations of the diagrams Simple illustrations Circles 1 to 3 are schematic diagrams of the methods for making self-aligned contact holes for conventional use β 4 to 9 are schematic diagrams of the methods for making self-aligned contact holes according to the invention q Figure 10 Fig. 15 to Fig. 15 are schematic diagrams of another embodiment of the present invention. Explanation of symbols in the diagram 10 Semiconductor wafer 12 Silicon substrate 14 Doped region 16 Gate oxide layer 18 Doped polycrystalline silicon layer 20 Metallic layer 22 Top protection layer 24 Gate. 26 Side wall 28 Dielectric layer 30 Photoresist layer 32 pattern 34 contact hole 40 semiconductor crystal 42 silicon substrate 43 active region 44 doped region 45 shallow trench isolation 46 silicon oxide layer 48 gate oxide layer 50 doped polycrystalline silicon layer 52 metal silicide layer 54 top protective layer 56 gate 58 sidewall child

43482 0 Brief description of the diagram 60 Dielectric layer 62 Photoresist layer 63 Case 64 Hole 6 5 Polycrystalline silicon layer 66 Side wall 68 Contact hole 70 Semiconductor wafer 88 Silicon nitride layer 90 Dielectric layer 92 Photoresist layer 93 Pattern 94 Hole 95 Polycrystalline silicon layer 96 sidewall 98 contact hole 第 6 页