KR101131216B1 - Manufacturing method for thin film of poly-crystalline silicon - Google Patents

Abstract

Method for producing a polycrystalline silicon thin film according to the present invention, a metal layer forming step of forming a metal layer on an insulating substrate; A first heat treatment step of forming a metal oxide film by heat-treating the metal layer formed in the metal layer forming step; Forming a first silicon layer by laminating an amorphous silicon layer on the oxide film; A second heat treatment step of forming a metal silicide oxidation catalyst film by heat-treating the oxide film and the first silicon layer; Forming a second silicon layer by laminating amorphous silicon on the catalyst film; Forming a surplus metal absorbing layer stacked on the second silicon layer to form a surplus metal absorbing layer that absorbs excess metal particles that do not participate in crystallization during heat treatment of the first silicon layer; A preliminary crystallization step of thermally treating the second silicon layer to produce crystalline silicon in the second silicon layer; And removing the excess metal absorbing layer to remove the excess metal absorbing layer after the preliminary crystallization step. Characterized in that it comprises a.

Description

Manufacturing method for thin film of poly-crystalline silicon}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polycrystalline silicon thin film for use in a solar cell, and more particularly, to a method for effectively producing a polycrystalline silicon thin film of an amorphous silicon thin film by metal induction crystallization.

In general, most problems arising in the production of poly-silicon (poly-Si) are due to the use of glass substrates that are vulnerable at high temperatures, and the process temperature cannot be raised sufficiently to the temperature at which the amorphous silicon (a-Si) thin film is crystallized.

The process requiring high temperature heat treatment in the production of poly-Si is a crystallization heat treatment (Crystallization) that converts the amorphous silicon (a-Si) thin film to a crystalline silicon thin film and an activation heat treatment (Dopant) that is electrically activated after doping Activation).

At present, a variety of processes (LTPS: Low Temperature poly-Si) have been proposed for forming a polycrystalline silicon thin film in a short time at a low temperature that the glass substrate allows. Representative methods for forming a polycrystalline silicon thin film include solid phase crystallization (SPC), excimer laser annealing (ELA), and metal induced crystallization (MIC).

Solid Phase Crystallization (SPC) is the most direct and long used method of obtaining polycrystalline silicon (poly-Si) thin films from amorphous silicon (a-Si). SPC is a method of obtaining a polycrystalline silicon thin film having a grain size of about several micro by heat-treating the amorphous silicon thin film at a temperature of 600 ℃ or more for several tens of hours. The polycrystalline silicon thin film obtained by this method has a disadvantage in that it is difficult to use a glass substrate because of high defect density in crystal grains and a high heat treatment temperature, and a long process time due to long heat treatment.

Excimer Laser Annealing (ELA) is a method of instantaneously irradiating an excimer laser to a amorphous silicon thin film for nanoseconds to melt and recrystallize the amorphous silicon thin film without damaging the glass substrate.

However, ELA is known to have significant problems in mass production processes. ELA has a very non-uniform grain structure of polycrystalline silicon (poly-Si) thin film according to the laser irradiation amount. ELA has a problem that it is difficult to manufacture a uniform crystalline silicon thin film because of the narrow process range. In addition, the surface of the polycrystalline silicon thin film is rough, which adversely affects the characteristics of the device. This problem is more serious in the application of organic light emitting diodes (OLEDs) in which the uniformity of thin film transistors (TFTs) is important.

To overcome this problem, the proposed method is Metal Induced Crystallization (MIC). MIC is a method of inducing crystallization of silicon by applying a metal catalyst to amorphous silicon by sputtering or spin coating, followed by heat treatment at low temperature. As the metal catalyst, various metals such as nickel (Ni), copper (Cu), aluminum (Al), and palladium (Pd) may be used. In general, nickel (Ni) is used as a metal catalyst in MIC, in which reaction control is easy and large grains are obtained. MIC can be crystallized at a lower temperature of less than 450 ° C., but there are significant problems in the actual production process. This problem is that a significant amount of metal diffused in the active region in the TFT causes typical metal contamination, increasing leakage current, one of the TFT characteristics.

The development of Low Temperature Poly-Si (LTPS) has been carried out for the purpose of application to liquid crystal display devices. In addition, the need for development is increasing.

Inexpensive, high-productivity poly-Si fabrication methods will compete with amorphous silicon thin-film transistor liquid crystal displays (a-Si TFT LCDs) in the display family with many active organic light emitting diodes (AMOLEDs) in the market. It is important in that it is. The method of manufacturing polycrystalline silicon is also important in that active organic light emitting diodes (AMOLEDs) will compete with crystalline wafer forms in solar cells. Therefore, the production cost and market competitiveness of the product can be stably polycrystalline at a low price compared to an amorphous silicon thin film transistor liquid crystal display (a-Si TFT LCD) and a crystalline wafer type solar cell in which the production technology has reached a stabilization stage. It depends on whether you can make silicon.

1 schematically shows a manufacturing process for obtaining a polycrystalline silicon thin film from amorphous silicon by a metal induction crystallization method. Referring to FIG. 1, in the conventional process, a buffer layer 2 made of silicon oxide (SiO ₂ ) is formed on a substrate 1 such as glass, and an amorphous silicon layer 3 is formed on the buffer layer 2 by plasma chemical vapor deposition (PECVD). After forming by Plasma Enhanced Chemical Vapor Deposition, sputtering and coating a metal such as nickel (Ni) on the amorphous silicon layer (3) and then heat-treated by RTA (Rapid Thermal Annealing) at about 700 ℃ The crystalline silicon 4 is formed from the silicon layer 3. However, according to the conventional method, since it is difficult to precisely control the amount of the metal applied to the upper portion of the amorphous silicon layer 3, there is an inconvenience that it is necessary to remove the excessively applied metal. This process not only increases manufacturing costs but also adversely affects the quality of the crystallized silicon.

An object of the present invention is to solve the above problems, in the method of producing a polycrystalline silicon thin film using the metal induction crystallization method, by making it possible to crystallize at a low temperature to provide an efficient method for producing a polycrystalline silicon thin film. In providing.

In order to achieve the above object, a method of manufacturing a polycrystalline silicon thin film according to the present invention includes: forming a metal layer on an insulating substrate;

A first heat treatment step of forming a metal oxide film by heat-treating the metal layer formed in the metal layer forming step;

Forming a first silicon layer by laminating an amorphous silicon layer on the oxide film;

A second heat treatment step of forming a metal silicide oxidation catalyst film by heat-treating the oxide film and the first silicon layer;

Forming a second silicon layer by laminating amorphous silicon on the catalyst film;

Stacking on the second silicon layer to form a surplus metal absorbing layer that absorbs excess metal particles generated from the second silicon layer during heat treatment of the second silicon layer and blocks impurities from flowing into the second silicon layer from the outside. Forming a surplus metal absorbing layer;

A preliminary crystallization step of thermally treating the second silicon layer to produce crystalline silicon in the second silicon layer; And

Removing the excess metal absorbing layer to remove the excess metal absorbing layer after the preliminary crystallization step; There is a feature in that it includes.

Forming a third silicon layer by laminating an amorphous silicon layer on the crystallized second silicon layer after removing the excess metal absorbing layer;

Forming a blocking layer stacked on the third silicon layer to form a blocking layer which blocks impurities from flowing into the third silicon layer from the outside during the heat treatment of the third silicon layer;

A final crystallization step of thermally treating the third silicon layer after the blocking layer forming step to produce crystalline silicon; And

And a barrier layer removing step of removing the barrier layer after the final crystallization step.

The thickness of the metal layer is 5 kPa to 1500 kPa, the thickness of the oxide film is 1 kPa to 300 kPa, the thickness of the first silicon layer is 5 kPa to 1500 kPa, and the ratio of the thickness of the metal layer and the thickness of the first silicon layer is 1: 0.2 to 1: 6, the thickness of the second silicon layer is 5 kPa to 20000 kPa, the thickness of the excess metal absorbing layer and the blocking layer is 5 kPa to 20000 kPa, and the thickness of the third silicon layer is 5 kPa to 20000 kPa. Do.

The excess metal absorbing layer or the blocking layer is preferably made of any one of a nitride of silicon, an oxide of silicon, a fluorine compound.

The heat treatment temperature in the first heat treatment step is 50 ℃ to 1000 ℃, the heat treatment temperature in the second heat treatment step is preferably 50 ℃ to 1000 ℃.

After the metal layer forming step, the first silicon layer forming step may be performed after the patterning step of removing a portion of the metal layer by a photolithography method.

The amorphous silicon stacked in the second silicon layer forming step or the third silicon layer forming step may be substituted with amorphous silicon germanium (SiGe) or amorphous silicon carbide (SiC).

The method of manufacturing a polycrystalline silicon thin film according to the present invention has an effect of providing a polycrystalline silicon thin film that can be applied to a flat panel display device and a solar cell by enabling improved crystallization at a lower temperature than a conventional metal induced crystallization method.

1 is a view for explaining a conventional method for producing a polycrystalline silicon thin film by a metal induction crystallization method.
2 is a view showing a manufacturing process according to a preferred embodiment of the present invention.
3 is a view showing a cross section after the first heat treatment step shown in FIG.
FIG. 4 is a cross-sectional view after the first silicon layer forming step illustrated in FIG. 2.
5 is a view showing a cross section after the second heat treatment step shown in FIG.
FIG. 6 is a view showing a cross section after the excess metal absorbing layer forming step illustrated in FIG. 2.
7 is a view showing a cross section after the preliminary crystallization step shown in FIG. 2.
8 is a view showing a cross section after the step of removing the excess metal absorbing layer shown in FIG.
9 is a view showing a cross section after the blocking layer forming step shown in FIG.
FIG. 10 shows a cross section after the final crystallization step shown in FIG. 2.
FIG. 11 is a cross-sectional view after the barrier layer removing step illustrated in FIG. 2.
12 is a photograph of the surface of amorphous silicon as viewed under an optical microscope.
FIG. 13 is a graph analyzing the wave number of the amorphous silicon illustrated in FIG. 12.
14 is a photograph of the surface of a crystalline silicon wafer viewed with an optical microscope.
FIG. 15 is a graph analyzing the wave number of the silicon wafer illustrated in FIG. 14.
16 is a photograph of a surface of a polycrystalline silicon thin film manufactured by a conventional metal induction crystallization method viewed with an optical microscope.
FIG. 17 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 16.
18 is a photograph of the surface of the polycrystalline silicon thin film prepared according to the present invention under an optical microscope.
19 is a graph analyzing the wave number of the polycrystalline silicon thin film shown in FIG. 18.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view for explaining a conventional method for producing a polycrystalline silicon thin film by a metal induction crystallization method. 2 is a view showing a manufacturing process according to a preferred embodiment of the present invention. 3 is a view showing a cross section after the first heat treatment step shown in FIG. FIG. 4 is a cross-sectional view after the first silicon layer forming step illustrated in FIG. 2. 5 is a view showing a cross section after the second heat treatment step shown in FIG. FIG. 6 is a view showing a cross section after the excess metal absorbing layer forming step illustrated in FIG. 2. 7 is a view showing a cross section after the preliminary crystallization step shown in FIG. 2. 8 is a view showing a cross section after the step of removing the excess metal absorbing layer shown in FIG. 9 is a view showing a cross section after the blocking layer forming step shown in FIG. FIG. 10 shows a cross section after the final crystallization step shown in FIG. 2. FIG. 11 is a cross-sectional view after the barrier layer removing step illustrated in FIG. 2.

2 to 11, a method of manufacturing a polycrystalline silicon thin film (hereinafter, referred to as a “manufacturing method”) according to a preferred embodiment of the present invention includes a metal layer forming step S1, a first heat treatment step S2, The first silicon layer forming step (S3), the second heat treatment step (S4), the second silicon layer forming step (S5), the surplus metal absorbing layer forming step (S6), the preliminary crystallization step (S7), and the surplus The metal absorbing layer removing step S8, the third silicon layer forming step S9, the blocking layer forming step S10, the final crystallization step S11, and the blocking layer removing step S12 are included.

In the metal layer forming step S1, a metal layer 30 such as nickel (Ni) is formed on an insulating substrate 10 such as glass. The substrate 10 includes a buffer layer 20 made of a material such as silicon nitride (SiN) or silicon oxide (SiO ₂ ). The buffer layer 20 is provided to serve as an insulation function. In addition, the buffer layer 20 may include a first silicon layer 50 or a second layer, which will be described later, from the substrate 10 in a second heat treatment step S4, a preliminary crystallization step S7, or a final crystallization step S11. In order to prevent impurities from being diffused in the silicon layer 60 or the third silicon layer 70, the impurities are contaminated in the first silicon layer 50, the second silicon layer 60, or the third silicon layer 70. It is prepared. The metal layer 30 may be performed by a known method such as sputtering or plasma chemical vapor deposition (PECVD). It is preferable that the thickness of the said metal layer 30 is 5 kPa-1500 kPa. If the thickness of the metal layer 30 is less than 5Å, the thickness of the metal layer 30 is so thin that the process reproducibility deteriorates, and the problem of deterioration in uniformity of the metal layer 30 when deposited in a large area. have. On the other hand, when the thickness of the metal layer 30 exceeds 1500 kPa, too much metal penetrates into the second silicon layer 60, which will be described later, so that a problem of contamination of the metal may occur, thereby preliminary crystallization step (S7) and final crystallization described later. There is a problem of degrading the characteristics of a device including polycrystalline silicon formed in step S11. After the metal layer forming step S1, a patterning step of removing a portion of the metal layer 30 by a photolithography method may be performed. If necessary, the patterning step can be omitted. The patterning step is to uniformly distribute the growth nucleus of the crystalline silicon.

In the first heat treatment step S2, the metal layer 30 formed in the metal layer forming step S1 is heat-treated to form a metal oxide film 40. The heat treatment temperature in the first heat treatment step (S2) is preferably 50 ℃ to 1000 ℃. If the heat treatment temperature of the first heat treatment step (S2) is less than 50 ℃ there is a problem that the oxide of nickel (Ni) is not well formed. On the other hand, when the heat treatment temperature of the first heat treatment step (S2) exceeds 1000 ℃ problem occurs that the glass substrate (10) is deformed or broken by thermal shock. The heat treatment method of the first heat treatment step S2 may be a high temperature furnace, a metal heat treatment (RTA), an ultraviolet (UV) heating method, or the like. The oxide film 40 serves to lower the activation energy during diffusion of the catalyst metal in the process of forming the metal silicide oxidation catalyst film 55 in the second heat treatment step S4 described later. The oxide film 40 preferably has a thickness of 1 kPa to 300 kPa. When the thickness of the oxide film 40 is less than 1 mm, it is difficult to implement the process and the overall thickness uniformity is poor. When the thickness of the oxide film 40 is greater than 300 GPa, there is a problem in that a chemical bond that is not necessary to form the metal silicide oxidation catalyst film 55 is generated due to the thick oxide film.

In the first silicon layer forming step (S3), an amorphous first silicon layer 50 is formed on the oxide layer 40 by using a known means such as plasma chemical vapor deposition. It is preferable that the thickness of the said 1st silicon layer 50 is 5 kPa-1500 kPa. In the case where the thickness of the first silicon layer 50 is less than 5 mm, the thickness of the first silicon layer 50 is so thin that process reproducibility deteriorates and the uniformity of the first silicon layer 50 when deposited in a large area. There is a problem of poor uniformity. On the other hand, when the thickness of the first silicon layer 50 exceeds 1500Å, the first silicon layer 50 is not required to form the metal silicidation catalyst film 55 in combination with the metal layer 30. There is a problem that chemical bonds are produced. In addition, the ratio of the thickness of the metal layer 30 and the thickness of the first silicon layer 50 is preferably 1: 0.2 to 1: 6. When the ratio of the thickness of the metal layer 30 and the thickness of the first silicon layer 50 is out of the above range, as described above, chemical bonds that are not necessary to form the metal silicidation catalyst film 55 are generated. There is this. In other words, a chemical bond of a composition other than the metal silicide composition required for metal inductive bonding is formed, which hinders inductive crystallization.

In the second heat treatment step S4, the oxide film 40 and the first silicon layer 50 are heat-treated to form a metal silicide oxidation catalyst film 55. The catalyst layer 55 is generated by the particles of the metal layer 30, the oxide layer 40, and the first silicon layer 50 being moved and chemically bonded by thermal energy. That is, a catalyst metal atom, such as nickel (Ni), moves from the metal layer 30 to the first silicon layer 50 to combine with oxygen transferred from the oxide film 40 to form a metal silicide oxidation catalyst film 55 (NiSiO). To form. The heat treatment performed in the second heat treatment step S4 may be performed by a high temperature furnace, rapid heat treatment (RTA), ultraviolet (UV) heating, or the like. The metal silicidation catalyst film 55 formed in the second heat treatment step S4 serves as a nucleus for crystallizing the second silicon layer 60 in a preliminary crystallization step S7 described later. The heat treatment temperature in the second heat treatment step (S4) is preferably 50 ℃ to 1000 ℃. If the heat treatment temperature of the second heat treatment step (S4) is less than 50 ℃ there is a problem that the oxide of nickel (Ni) is not formed well. When the heat treatment temperature of the second heat treatment step S4 exceeds 1000 ° C., the substrate 10 made of glass is deformed or damaged by thermal shock.

In the second silicon layer forming step (S5), the second silicon layer 60 is formed by stacking amorphous silicon on the catalyst film 55. The method of forming the second silicon layer 60 may be performed using a method such as a known plasma chemical vapor deposition method. The thickness of the second silicon layer 60 is preferably 5 kPa to 20,000 kPa. In the case where the thickness of the second silicon layer 60 is less than 5 mm, the problem is that the thickness is so thin that the process reproducibility deteriorates and that the uniformity of the second silicon layer 60 deteriorates when deposited in a large area. have. When the thickness of the second silicon layer 60 exceeds 20000 GPa, the second silicon layer 60 is too thick to absorb excess metal particles generated from the second silicon layer 60, so that the surplus metal absorbing layer 75 of the subsequent process is crystallized during heat treatment. There is a problem that it is difficult to sufficiently absorb and remove the extra metal particles that do not participate in. That is, it is preferable to remove in advance the excess metal particles which are not absorbed, since they cause leakage current to degrade the performance of the device. For this purpose, it is possible to stabilize the structure of the third silicon layer 70 crystallized by the excess metal absorption layer 75 to be described later to the excess metal particles generated in the second silicon layer 60.

In the excess metal absorbing layer forming step (S6), the excess metal absorbing layer 75 is stacked on the second silicon layer 60. The excess metal absorbing layer 75 serves to absorb excess metal particles generated from the second silicon layer during heat treatment of the second silicon layer and to block impurities from flowing into the second silicon layer from the outside. The excess metal absorbing layer 75 may be formed of any one of a nitride of silicon (SiN), an oxide of silicon (SiO ₂ ), and a fluorine compound (CaF ₂ , LaF ₃ , MgF ₂ ). It is preferable that the thickness of the said excess metal absorption layer 75 is 5 kPa-20000 kPa. When the thickness of the excess metal absorbing layer 75 is less than 5 mm, the thickness is too thin, so that the process reproducibility is poor and the uniformity of the excess metal absorbing layer 75 is degraded when deposited in a large area. If the thickness of the excess metal absorbing layer 75 exceeds 20000Å, the process takes a long time and there is a problem that the thin film may be peeled off. The excess metal absorbing layer 75 also serves to absorb extra metal particles that do not participate in crystallization during the heat treatment of the first silicon layer 50.

In the preliminary crystallization step S7, heat treatment is performed such that crystalline silicon 80 is generated in the amorphous second silicon layer 60 through the metal particles of the catalyst film 55. The heat treatment in the crystallization step (S7) is performed at 630 ° C using Rapid Thermal Annealing (RTA) equipment.

The excess metal absorbing layer removing step S8 removes the excess metal absorbing layer 75 after the preliminary crystallization step S7. The method of removing the excess metal absorbing layer 75 may use a chemical method such as etching or a physical method such as grinding.

In the third silicon layer forming step S9, after the removal of the excess metal absorbing layer S8, the third silicon layer 70 is formed by stacking an amorphous silicon layer on the crystalline silicon 80 in which the second silicon layer 60 is crystallized. ). The method of forming the third silicon layer 70 is similar to the method of forming the second silicon layer 60. It is preferable that the thickness of the said 3rd silicon layer 70 is 5 kPa-20000 kPa. In the case where the thickness of the third silicon layer 70 is less than 5 mm, there is a problem that the thickness is too thin, so that the process reproducibility is bad and that the uniformity of the third silicon layer 70 deteriorates when deposited in a large area. . If the thickness of the third silicon layer 70 exceeds 20000Å, the process may take a long time and the thin film may be peeled off.

The blocking layer forming step (S10) may be stacked on the third silicon layer 70 to block impurities from flowing into the third silicon layer 70 from the outside during the heat treatment of the third silicon layer 70. Form 77. The blocking layer 77 may be formed of any one of an oxide of silicon (SiO ₂ ), a nitride of silicon (SiN), and a fluorine compound of silicon (CaF ₂ , LaF ₃ , and MgF ₂ ). The thickness of the barrier layer 77 is preferably 5 kPa to 20,000 kPa. When the thickness of the barrier layer 77 is less than 5 μs, there is a problem that the thickness is too thin, so that the process reproducibility is poor and that the uniformity of the barrier layer 77 is degraded when the barrier layer 77 is deposited on a large area. On the other hand, when the thickness of the blocking layer 77 exceeds 20000Å, the process takes a long time and there is a problem that the thin film may be peeled off.

In the final crystallization step (S11), after the blocking layer forming step (S10), the third silicon layer 70 is heat-treated to generate crystalline silicon from the third silicon layer 70. The crystalline silicon 80 produced from the third silicon layer 70 is produced using the crystalline silicon 80 crystallized from the second silicon layer 60 as a growth nucleus. In this process, the blocking layer 77 serves to block impurities from flowing into the third silicon layer 70 from the outside during the crystallization of the third silicon layer 70. The crystalline silicon formed in the final crystallization step S11 is the same as the crystalline silicon formed in the step S7 for the preliminary crystallization. However, since the crystal grains are grown in the final crystallization step, the crystalline silicon particles formed in the preliminary crystallization step are relatively larger than the size of the crystal grains of the crystalline silicon particles formed in the final crystallization step, and the surface state of the crystal grains may be slightly changed. . This will be obvious to those of ordinary skill in the art.

In the barrier layer removing step S12, the barrier layer 77 is removed after the final crystallization step S11. The barrier layer 77 may be removed by using a chemical method such as etching or a physical method such as grinding.

The amorphous silicon stacked in the second silicon layer forming step S5 or the third silicon layer forming step S9 may be replaced with amorphous silicon germanium (SiGe) or amorphous silicon carbide (SiC).

In order to analyze the crystallization state of the polycrystalline silicon thin film manufactured by such a manufacturing method, the size of the crystal grains was observed by using an optical microscope and Raman Spectroscopy, and the wave number having the maximum intensity was analyzed.

12 is a photograph of the surface of amorphous silicon as viewed under an optical microscope. FIG. 13 is a graph analyzing the wave number of the amorphous silicon illustrated in FIG. 12. 14 is a photograph of the surface of a crystalline silicon wafer viewed with an optical microscope. FIG. 15 is a graph analyzing the wave number of the silicon wafer illustrated in FIG. 14. 16 is a photograph of a surface of a polycrystalline silicon thin film manufactured by a conventional metal induction crystallization method viewed with an optical microscope. FIG. 17 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 16. 18 is a photograph of the surface of the polycrystalline silicon thin film prepared according to the present invention under an optical microscope. 19 is a graph analyzing the wave number of the polycrystalline silicon thin film shown in FIG. 18.

12 and 13, the second silicon layer 60 and the third silicon layer 70, which are amorphous silicon, exhibit maximum intensity at a wave number of 480 cm ⁻¹ . In FIG. 13, the horizontal axis represents a wave number (cm ⁻¹ ) and corresponds to a frequency. Wave number is a unit of frequency that represents the number of waves in unit distance by dividing the frequency of light by the speed of light in atomic, molecular, and nuclear spectroscopy. In other words, the frequency of a wave is represented by the Greek letter ν (nu), which is equal to the luminous flux c divided by the wavelength λ. That is, ν〓c / λ. In the visible region of the spectrum, a typical spectral line is a wavelength of 5.8 × 10 −5 cm and corresponds to a frequency of 5.17 × 10 14 kHz. However, because such a frequency has a value that is too large, it is convenient to divide the number by the speed of light to reduce the size. The frequency divided by the speed of light is ν / c, which is 1 / λ in the above equation. When the wavelength is measured in m, 1 / λ represents the number of waves found within 1m. The wavenumber is usually measured in units of 1 / m, i.e. m ^{- 1} and 1 / cm, i.e. cm- ¹ .

In FIG. 13, the vertical axis represents a sum of wave numbers measured per unit time and corresponds to intensity (CPS, Count Per Second). The units of the horizontal axis and the vertical axis of FIGS. 15, 17, and 19 are the same as in FIG. 13. In contrast, silicon wafers, which are typical crystalline silicon, exhibit maximum strength at a wavenumber of 520 cm ⁻¹ as shown in FIGS. 14 and 15. 16 and 17 show surface photographs and wave number analysis graphs of a polycrystalline silicon thin film manufactured by a conventional metal induction crystallization method. Referring to FIGS. 16 and 17, the maximum strength is exhibited at a similar frequency compared to the crystalline silicon wafers shown in FIGS. 14 and 15. By the way, it can be seen that the optical micrograph of the surface of the silicon thin film shown in FIG. 16 is enlarged by 1000 times and the size of the crystal grains is relatively small.

Meanwhile, optical micrographs and wave number analysis graphs of the polycrystalline silicon thin film manufactured by the present invention are shown in FIGS. 18 and 19, respectively. Referring to FIG. 19, it can be seen that the wave number representing the maximum strength in the polycrystalline silicon thin film manufactured by the present invention is well represented as in the crystalline silicon wafer shown in FIG. 15. In addition, FIG. 18 is an optical micrograph of 1000 times magnification. Comparing FIG. 18 with FIG. 16, the grains of the polycrystalline silicon thin film manufactured by the present invention are much larger than those of the polycrystalline silicon thin film manufactured by the conventional method. Able to know. From the experimental results, it can be seen that the manufacturing method of the polycrystalline silicon thin film according to the present invention is superior to the conventional manufacturing method. In addition, the manufacturing method of the polycrystalline silicon thin film according to the present invention has the advantage that it can be crystallized at a lower temperature than the conventional manufacturing method.

While the present invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not to be limited by the example, and various changes and modifications may be made without departing from the spirit and scope of the invention.

10 substrate 20 buffer layer
30 metal layer 40 oxide film
50 first silicon layer 55 catalyst film
60 ... second silicon layer 70 ... third silicon layer
75 ... excess metal absorbing layer 77 ... barrier layer
S1 ... metal layer forming step S2 ... first heat treatment step
S3 ... first silicon layer forming step S4 ... second heat treatment step
S5 ... second silicon layer forming step S6 ... surplus metal absorbing layer forming step
S7 ... preliminary crystallization step S8 ... removal of excess metal absorber layer
S9 ... 3rd silicon layer forming step S10 ... blocking layer forming step
S11 ... final crystallization step S12 ... barrier layer removal step

Claims (7)

A metal layer forming step of forming a metal layer on the insulating substrate;
A first heat treatment step of forming a metal oxide film by heat-treating the metal layer formed in the metal layer forming step;
Forming a first silicon layer by laminating an amorphous silicon layer on the oxide film;
A second heat treatment step of forming a metal silicide oxidation catalyst film by heat-treating the oxide film and the first silicon layer;
Forming a second silicon layer by laminating amorphous silicon on the catalyst film;
Stacking on the second silicon layer to form a surplus metal absorbing layer that absorbs excess metal particles generated from the second silicon layer during heat treatment of the second silicon layer and blocks impurities from flowing into the second silicon layer from the outside. Forming a surplus metal absorbing layer;
A preliminary crystallization step of thermally treating the second silicon layer to produce crystalline silicon in the second silicon layer; And
And removing the excess metal absorbing layer to remove the excess metal absorbing layer after the preliminary crystallization step. The method of claim 1,
Forming a third silicon layer by laminating an amorphous silicon layer on the crystallized second silicon layer after removing the excess metal absorbing layer;
Forming a blocking layer stacked on the third silicon layer to form a blocking layer which blocks impurities from flowing into the third silicon layer from the outside during the heat treatment of the third silicon layer;
A final crystallization step of thermally treating the third silicon layer after the blocking layer forming step to produce crystalline silicon; And
And a blocking layer removing step of removing the blocking layer after the final crystallization step. The method of claim 2,
The thickness of the metal layer is 5 kPa to 1500 kPa, the thickness of the oxide film is 1 kPa to 300 kPa, the thickness of the first silicon layer is 5 kPa to 1500 kPa, and the ratio of the thickness of the metal layer and the thickness of the first silicon layer is 1: 0.2 to 1: 6, the thickness of the second silicon layer is 5 kPa to 20000 kPa, the thickness of the excess metal absorbing layer and the blocking layer is 5 kPa to 20000 kPa, and the thickness of the third silicon layer is 5 kPa to 20000 kPa. A method for producing a polycrystalline silicon thin film. The method of claim 2,
The surplus metal absorbing layer or the blocking layer is a method of manufacturing a polycrystalline silicon thin film, characterized in that made of any one of nitride of silicon, oxide of silicon, fluorine compound. The method of claim 1,
The heat treatment temperature in the first heat treatment step is 50 ℃ to 1000 ℃, the heat treatment temperature in the second heat treatment step is a method for producing a polycrystalline silicon thin film, characterized in that 50 to 1000 ℃. The method of claim 1,
And a first silicon layer forming step after the patterning step of removing a portion of the metal layer by a photolithography method after the metal layer forming step. The method of claim 2,
Amorphous silicon laminated in the second silicon layer forming step or the third silicon layer forming step is a method of manufacturing a polycrystalline silicon thin film, characterized in that substituted with amorphous silicon germanium (SiGe) or amorphous silicon carbide (SiC).

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