KR101061792B1 - Chip embedded printed circuit board and manufacturing method - Google Patents

Abstract

An upper circuit pattern and a lower circuit pattern are formed on each of the upper carrier and the lower carrier, the chip is mounted on the upper circuit pattern, an intermediate insulating layer is introduced, and the upper carrier is embedded in the intermediate insulating layer. And a method of manufacturing a chip embedded printed circuit board which bonds a lower carrier and removes the upper carrier and the lower carrier so that the back surfaces of the upper and lower circuit patterns are exposed.

PCB, MSAP, Embedded, IC chip, Bump

Description

PCB having embedded chip and manufacturing method for the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuit devices, and more particularly, to an embedded chip printed circuit board (PCB) and a manufacturing method in which an integrated circuit chip (IC chip) is embedded in a printed circuit board.

With the miniaturization of electronic devices, electronic components are becoming more functional and more compact. In particular, in order to reduce the thickness of a portable terminal device such as a mobile phone or a portable computer, there is a great demand for reducing the thickness of components mounted thereon. In order to reduce the size of components, there is an increasing demand for reducing the thickness of a component package, and a demand for implementing a high function by mounting a plurality of integrated circuit chips for multifunction in one component package is increasing. To this end, the development of component package technologies such as chip embedded printed circuit boards in which chips are embedded between upper and lower printed circuit boards. In the chip embedded printed circuit board technology, by embedding the chip between the boards, it is possible to miniaturize the whole packaged parts, and to improve the electrical characteristics by increasing the mounting density of the parts and improving the high frequency characteristics. .

The chip embedded printed circuit board includes an integrated circuit chip, which is an active element, between the substrates, presses the substrate in the state where the chip is embedded, mounts the chip, and then performs a printed circuit board (PCB) process. Is being manufactured. After chip mounting, drilling for electrical connection between chip and external circuit pattern, circuit pattern formation process through copper plating and image transfer process on the exposed surface of the substrate are performed. have.

If an error or a defect is caused in the PCB process performed after chip mounting, the result of the chip embedded printed circuit board manufactured regardless of whether the mounted active device chip is defective may be defectively processed. As a result of poor PCB process following chip mounting, expensive active device chips are undesirably discarded, causing an undesired increase in the cost of manufacturing chip embedded printed circuit boards. In addition, since chip mounting is preceded and damage to chips mounted therein must be suppressed, many restrictions may be caused in a process of forming a printed circuit pattern on a subsequent substrate. As a result, difficulty in forming a high density printed circuit pattern may be caused, and in addition, constraints may be caused in embedding various kinds of active device chips.

The present invention is to provide a chip-embedded printed circuit board and a manufacturing method which can suppress the damage or loss of the chip to be embedded by the defect that can be caused in the process of forming a circuit pattern of the printed circuit board.

One aspect of the invention, forming an upper circuit pattern and a lower circuit pattern on each of the upper carrier (carrier) and the lower carrier; Mounting a chip on the upper circuit pattern of the upper carrier; Introducing an intermediate insulating layer on the lower circuit pattern of the lower carrier; Introducing the upper carrier onto the lower carrier such that the chip faces the intermediate insulating layer; Bonding the upper carrier and the lower carrier so that the chip is embedded in the intermediate insulating layer; And removing the upper carrier and the lower carrier to expose the back surfaces of the upper and lower circuit patterns to provide a chip embedded printed circuit board manufacturing method.

Another aspect of the invention, forming an upper circuit pattern and a lower circuit pattern on each of the upper carrier (carrier) and the lower carrier; Mounting a chip on the upper circuit pattern of the upper carrier; Forming a via bump on the lower circuit pattern of the lower carrier; Introducing an intermediate insulating layer on the lower carrier having the via bumps formed thereon; Introducing the upper carrier onto the lower carrier such that the chip faces the intermediate insulating layer; Bonding the upper carrier and the lower carrier to recess the chip and the via bump to connect the lower circuit pattern and the upper circuit pattern to the intermediate insulating layer; And removing the upper carrier and the lower carrier to expose the back surfaces of the upper and lower circuit patterns to provide a chip embedded printed circuit board manufacturing method.

Another aspect of the present invention, the chip is recessed embedded intermediate insulation layer; Upper and lower circuit patterns formed on upper and lower surfaces of the intermediate insulating layer; And a solder mask insulated between the adjacent circuit patterns and having an exposed surface having a surface height equivalent to that of the circuit pattern and having a protruding portion recessed in the intermediate insulating layer. Presents an embedded printed circuit board.

The forming of the circuit pattern may include introducing the upper carrier and the lower carrier on which a carrier resin layer, a carrier metal layer, and a base metal layer are laminated, respectively, by bonding a release layer in the middle so that the carrier resin layers face each other. step; Performing pattern plating on each of the base metal layers sequentially to form the upper and lower circuit patterns; And forming a solder mask to isolate between the upper and lower circuit patterns.

The pattern plating may be performed including a modified semi-additive method (MSAP).

Prior to mounting the chip, the method may further include performing a pattern check on the circuit pattern to select the carrier having a normal circuit pattern in which no pattern failure occurs.

The chip may be connected to a connection part including a solder on pad (SOP), an anisotropic conductive film (ACF), or wire bonding in the upper circuit pattern.

The chip may be introduced into an active device including the integrated circuit (IC) device.

The chip may be introduced into a passive device including the capacitor, inductor or resistor device.

The via bumps may be formed in a cone shape to expose a tip through the intermediate insulating layer using the conductive paste.

The intermediate insulating layer may be introduced into a laminate substrate or prepreg substrate of an insulating resin.

Forming a protective film on a part of the back surface of the exposed upper and lower circuit patterns; And performing surface treatment on the other part of the back surface of the exposed upper and lower circuit patterns.

Embodiments of the present invention can provide a chip-embedded printed circuit board and a manufacturing method which can suppress the damage or loss of the chip to be embedded by the defect that can be caused in the process of forming a circuit pattern of the printed circuit board. Prior to embedding the chip, a process of forming a circuit pattern of a printed circuit board is performed, and a test process of confirming whether a formed circuit pattern is defective is performed. Thus, a chip is formed between substrates having a normally formed circuit pattern. It can be built. Therefore, damage to the chip during the circuit pattern formation process can be suppressed, and the chip can be prevented from being discarded or lost due to defective circuit pattern, thereby effectively reducing the cost of manufacturing the chip embedded printed circuit board. Can be implemented.

1 to 13 are views for explaining a chip embedded printed circuit board and a manufacturing method according to an embodiment of the present invention.

Referring to FIG. 1, a carrier 110 having a base metal layer 115 and 125 on which one side of a base metal layer 115 and 125 to be subjected to pattern plating, such as a modified semi additive process (MSAP), is formed. 120). Carriers 110 and 120 are formed with carrier metal layers 113 and 123 on carrier resin layers 111 and 121, and base metal layers 115 and 125 for plating on carrier metal layers 113 and 123. It is formed into a formed film (film) shape. The upper carrier 110 is prepared for the upper circuit pattern of the chip embedded printed circuit board, the lower carrier 120 is prepared for the lower circuit pattern, and the upper and lower carriers 110 and 120 are formed of a release layer in the form of a film. It is bonded via 130 and treated as one carrier (110, 120).

The upper base metal layer 115 of the upper carrier 110 or the lower base metal layer 125 of the lower carrier 120 is formed of a thin copper (Cu) layer having a thickness of 3 μm or less useful for the MSAP process. The upper and lower carrier metal layers 113 and 123 supporting the base metal layers 115 and 125 may be formed of a material equivalent to the base metal layers 115 and 125, for example, a copper layer, to be etched away in a subsequent process. . In this case, the carrier metal layers 113 and 123 may be formed to have a thickness of about 18 μm. The upper and lower carrier resin layers 111 and 121 may be formed of an insulating material as a carrier body to be peeled off in a subsequent process.

Referring to FIG. 2, an upper circuit pattern 210 and a lower circuit pattern 220 are formed by performing an MSAP process on the base metal layers 115 and 125. The base metal layers 115 and 125 are used as seed layers, and dry films (not shown) are formed on the base metal layers 115 and 125, and exposed and developed to perform circuit patterns. It is possible to form a pattern corresponding to the image of. Exposure may be sequentially performed on the upper and lower base metal layers 115 and 125 positioned on the upper and lower surfaces of the carriers 110 and 120, respectively. By patterning the dry film, the time required for the entire imaging process can be reduced. After the formation of the circuit patterns 210 and 220 by forming a pattern plating process such as copper plating on portions of the base metal layers 115 and 125 exposed to the dry film, the dry film is peeled off and removed. The upper circuit pattern 210 is. A chip pad 211 connected to the carrier and a via upper pad 213 to which a via is connected may be included. The lower circuit pattern 220 may include a wiring pattern 221 and a via. It may include a via bottom pad 223 to be connected.

Referring to FIG. 3, a solder mask 300 that isolates the circuit patterns 210 and 220 may be formed by applying a solder resist and an exposure developing process.

A pattern inspection process is performed to determine whether a pattern defect is caused during the formation of the solder mask 300 or the formation of the circuit patterns 210 and 220. The case where the pattern defect is caused by the pattern inspection process is filtered out and the subsequent chip insertion process is performed only when the circuit patterns 210 and 220 and the solder mask 300 are normally formed. As such, by performing an image process such as MSAP forming the circuit patterns 210 and 220 and a process of forming the solder mask 300 prior to the insertion of the chip to be embedded, it may be accompanied when the circuit pattern is formed after the chip insertion. Failure problems or the chips being discarded when such failures occur can be prevented. Since the chip embedding process is performed only when the circuit patterns 210 and 220 and the solder mask 300 are normally formed, the chip having a relatively high unit cost is discarded undesirably due to defects such as the circuit patterns 210 and 220 and is printed on the chip. A reduction in manufacturing costs can be realized by effectively preventing or suppressing an increase in circuit board manufacturing costs.

Referring to FIG. 4, the release layer 130 is peeled off to separate the upper carrier 110 and the lower carrier 120 from each other.

Referring to FIG. 5, a chip connection part 310 is formed on the chip pad 211 of the upper circuit pattern 210 of the upper carrier 110 for electrical connection between the chip and the circuit pattern 210. Prior to forming the chip connection 310, a surface treatment to prevent oxidation on the chip pad 211 may be performed, for example, an organic solderability preservative (OSP), ENIG, or direct immersion gold (DIG). One surface modification layer 270 is induced to be formed. The chip connector 310 may be formed on the first surface modification layer 270 by performing a solder on pad (SOP) process. The chip connector 310 may be formed using solder paste, solder ball, solder bump, anisotropic conductive film (ACF), or wire bonding.

Referring to FIG. 6, the chip 400 is mounted on the chip connector 310. The chip 400 may be an active device such as an integrated circuit (IC) device, or may be a passive device such as a capacitor, an inductor, or a resistor.

Referring to FIG. 7, via bumps 330 are formed on the lower via pad 223 of the lower circuit pattern 220 of the lower carrier 120 by using a conductive paste. In this case, the via bump 330 may be formed into an initial shape of a cone shape having a sharp tip 331 through printing. The via bumps 330 are formed in a conical shape more easily when penetrating the intermediate insulating layer that insulates the chips 400 and the like in the subsequent compression bonding process.

Referring to FIG. 8, an intermediate insulating layer 500 is formed on the solder mask 300 of the lower carrier 120. In this case, the intermediate insulation layer 500 is formed to cover the via bumps 330, and the tip 331 of the via bumps 330 is exposed to the outside. Further, a process of etching away a part of the thickness of the intermediate insulating layer 500 may be further introduced to expose the tip 331 of the via bump 330. The intermediate insulating layer 500 may be introduced into a prepreg substrate or a laminate substrate made of an insulating resin.

Referring to FIG. 9, the upper carrier 110 is introduced on the lower carrier 120 so that the via upper pad 213 of the upper circuit pattern 210 faces the tip 331 of the via bump 330. Afterwards, the upper carrier 110 and the lower carrier 120 are adhesively bonded by pressing and heating to allow the chip 400 to be embedded in the intermediate insulating layer 500. By pressing and heating, the resin of the intermediate insulating layer 500 is cured to bond the upper and lower carriers 110 and 120. By pressing, the tip 331 of the via bump 330 is connected and bonded to the via upper pad 213 to form a final via bump 332 electrically connecting the upper circuit pattern 210 and the lower circuit pattern 220. do.

In the embodiment of the present invention, since the via is formed using the via bump 332, the plating process performed after the formation of the through hole or the formation of the through hole may be effectively omitted.

Referring to FIG. 10, the carrier metal layers 113 and 123 and the carrier resin layers 111 and 121 are separated and removed.

Referring to FIG. 11, flash etching may be performed to expose the surfaces of the circuit patterns 210 and 220 by removing the base metal layers 115 and 125. By removing the base metal layers 115 and 125, the circuit patterns 210 and 220 are separated from each other and are insulated from each other by the solder mask 300 therebetween. In the embodiment of the present invention, since the formation of the circuit patterns 210 and 220 is performed before the embedded process of the chip 400, the surface of the solder mask 300 and the surface of the circuit patterns 210 and 220 exposed to the outside are formed. This has a substantially equivalent surface height. Therefore, the outer upper and lower surfaces of the manufactured chip embedded printed circuit board have a substantially flat surface.

Since the solder mask 300 and the circuit patterns 210 and 220 do not have a substantial height difference, and a flat surface is realized, it may be easier to perform a subsequent process on the outer surface of the resulting chip embedded printed circuit board. When the resulting chip-embedded printed circuit boards are laminated to each other, it is possible to prevent the protrusion of the solder mask 300 from acting as a factor that hinders the process. In addition, the surface of the circuit patterns 210 and 220 may be lower than the surface of the solder mask 300 by adjusting the execution time of the flash etching. A portion of the solder mask 300 protruding may face the intermediate insulating layer 500, and may be recessed into the intermediate insulating layer 500, thereby inducing a thickness of the entire chip embedded printed circuit board even thinner. Accordingly, the thickness of the electronic device employing the chip-embedded printed circuit board can also be made thinner.

Referring to FIG. 12, a portion of the circuit patterns 210 and 220 exposed to the outside of the manufactured chip embedded printed circuit board to be connected to an external device (not shown), for example, a via upper pad 213 and a via lower pad. The protective film 600 is formed in the region except the portion 223. The protective film 600 serves to electrically and chemically protect the exposure circuit from the outside. At this time, since the surface height of the solder mask 300 and the circuit patterns 210 and 220 are substantially equal, the surface of the printed circuit board is flat, so that the protective film 600 may be printed or coated with a film or coated with an insulating material. It can be formed by applying the same various methods.

Referring to FIG. 13, surface treatment or aging for inducing a second surface modification layer 700 to exposed surfaces of a portion to be connected to an external device, for example, a via upper pad 213 and a via lower pad 223. Perform the process. The second surface modification layer 700 is surface treated to include nickel gold (NiAu), nickel palladium gold (NiPdAu), gold (Au), silver (Ag), or tin (Sn) or OSP (Organic solderability preservative) Can be processed.

In the chip embedded printed circuit board according to the exemplary embodiment of the present invention, after the circuit patterns 210 and 220 are formed on the upper and lower carriers 110 and 120, the chip 400 is mounted and the upper and lower carriers 110 and 120 are formed. 120 is formed by pressing. Accordingly, before the chip 400 is mounted, between the upper and lower carriers 110 and 120 on which the circuit patterns 210 and 220 are determined to be in a normal state by checking whether the circuit patterns 210 and 220 are defective. The chip 400 may be embedded in the chip. As a result, defects in the circuit patterns 210 and 220 may be selected in advance, and chip and lower losses due to defects in the PCB process itself, such as defects in the circuit patterns 210 and 220, may be suppressed in advance. The chip and bottom loss or the chip and bottom caso can be prevented in advance, thereby reducing the cost required to manufacture the chip embedded printed circuit board. In addition, since the upper circuit pattern 210 and the lower circuit pattern 220 are connected to the via bumps 332, mechanical drilling may be omitted. In addition, laser drilling for external connection of the circuit patterns 210 and 220 may also be omitted. Accordingly, damage to the chip 400 that may be caused in the drilling process can be suppressed.

1 to 13 are views for explaining a chip embedded printed circuit board and a manufacturing method according to an embodiment of the present invention.

Claims (15)

Forming an upper circuit pattern and a lower circuit pattern on each of an upper carrier and a lower carrier; Mounting a chip on the upper circuit pattern of the upper carrier; Forming an intermediate insulating layer on the lower circuit pattern of the lower carrier; Introducing the upper carrier onto the lower carrier such that the chip faces the intermediate insulating layer; Bonding the upper carrier and the lower carrier so that the chip is embedded in the intermediate insulating layer; And Removing the upper carrier and the lower carrier to expose the back surfaces of the upper and lower circuit patterns. The method of claim 1, Forming the circuit pattern A chip embedded printed circuit board manufacturing method performed by pattern plating including a modified semi-additive method (MSAP). The method of claim 1, Before mounting the chip And performing a pattern inspection on the circuit pattern to sort the carrier having a normal circuit pattern in which a pattern failure has not occurred. Forming an upper circuit pattern and a lower circuit pattern on each of an upper carrier and a lower carrier; Mounting a chip on the upper circuit pattern of the upper carrier; Forming a via bump on the lower circuit pattern of the lower carrier; Introducing an intermediate insulating layer on the lower carrier having the via bumps formed thereon; Introducing the upper carrier onto the lower carrier such that the chip faces the intermediate insulating layer; Bonding the upper carrier and the lower carrier so that the chip is embedded in the intermediate insulating layer and the via bumps connect the lower circuit pattern and the upper circuit pattern; And Removing the upper carrier and the lower carrier to expose the back surfaces of the upper and lower circuit patterns. 5. The method of claim 4, Forming the circuit pattern Introducing the upper carrier and the lower carrier on which a carrier resin layer, a carrier metal layer, and a base metal layer are laminated, respectively, by adhering a carrier layer therebetween with a release layer interposed therebetween; Performing pattern plating on each of the base metal layers sequentially to form the upper and lower circuit patterns; And And forming a solder mask to isolate between the upper and lower circuit patterns. The method of claim 5, The pattern plating is A chip embedded printed circuit board manufacturing method including a modified semi-additive method (MSAP). 5. The method of claim 4, Before mounting the chip And performing a pattern inspection on the circuit pattern to sort the carrier having a normal circuit pattern in which a pattern failure has not occurred. 5. The method of claim 4, The chip is A chip embedded printed circuit board manufacturing method connected to the upper circuit pattern by a connection including a solder on pad (SOP), an anisotropic conductive film (ACF) or wire bonding (wire bonding). 5. The method of claim 4, The chip is An active element including an integrated circuit (IC) element, or A method for manufacturing a chip embedded printed circuit board, which is introduced into any one passive element selected from a group including a capacitor, an inductor, and a resistance element. 5. The method of claim 4, The chip is A chip embedded printed circuit board manufacturing method in which an active element and a passive element are introduced together. 5. The method of claim 4, The via bump is And a conductive paste formed in a conical shape so that a tip is exposed through the intermediate insulating layer. 5. The method of claim 4, The intermediate insulation layer A method for manufacturing a chip embedded printed circuit board, which is introduced into a laminate substrate or a prepreg substrate of an insulating resin. 5. The method of claim 4, Forming a protective film on a part of the back surface of the exposed upper and lower circuit patterns; And And performing surface treatment on the other part of the back surface of the exposed upper and lower circuit patterns. An intermediate insulation layer in which chips are embedded; Upper and lower circuit patterns formed on upper and lower surfaces of the intermediate insulating layer; And A solder mask having an exposed surface which is isolated between the upper and lower circuit patterns adjacent to each other and has an exposed surface having a surface height equivalent to that of the upper and lower circuit patterns, and a protruding portion is formed in the intermediate insulating layer. Chip embedded printed circuit board having a flat outer surface. The method of claim 14, And a via bump penetrating the intermediate insulating layer to connect the upper and lower circuit patterns.

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