KR101067875B1 - Method of manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device capable of preventing damage to the device isolation layer and the active region after forming the buried gate in the cell region. The method of manufacturing a semiconductor device firstly forms a hard mask layer having an etching selectivity different from that of the semiconductor substrate which exposes a portion of the cell region on the semiconductor substrate and covers the peripheral circuit region. An exposed portion of the cell region is etched using the hard mask layer to form a gate trench. A gate electrode is formed at the bottom of the gate trench. A capping film is formed in the gate trench on the gate electrode, and a sealing layer is formed over the entire surface of the substrate. The sealing layer and the hard mask layer of the peripheral circuit region are etched using a material having an etching selectivity different from that of the semiconductor substrate to expose the semiconductor substrate.

Description

Method of manufacturing semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing damage to an active region and a device isolation film after formation of a buried gate in a cell region.

 As the device size shrinks, the channel length of the transistors becomes shorter. Accordingly, a method of performing high channel doping has been proposed in order to secure transistor characteristics, but the refresh characteristic is degraded due to high channel doping. In addition, due to the low storage capacitance (Cs) it is difficult to secure a sufficient sensing margin is making efforts to lower the parasitic capacitance (Cb).

In order to solve the above problem, a buried gate structure in which a gate is arranged under a bit line has been proposed. Such a buried gate structure can reduce the capacitance between the word line and the bit line and the overall capacitance of the bit line, thereby reducing parasitic capacitance.

In general, a buried gate is formed in a cell region, and a stack gate is formed in a peripheral circuit region. Therefore, since gates cannot be simultaneously formed in the cell region and the peripheral circuit region, the buried gate is first formed in the cell region and then the stack gate is formed in the peripheral circuit region.

Therefore, after the buried gate is formed in the cell region, the sealing layer of the nitride film and the hard mask layer of the oxide film formed for the buried gate should be removed from the peripheral circuit region. However, when the etching process is performed, the device isolation layer is lost in the peripheral circuit area. The damage of the device isolation layer may result in a smaller CD and a gate tilt phenomenon when the etching process is performed to form the stack gate in the peripheral circuit region. In addition, a step occurs between the substrate and the device isolation layer, thereby causing a problem in that the active region is damaged.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing etch damage of an isolation layer and an active region when forming a gate of a stack in a peripheral circuit region after forming a buried gate in a cell region.

A method of manufacturing a semiconductor device according to an embodiment of the present invention is as follows. First, a portion of the cell region is exposed on the semiconductor substrate, and a hard mask layer having an etch selectivity different from that of the semiconductor substrate overlying the peripheral circuit region is formed. An exposed portion of the cell region is etched using the hard mask layer to form a gate trench. A gate electrode is formed at the bottom of the gate trench. A capping film is formed in the gate trench on the gate electrode, and a sealing layer is formed over the entire surface of the substrate. The sealing layer and the hard mask layer of the peripheral circuit region are etched to expose a semiconductor substrate.

The hard mask layer may include a nitride film, and the sealing layer may include a nitride film.

The capping layer and the sealing layer may be formed by forming a capping insulating layer on the hard mask layer to fill the gate trench, and etching the capping insulating layer to form the capping layer on the gate electrode in the gate trench. And forming a sealing layer on the entire surface of the substrate on which the capping film is formed.

  Forming the capping film and the sealing layer may include forming an insulating film on the hard mask pattern to fill the gate trench, and planarizing the insulating film to form the capping film on the gate electrode in the gate trench and to cover the entire substrate. It may include forming a sealing layer in. The insulating layer may include a material having an etching selectivity different from that of the semiconductor substrate, for example, a nitride layer.

A gate insulating layer may be further formed on the exposed peripheral circuit region of the semiconductor substrate.

In addition, a method of manufacturing a semiconductor device according to another embodiment of the present invention is as follows. First, an etch stop film and a hard mask layer are sequentially formed on a semiconductor substrate including a cell region and a peripheral circuit region. The etch stop layer and the hard mask layer are patterned to expose a portion of the cell region and cover the peripheral circuit region. An exposed portion of the cell region is etched using the hard mask layer to form a gate trench. A gate electrode is formed at the bottom of the gate trench. A capping film is formed in the gate trench on the gate electrode, and a sealing layer is formed over the entire surface of the substrate. The sealing layer and the hard mask layer of the peripheral circuit region are etched using the etch stop layer. The etch stop layer in the peripheral circuit region is etched to expose a semiconductor substrate.

The etch stop layer may include a material having an etching selectivity different from that of the semiconductor substrate, for example, a nitride layer.

According to the method of manufacturing a semiconductor device of the present invention, a nitride film having an etch selectivity between the device isolation layer and the active region is used as a hard mask layer for forming the buried gate in the cell region. Therefore, in the wet etching process for removing the hard mask layer to form the stack gate in the peripheral circuit region, it is possible to prevent the loss of the device isolation layer.

In addition, the present invention forms an etch stop film made of a nitride film before forming the buried gate. Therefore, even if the hard mask layer is used as the oxide film, the etching stop film can prevent the etching loss of the device isolation film. Therefore, damage to the active region due to the etching loss of the device isolation layer can be prevented, and the gate tilt phenomenon due to the CD decrease can be prevented.

1 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
8 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.
10 to 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with still another embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device in an embodiment of the present invention.

Referring to FIG. 1, a semiconductor substrate 100 is provided. The semiconductor substrate 100 may include a silicon substrate. The semiconductor substrate 100 may include a cell region 101 in which memory cells are arranged and a peripheral circuit region 105 in which peripheral circuits are arranged. The isolation layer process may be performed to form the isolation layer 110 defining the active regions 120 of the cell region 101 and the peripheral circuit region 105 in the isolation trench. The device isolation layer may include a spin on dielectric (SOD) -based insulating layer. For example, the device isolation layer may include an oxide layer. Prior to forming the device isolation layer 110, a liner nitride layer (not shown) and a liner oxide layer (not shown) may be further formed on the bottom and sidewalls of the device isolation trench.

Referring to FIG. 2, a hard mask layer 130 is formed on the semiconductor substrate 100 on which the device isolation layer 110 is formed. Subsequently, the hard mask layer 130 is etched using a gate mask (not shown) to expose the gate forming region of the active region 120 of the cell region 101.

In this case, the hard mask layer 130 may expose a portion of the device isolation layer 110 in the cell region 101. The hard mask layer 130 may include a material having an etching selectivity different from that of the semiconductor substrate 100 and the device isolation layer 110. The hard mask layer 130 may include a nitride film.

Subsequently, the exposed portion of the active region 120 of the cell region 101 is etched by a predetermined depth using the hard mask layer 130 to gate the active region 120 of the cell region 101. Trench 140 is formed. In this case, a portion of the device isolation layer 110 in the cell region 101 may also be etched to a predetermined depth to form the gate trench 140 in the device isolation layer 110.

Referring to FIG. 3, a gate insulating layer 145 is formed on the bottom and sidewalls of the gate trench 140. When the gate insulating layer 145 includes an oxide layer formed through an oxidation process, the gate insulating layer 145 may be arranged only in the gate trench 140. A gate electrode material (not shown) is formed on the hard mask layer 130 to fill the gate trench 140.

Subsequently, the gate electrode material is etched through the CMP process and / or the etch back process to form the gate electrode 150 at the bottom of the gate trench 140. The gate electrode 150 may have a stacked structure of a barrier layer and a gate metal layer. The barrier metal may include TiN, and the gate metal layer may include a tungsten film.

Referring to FIG. 4, a capping insulating layer (not shown) is formed on the hard mask layer 130 to fill the upper portion of the gate trench 140. The capping insulating layer may include a material having an etching selectivity different from that of the device isolation layer 110 and the semiconductor substrate 100. The capping insulating layer may include a nitride layer. The capping insulating layer is etched through a CMP process or an etch back process to form a capping layer 155 so that the gate trench 140 is buried on the gate electrode 150. Thus, a buried gate including the gate insulating layer 145, the gate electrode 150, and the capping layer 155 is formed in the gate trench.

Referring to FIG. 5, a sealing layer 160 is formed on the hard mask layer 130 and the buried gate. The sealing layer 160 may include a nitride film.

Referring to FIG. 6, a photoresist pattern (not shown) is formed on the sealing layer 160 to expose the sealing layer 160 on the peripheral circuit region 105. The sealing layer 160 and the hard mask layer 130 are etched using the photoresist as an etch mask to expose the semiconductor substrate 100 in the peripheral circuit region. The sealing layer 160 and the hard mask layer 130 may be removed by a wet etching process or a dry etching process.

Referring to FIG. 7, a gate insulating film 170 for a peripheral circuit is formed on the semiconductor substrate 100 in the peripheral circuit region 105. Although not shown in the drawing, a stack gate is formed on the gate insulating layer 170 through a gate forming process.

8 and 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention. 8 and 9 illustrate only the process of forming the gate capping layer and the sealing layer.

The process of forming the gate electrode 150 in the gate trench 140 may be performed in the same manner as illustrated in FIGS. 1 to 3.

Subsequently, the gate electrode 150 is formed on the bottom of the gate trench 140, and the nitride film 180 for the capping film and the sealing layer is deposited as shown in FIG. 8 through a single deposition process. Next, the nitride film 180 is planarized through a CMP process or an etch back process. Accordingly, the nitride film 180 is formed on the gate electrode 150 to serve as a gapping film embedded in the gate trench 140 and a sealing layer arranged on the hard mask layer 130.

The process of exposing the semiconductor substrate 100 in the peripheral circuit region 105 by removing the nitride film 180 from the peripheral circuit region 105 and the subsequent process of forming the gate insulating layer 170 are illustrated in FIG. 6 and the same procedure as in FIG.

10 to 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with still another embodiment of the present invention.

Referring to FIG. 10, the device isolation layer 110 defining the active region 120 is formed in the cell region 101 and the peripheral circuit region 105 of the semiconductor substrate 10 in the same manner as in FIG. 1. Subsequently, an etch stop layer 190 is formed on the semiconductor substrate 100 including the device isolation layer 110. The etch stop layer 190 may include a material having an etching selectivity different from that of the semiconductor substrate 100 and the device isolation layer 110. The etch stop layer 190 may include a nitride layer.

Referring to FIG. 11, a hard mask layer 130 is formed on the etch stop layer 110, and then the etch stop layer 190 and the hard mask layer 130 are formed using a gate mask (not shown). By etching, a portion of the active region 120 of the cell region 101 is exposed. Subsequently, the gate trench 140 is formed by etching the exposed portion of the active region 120 in the cell region 101 using the hard mask layer 130 as a mask.

The hard mask layer 130 may include an oxide film or a nitride film because an etch stop film 190 having an etch selectivity different from that of the semiconductor substrate 100 and the device isolation layer 110 is arranged below. have. A TEOS film may be used as the oxide film for the hard mask layer 130.

Referring to FIG. 12, a process including a gate insulating layer 145, a gate electrode 150, and a capping layer 155 is formed in the gate trench 140 by performing a process as illustrated in FIGS. 3 to 5. A gate is formed, and a sealing layer 160 is formed on the hard mask layer 130 including the buried gate. In this case, as shown in FIGS. 8 and 9, the capping layer 155 and the sealing layer 160 may have a structure in which the capping layer and the sealing layer are integrated. The sealing layer 160 may include a nitride film.

Referring to FIG. 13, the hard mask layer 130 and the sealing layer 160 are removed from the peripheral circuit region 105 using the etch stop layer 190, and then, in the peripheral circuit region 105. The etch stop layer 190 is removed to expose the semiconductor substrate 100 in the peripheral circuit region 105. The etch stop layer 190 may be removed using a phosphoric acid solution. A gate insulating layer 170 may be formed on the exposed semiconductor substrate 100 of the peripheral circuit region 105, and then a stack gate (not shown) may be formed thereon.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, various modifications and changes by those skilled in the art within the spirit and scope of the present invention Changes are possible.

100: semiconductor substrate 110: device isolation film
120: active region 130: hard mask layer
140: trenches 145 for gates and 170: gate insulating films
150: gate electrode 155: capping film
160: sealing layer 180: nitride film
190: etching stop film

Claims (15)

Forming a hard mask layer on the semiconductor substrate, the hard mask layer having an etch selectivity different from that of the semiconductor substrate exposing a portion of the cell region and covering the peripheral circuit region;
Etching the exposed portion of the cell region by using the hard mask layer to form a gate trench;
Forming a gate electrode at a bottom of the gate trench;
Forming a capping film in the gate trench on the gate electrode, and forming a sealing layer over the entire surface of the substrate; And
And etching the sealing layer and the hard mask layer in the peripheral circuit region using a material having an etching selectivity different from that of the semiconductor substrate to expose the semiconductor substrate. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, wherein the hard mask layer comprises a nitride film. Claim 3 was abandoned when the setup registration fee was paid. The method of manufacturing a semiconductor device according to claim 1, wherein the sealing layer comprises a nitride film. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, wherein the forming of the capping layer is performed.
Forming a capping insulating layer on the hard mask layer to fill the gate trench; And
Etching the capping insulating layer to form the capping layer on the gate electrode in the gate trench. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein the sealing layer and the capping film include a nitride film. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, wherein the forming of the capping layer and the sealing layer is performed.
Forming an insulating film on the hard mask pattern to fill the gate trench; And
And planarizing the insulating film to form the capping film on the gate electrode in the gate trench and to form a sealing layer on the entire surface of the substrate. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, wherein the insulating layer comprises a material having an etching selectivity different from that of the semiconductor substrate. Claim 8 was abandoned when the registration fee was paid. 8. The method of claim 7, wherein the insulating film includes a nitride film. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, further comprising forming a gate insulating film on the exposed peripheral circuit area of the semiconductor substrate. Sequentially forming an etch stop layer and a hard mask layer on the semiconductor substrate including the cell region and the peripheral circuit region;
Patterning the etch stop layer and hard mask layer to expose a portion of the cell region and cover a peripheral circuit region;
Etching the exposed portion of the cell region by using the hard mask layer to form a gate trench;
Forming a gate electrode at a bottom of the gate trench;
Forming a capping film in the gate trench on the gate electrode, and forming a sealing layer over the entire surface of the substrate;
Etching the sealing layer and the hard mask layer in the peripheral circuit region using the etch stop layer; And
Etching the etch stop layer in the peripheral circuit region to expose a semiconductor substrate. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10, wherein the etch stop layer comprises a material having an etching selectivity different from that of the semiconductor substrate. Claim 12 was abandoned upon payment of a registration fee. The method of claim 11, wherein the etch stop layer comprises a nitride layer. Claim 13 was abandoned upon payment of a registration fee. The method of claim 10, wherein the forming of the capping layer and the sealing layer is performed.
Forming an insulating film on the hard mask pattern to fill the gate trench; And
And planarizing the insulating film to form the capping film on the gate electrode in the gate trench and to form a sealing layer on the entire surface of the substrate. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, wherein the insulating film comprises a nitride film. Claim 15 was abandoned upon payment of a registration fee. The method of claim 10, further comprising forming a gate insulating film on the exposed peripheral circuit area of the semiconductor substrate.

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