KR20080090798A - Transistor manufacturing method of semiconductor device - Google Patents

Abstract

A transistor manufacturing method of a semiconductor device of the present invention includes forming a gate pattern on a semiconductor substrate in which a cell region and a peripheral circuit region are defined; Sequentially depositing a buffer film, a spacer nitride film, and a spacer oxide film on the gate pattern and the semiconductor substrate; Forming a mask layer pattern exposing the spacer oxide layer of the cell region while blocking the peripheral circuit region; Performing an ion implantation process on the spacer oxide film of the cell region exposed with the mask layer pattern by the ion implantation mask; And etching to remove the spacer oxide film having undergone the ion implantation process.

Description

Method for manufacturing transistor in semiconductor device

1 to 6 are views illustrating a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a transistor manufacturing method of a semiconductor device capable of improving a lack of space margin.

Recently, as semiconductor devices have been highly integrated, design rules have become smaller. As a result, the size of the device is also decreasing. As the size of the device becomes smaller and the space margin between the gate and the gate becomes smaller, a spacer structure in which a buffer film and a spacer nitride film are stacked on the gate is applied. This is because a thinner spacer is deposited as the space margin becomes smaller, while requiring excellent step coverage characteristics and excellent intermetallic insulating properties. At this time, the spacer nitride film is also used as an ion implantation barrier film in the ion implantation process performed in the transistor formation process to improve the characteristics of the junction region and the transistor. In addition, the spacer nitride layer is used as an etch barrier layer in an etching process to form a subsequent landing plug, thereby preventing self alignment contact (SAC) defects between the gate and the bit line, and preventing SAC defects between the word line and the capacitor. Improves the characteristics of the device to increase the yield and stability of the semiconductor device.

Meanwhile, when a word line is formed using a gate spacer formed of a buffer film, a spacer nitride film, and a spacer oxide film when fabricating a DRAM having a dynamic random access memory (DRAM) of 80-100 nm or more, the cell region has a space between the word lines. Due to lack of critical dimension (CD) margin, a problem may occur in that the spacer nitride layer is etched in the etching process for forming the landing plug. When the spacer nitride layer is etched, the semiconductor substrate, which is a channel formation region, may be exposed, resulting in a problem of deterioration of transistor characteristics. Accordingly, after forming the gate spacer, the peripheral circuit region is blocked, the spacer oxide layer of the cell region is selectively removed, the nitride layer is deposited to a predetermined thickness, and the etching process for forming the landing plug is performed. A method of preventing a defect has been proposed.

However, DRAM devices of 80 nm or less face limitations in terms of space margin in the process of removing spacer oxide layers in the cell region using wet chemicals. Specifically, as the space between the gate becomes narrower, a spacer oxide film is deposited while filling the space between the gate and the gate. Accordingly, when the spacer oxide layer is etched in the cell region, the etching target position is almost the height of the gate. In addition, in the etching process for forming the landing plug according to the etching time, a phenomenon in which the landing plug is not properly formed may occur while the spacer oxide layer remains between the gates. In order to improve this phenomenon, there is also a method of reducing the deposition thickness of the spacer oxide layer to facilitate etching chemical penetration, but may cause SAC defects in the etching process. In addition, since the line width CD of the gate spacer is reduced in the peripheral circuit region, the cell threshold voltage of the transistor disposed in the peripheral circuit region is lowered.

Therefore, while the remaining oxide film is completely removed in the cell region, there is no side attack of the transistor disposed in the peripheral circuit region by the etching chemical, and the thickness of the spacer oxide layer in the peripheral circuit region is kept constant so that the PMOS / NMOS transistor is stable. There is a need for a method of removing a spacer oxide layer in a cell region in which a threshold voltage of 5 is implemented.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of fabricating a transistor of a semiconductor device capable of improving a space margin shortage phenomenon of a word line by selectively removing a spacer oxide layer in a cell region when forming a gate spacer.

In order to achieve the above technical problem, a transistor manufacturing method of a semiconductor device according to the present invention, forming a gate pattern on a semiconductor substrate in which a cell region and a peripheral circuit region is defined; Sequentially depositing a buffer film, a spacer nitride film, and a spacer oxide film on the gate pattern and the semiconductor substrate; Forming a mask layer pattern exposing the spacer oxide layer of the cell region while blocking the peripheral circuit region; Performing an ion implantation process on the spacer oxide layer of the exposed cell region using the mask layer pattern as an ion implantation mask; And etching to remove the spacer oxide film in which the ion implantation process has been performed.

In the present invention, the buffer film may be formed using an oxidation process.

The mask layer pattern may be formed of a photoresist material.

In the ion implantation step, it is preferable to use phosphorus (P) ions or ascetic (As) ions.

The ion implantation process is carried out while maintaining ion implantation energy of 5 to 20 KeV at a dose of 1.0E14 to 1.5E16 atoms / cm 2 at a tilt angle of 0-10 °.

In the ion implantation process, it is preferable to use boron (B) ions or boron fluoride (BF ₂ ) ions.

The ion implantation step proceeds in a state in which ion implantation energy of 5 to 10 KeV is maintained at a dose of 1.0E12 to 1.0E14 atoms / cm 2.

Etching and removing the spacer oxide layer is preferably performed by wet etching.

The wet etching is preferably using a BOE solution, hydrofluoric acid (DHF) solution or an etching solution that can exhibit similar characteristics.

The wet etching is preferably performed for 10-15 seconds.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity.

1 to 6 are views illustrating a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention. In particular, Figure 6 is a SEM (SEM) picture showing a transistor formed in accordance with an embodiment of the present invention.

Referring to FIG. 1, a first gate pattern 112a and a second gate pattern 112b are disposed on a semiconductor substrate 100. In the semiconductor substrate 100, a cell region A and a peripheral region B are defined, and a recess trench 102 is formed in the cell region A of the semiconductor substrate 100. have. The first gate pattern 112a is disposed to overlap the recess trench 102 formed in the cell region A, and the second gate pattern 112b is disposed in the peripheral circuit region B. The first and second gate patterns 112a and 112b have a structure in which the gate insulating film pattern 104, the conductive film pattern 106, the metal film pattern 108, and the hard mask film pattern 110 are stacked. . In this case, the conductive film pattern 106 may be formed of polysilicon, and the metal film pattern 108 may be formed of tungsten (W) or tungsten silicide (WSix). In addition, the hard mask film pattern 110 may be formed of a nitride film. On the other hand, as the semiconductor devices are highly integrated, the density between patterns increases, so that the first gate pattern 112a disposed in the cell region A is more gated than the second gate pattern 112b disposed in the peripheral circuit region B. The space margin a between the gate and the gate appears narrow.

Referring to FIG. 2, a buffer oxide film 114, a spacer nitride film 116, and a spacer oxide film 118 are sequentially deposited on the semiconductor substrate 100 on which the first and second gate patterns 112a and 112b are formed.

Specifically, the buffer film 114 is deposited on the semiconductor substrate 100. The buffer layer 114 is formed on both sides of the first and second gate patterns 112a and 112b and the semiconductor substrate 100 by performing an oxidation process, for example, a thermal oxidation process. The buffer layer 114 recovers etch damage applied to the first and second gate patterns 112a and 112b in an etching process performed to form the first and second gate patterns 112a and 112b. It plays a role. Next, the spacer nitride film 116 is deposited on the buffer film 114 to a thickness of 80-200 kPa using a method such as chemical vapor deposition (CVD). After the spacer nitride layer 116, the etching process using the wet chemical is performed to protect the first and second gate patterns 112a and 112b from being attacked by the wet chemical. do.

Next, a spacer oxide film 118 is deposited over the spacer nitride film 116. The spacer oxide layer 118 then serves as a sidewall in the process of forming a lightly doped drain (LDD) structure in the peripheral circuit region B. FIG. The spacer oxide layer 118 is a low pressure tetra ethyl ortho silicate (LPTEOS) layer having a fast wet etching rate and good step coverage, and is deposited to have a thickness of 580-680 kPa. At this time, the first gate pattern 112a disposed in the cell region A has only a space of about 70-90nm when the space margin (a, see FIG. 1) between the gate and the gate is 80 nm or less. All are filled by the spacer oxide film 118.

Referring to FIG. 3, the photoresist layer pattern 120 may be formed to block the second gate pattern 112b of the peripheral circuit region B and expose the cell region A. FIG. Specifically, the photoresist film is applied onto the semiconductor substrate 100 using a method such as spin coating. Next, the photoresist film pattern 120 which selectively exposes the cell region A is formed by performing a photo process using an exposure and development process on the photoresist film.

Referring to FIG. 4, an ion implantation process of implanting impurities onto the semiconductor substrate 100 is performed by using the photoresist layer pattern 120 as an ion implantation mask as indicated by arrows in the drawing. An ion implantation process is implanted on the spacer oxide film 118 in the cell region A exposed by the photoresist film pattern 120. The impurities are implanted with n-type impurities, for example phosphorus (P) ions or asic (As). The ion implantation process is implanted at a dose angle of 1.0E14 to 1.5E16 atoms / cm 2 at a tilt angle of 0-10 ° while maintaining ion implantation energy of 5 to 20 KeV. In this case, the impurity to be injected into the spacer oxide film 118 of the cell region A may be implanted with p-type impurities such as boron (B) ions or boron fluoride (BF ₂ ) ions. In the case of implanting the p-type impurity, the impurity is preferably implanted in a state in which ion implantation energy of 5 to 10 KeV is maintained at a dose of 1.0E12 to 1.0E14 atoms / cm 2.

The ion implantation process performed in this manner serves to enhance wet etch rate characteristics of the spacer oxide film 118 of the region exposed by the photoresist film pattern 120, that is, the cell region A. FIG. do. In general, the wet etching characteristics of the oxide film implanted with impurities increase as the mass of impurities implanted, the larger the dose, and the smaller the ion implantation energy for implanting impurities, the faster the etching rate on the surface. When the ion implantation process of implanting impurities into the spacer oxide film 118 of the cell region A using the ion implantation characteristics is performed, the spacer oxide film 118 undergoing ion implantation is compared with the oxide film not undergoing the ion implantation process. Thus, the etching speed is about 7-10 times faster.

Referring to FIG. 5, the spacer oxide layer 118 of the cell region A is etched and removed using the photoresist layer pattern 120 as an etch mask on the semiconductor substrate 100 on which the ion implantation process is performed.

The spacer oxide film 118 in the cell region A has an etching rate of 280-400 Pa / sec in the etching solution while the etching rate is increased by the ion implantation process described above. At this time, the selection ratio of the vertical oxide loss to the lateral oxide loss of the spacer oxide 118 increases by at least 7 times. The wet etching is performed for 10-15 seconds using an etched solution which can exhibit a buffered oxide etchant (BOE) solution, a hydrofluoric acid (DHF) solution, or the like. Then, the spacer oxide film 118 of the cell region A in which the impurities are implanted is about compared with that of the oxide film that has not undergone the ion implantation process due to the above-described ion implantation characteristics, which exhibits an etching rate of 40-50 kV / sec in the BOE solution. Etch rate is 7-10 times faster. In the conventional case, when the spacer oxide film is selectively removed, the gate spacer height is approximately 350-400 nm after the deposition of the spacer oxide film, so that when the wet etching is performed with the target to remove all of them, the gate pattern of the peripheral circuit region is attacked. do. This means that the thickness from the mask that selectively exposes the cell region to the peripheral circuit region is about 250-350 nm, which is shorter than the gate spacer height, and the chemical diffusion rate by the oxide etching solution is about 1.2 to 1.5 times faster than the vertical etching rate. Because.

In contrast, in the present invention, by increasing the etching rate of the spacer oxide layer 118 of the cell region A, the residual oxide layer may not be left between the gate and the gate even though the wet etching process time is short, such as 10-15 seconds. In addition, by increasing the etching rate of the spacer oxide film, it is possible to reduce the oxide film loss of the peripheral circuit area due to the lateral attack. This may be confirmed through FIG. 6, which is a SEM image of selectively etching the spacer oxide layer and then depositing a conductive layer with a capping layer.

In the transistor manufacturing method of the semiconductor device according to the present invention, an ion implantation step of implanting a high concentration of impurities into the spacer oxide film is performed before removing the spacer oxide film of the cell region. Accordingly, the selection ratio of the vertical loss amount to the side loss amount of the spacer oxide layer is increased by at least 7 times to secure enough margin for the side attack of the etching solution and to remove the spacer oxide layer of the cell region without changing the side thickness of the peripheral circuit region. can do. In addition, by improving the etching rate of the spacer oxide layer, it is possible to control defects in which the bit line contact hole is not formed in a subsequent process, and to reduce the thickness of the spacer oxide layer to secure a space margin, thereby ensuring a stable threshold of the peripheral circuit region. Voltage can be implemented.

As described so far, according to the transistor manufacturing method of the semiconductor device according to the present invention, by implanting impurities on the spacer oxide film in the cell region to increase the selectivity ratio of the vertical oxide loss to the side oxide loss to the side attack of the wet chemical We can secure enough margin. In addition, the spacer oxide film of the cell region can be effectively removed without changing the gate sidewall thickness of the peripheral circuit region. Accordingly, as the device shrinks, the lack of space margin between the gate and the gate may be controlled by adjusting the amount of impurity dose. In addition, bit line contact control and threshold voltage stabilization of the peripheral circuit region may be implemented.

Claims (10)

Forming a gate pattern on a semiconductor substrate in which cell regions and peripheral circuit regions are defined; Sequentially depositing a buffer film, a spacer nitride film, and a spacer oxide film on the gate pattern and the semiconductor substrate; Forming a mask layer pattern exposing the spacer oxide layer of the cell region while blocking the peripheral circuit region; Performing an ion implantation process on the spacer oxide layer of the exposed cell region using the mask layer pattern as an ion implantation mask; And And removing the spacer oxide film subjected to the ion implantation process by etching. The method of claim 1, The buffer film is a transistor manufacturing method of a semiconductor device, characterized in that formed by the oxidation process. The method of claim 1, And the mask film pattern is formed of a photoresist material. The method of claim 1, The ion implantation process is a transistor manufacturing method of a semiconductor device, characterized in that it uses phosphorus (P) ions or ashenic (As) ions. The method of claim 4, wherein The ion implantation process is a transistor of a semiconductor device, characterized in that the ion implantation energy of 5 ~ 20 KeV at a tilt angle of 0-10 ° at a dose of 1.0E14 ~ 1.5E16 atoms / ㎠ Manufacturing method. The method of claim 1, The ion implantation process is a transistor manufacturing method of a semiconductor device, characterized in that using the boron (B) ions or boron fluoride (BF ₂ ) ions. The method of claim 6, The ion implantation process is a transistor manufacturing method of a semiconductor device, characterized in that the progress of the ion implantation energy of 5 ~ 10 KeV at a dose of 1.0E12 ~ 1.0E14 atoms / ㎠. The method of claim 1, And etching the spacer oxide layer to remove the spacer oxide layer by using wet etching. The method of claim 8, The wet etching method is a transistor manufacturing method of a semiconductor device, characterized in that using an etching solution that can exhibit a BOE solution, hydrofluoric acid (DHF) solution or similar characteristics. The method of claim 8, The wet etching is a transistor manufacturing method of a semiconductor device, characterized in that for 10-15 seconds.

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