KR101044019B1 - Nonvolatile memory device and manufacturing method of the same - Google Patents

Abstract

The present invention relates to a method of manufacturing a nonvolatile memory device capable of securing process stability in forming a stacked structure of memory cells.

According to the present invention, an etching auxiliary layer may be formed on the sidewall of the gate polysilicon layer while simultaneously etching the gate polysilicon layer. In addition, according to the present invention, the etching width of the lower layer may be uniformly controlled when the lower layer is etched in a subsequent process by using the etching auxiliary layer. As a result, the present invention can uniformize the steps formed at the edge of the structure in which the interlayer insulating film and the gate polysilicon film are alternately stacked.

Polymer, 3D Memory Cells

Description

Nonvolatile memory device and manufacturing method thereof

The present invention relates to a nonvolatile memory device and a method for manufacturing the same, and more particularly, to a nonvolatile memory device and a method for manufacturing the same that can ensure the stability of the manufacturing process.

Recently, the demand for high capacity nonvolatile memory devices is increasing rapidly. Accordingly, there is a demand for development of a design rule capable of highly integrated nonvolatile memory devices. Among the nonvolatile memory devices, NAND flash memory devices are electrically programmable and erased, and do not require a refresh function to rewrite data at regular intervals. Therefore, the demand is increasing.

In order to further integrate the NAND flash memory device described above, the size of the patterns constituting the NAND flash memory device is reduced. In general, the pattern of the device is patterned using a photolithography process, the photolithography process is limited by the exposure resolution, there is a limit to the high integration of the device by reducing the size of the pattern. In order to overcome these limitations and increase the degree of integration of devices, the development of a three-dimensional memory cell having a structure in which a plurality of cells are stacked is in progress. In addition, in forming a 3D memory cell having a stacked structure of memory cells, various technology developments are required, and a method for securing stability of the manufacturing process is required.

The present invention provides a nonvolatile memory device and a method of manufacturing the same that can ensure process stability in forming a stacked structure of memory cells.

The nonvolatile memory device according to the present invention is stacked on top of a semiconductor substrate, and includes a plurality of polysilicon layers having a step to which a contact structure is connected, and an interlayer insulating layer stacked between each layer of the plurality of polysilicon layers. . Each of the plurality of polysilicon films exposed by the step may include an upper sidewall inclined with respect to the semiconductor substrate and a lower sidewall connected to the upper sidewall and perpendicular to the semiconductor substrate. The interlayer insulating film includes sidewalls perpendicular to the semiconductor substrate.

A method of manufacturing a nonvolatile memory device according to the present invention includes forming a stacked structure in which a plurality of interlayer insulating films and a plurality of polysilicon layers are alternately stacked on a semiconductor substrate, and forming an etch barrier pattern on the stacked structure. And performing a first etching process such that a residue generated while etching the polysilicon layer exposed by the etch barrier pattern is deposited on the etched surface of the polysilicon layer to form an etch auxiliary layer, and exposed through the etch auxiliary layer. Etching the polysilicon film in a second etching process to expose the interlayer insulating film, etching the exposed region of the interlayer insulating film in a third etching process, and contact structures are connected to the plurality of polysilicon films. The plurality of interlayer insulating films and the plurality of polysilicon films to form stepped portions. Etching each layer by repeatedly performing the first to third etching processes.

The etching barrier pattern is formed of an organic material.

The etching barrier pattern is formed of a photoresist pattern.

The first etching process is performed using an etching gas including at least one of carbon and hydrogen.

The etching gas used in the first etching process may have a higher content of carbon or hydrogen than the etching gas used in the second etching process.

The etching gas used in the first etching process further includes at least one of HBr and HI.

The sidewalls inclined with respect to the semiconductor substrate are formed on the polysilicon layer by the first etching process.

The inclined sidewall is preferably formed at an inclination of 5 ° to 45 ° with respect to the semiconductor substrate.

The width of the polysilicon film forming the inclined sidewall is preferably 40nm to 1000nm.

In the second etching process, sidewalls perpendicular to the semiconductor substrate may be formed in the polysilicon layer.

In the third etching process, sidewalls perpendicular to the semiconductor substrate are formed in the interlayer insulating layer.

The first and second etching processes may be performed in-situ or ex-situ.

The third etching process includes at least one of a gas containing C, F, Cl ₂ gas, and HBr gas.

The first to third etching processes are performed using plasma etching equipment.

The plasma etching apparatus may be performed using a capacitively coupled plasma (CCP) type, an inductively coupled plasma (ICP) type, a microwave plasma type, or a mixture of two or more characteristics.

According to the present invention, an etching auxiliary layer may be formed on the sidewall of the gate polysilicon layer while simultaneously etching the gate polysilicon layer. In addition, according to the present invention, the etching width of the lower layer may be uniformly controlled when the lower layer is etched in a subsequent process by using the etching auxiliary layer. As a result, the present invention can uniformize the steps formed at the edge of the structure in which the interlayer insulating film and the gate polysilicon film are alternately stacked.

Since the present invention can secure a certain distance step on the edge of the stacked structure, the yield of the nonvolatile memory device can be improved by improving the bridge due to misalignment when forming the subsequent contact structure.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1 is a perspective view schematically illustrating a nonvolatile memory device including a 3D memory cell.

Referring to FIG. 1, a nonvolatile memory device including a 3D memory cell includes a memory cell region, a word line (WL) driving circuit, a source select line (SSL) driving circuit, a drain select line (DSL) driving circuit, and the like. do.

The memory cell region includes a plurality of string structures arranged in a matrix. The string structure consists of a plurality of memory cells connected in series between a source select transistor and a drain select transistor. Here, the gates of the source select transistors are connected to form a source select line SSL, and the gates of the drain select transistors are connected to form a drain select line DSL. The control gates of the memory cells arranged on the same layer are connected via word lines WL.

The above-described string structure is selectively connected to the bit line BL through the drain select transistor, and selectively connected to the common source line connected to the ground through the source select transistor.

The word lines WL are formed by stacking a plurality of layers with an insulating layer therebetween. A source select line SSL is formed under the word lines WL stacked in multiple layers with an insulating layer interposed therebetween, and a drain select line DSL is formed with an insulating layer interposed therebetween. do. That is, the multilayer word lines WL are stacked between the source select line SSL and the drain select line DSL. According to this structure, not only a plurality of memory cells are formed in a plane parallel to the semiconductor substrate, but also a plurality of memory cells are formed in a plane parallel to the semiconductor substrate and arranged in three dimensions, thereby providing a highly integrated device.

2 is a cross-sectional view schematically illustrating a memory cell region of a nonvolatile memory device including a 3D memory cell.

Referring to FIG. 2, memory cells of a nonvolatile memory device including a three-dimensional memory cell may include a bulk structure 203, 205, and 207 implanted with impurity ions, and a semiconductor substrate 201 including a device isolation structure 209. It is formed at the top of the. When the memory cells of the nonvolatile memory device have an NMOS structure, the bulk structure includes a TN well 203 formed in a P-type substrate, a P well 205 formed in the TN well 203, and a threshold voltage. The n + region 207 is formed by implanting n-type impurity ions into the P well 205 to control the P-type.

More specifically, the interlayer insulating films 213a, 213b, 213c, 213d, and 213f and the gate polysilicon films 215a, 215b, 215c, 215d, and 215f are alternately stacked on the semiconductor substrate 201, so that the source select line SSL may be stacked. ), The gate patterns including the word lines WL1, WL2, WL3, and WL4, and the drain select line DSL are insulated from each other to form a stacked structure. A plurality of holes are formed through the interlayer insulating films 213a, 213b, 213c, 213d, and 213f and the polysilicon films 215a, 215b, 215c, 215d, and 215f to expose the n + region 207, and each hole is formed. The sidewall insulating layer 221 including the charge storage layer is formed on the sidewall. The inside of the hole in which the sidewall insulating layer 221 is formed is filled with the semiconductor layer 223. The semiconductor layer 223 may be formed using amorphous silicon, polysilicon, monosilicon, or the like formed through epitaxial growth. In addition, a source region and a drain region (not shown) are formed in a predetermined region of the semiconductor layer 223. The source region of the semiconductor layer 223 may be connected to the semiconductor substrate 201 including a bulk structure, and the drain region of the semiconductor layer 223 may be connected to the bit line.

The sidewall insulating layer 221 including the charge storage layer may be formed as a stacked structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film. In this case, charge may be stored in the silicon nitride film of the sidewall insulating layer 221 formed between the semiconductor layer 223 and the word lines WL1, WL2, WL3, and WL4.

In the nonvolatile memory device having the above-described structure, a threshold of a memory cell is formed by injecting or releasing charge into the charge storage layer of the sidewall insulating layer 221 formed between the semiconductor layer 223 and the word lines WL1, WL2, WL3, and WL4. The voltage is controlled to perform a program or erase operation.

Meanwhile, each gate polysilicon film 215a has a lamination structure of gate patterns formed by alternately stacking the interlayer insulating films 213a, 213b, 213c, 213d, and 213f and the gate polysilicon films 215a, 215b, 215c, 215d, and 215f. , 215b, 215c, 215d, and 215f) have a step at the edge. This step is formed in a step shape so that the gate polysilicon films 215a, 215b, 215c, 215d, and 215f of each layer can be exposed. Through such a step, each of the gate patterns SSL, WL1, WL2, WL3, WL4, and DSL is formed by forming a contact structure connected to the driving circuit at the edge of each gate pattern (SSL, WL1, WL2, WL3, WL4, DSL). It can be electrically connected to the furnace.

3A to 3C are cross-sectional views illustrating a method of patterning the gate patterns of each layer to have a stepped step.

Referring to FIG. 3A, first, an interlayer insulating film 213a, 213b, 213c, 213d, and 213f and a gate polysilicon film 215a, 215b, 215c, and 215d are disposed on a semiconductor substrate 301 including an isolation structure and a bulk structure. , 215f) forms an alternately stacked structure. At this time, an oxide film can be used as the interlayer insulating films 213a, 213b, 213c, 213d, and 213f.

The number of stacked layers of the interlayer insulating films 213a, 213b, 213c, 213d, and 213f and the gate polysilicon films 215a, 215b, 215c, 215d, and 215f increases as the number of memory cells included in the string structure to be formed increases. do.

Thereafter, an etching barrier pattern 301 such as a photoresist pattern is formed on the uppermost gate polysilicon film 215f. In this case, the width of the etch barrier pattern 301 is the first width W1 and the height is the first height h1. The gate polysilicon layer 215f and the interlayer insulating layer 213f are etched using the etching barrier pattern 301 having the first width W1 and the first height h1.

Referring to FIG. 3B, while the uppermost gate polysilicon layer 215f and the interlayer insulating layer 213f are etched, the width of the etch barrier pattern 301 may be a second width W2 narrower than the first width W1. The second height h2 may be lower than the first height h1. As a result, the uppermost gate polysilicon film 215f and the interlayer insulating film 213f are etched to become narrower than the lower gate polysilicon film 215e and the interlayer insulating film 213f.

Referring to FIG. 3C, the width of the etching barrier pattern 301 during the etching process using the etching barrier pattern 301 until the lowermost gate polysilicon layer 215a and the interlayer insulating layer 213a are etched is performed. The height may decrease gradually to become the third width W3 narrower than the second width W2 and may become the third height h3 lower than the second height h2. The gate polysilicon film and the interlayer insulating film formed on the upper layer portion are etched to a greater width. As a result, the interlayer insulating films 213a, 213b, 213c, 213d, and 213f and the gate polysilicon films 215a, 215b, 215c, 215d, and 215f are patterned in a narrower width toward the upper layers, thereby forming the interlayer insulating films 213a, 213b, 213c, and 213d. , 213f) and stepped steps are formed at the edges of the gate polysilicon films 215a, 215b, 215c, 215d, and 215f.

However, when the stepped step is formed by the method described above with reference to FIGS. 3A to 3C, the width of the step may be uneven, so that an alignment error may occur when the contact structure is formed in the step in the subsequent step. The present invention proposes a method to ensure the stability of the manufacturing process of the nonvolatile memory device including a three-dimensional memory cell by controlling the stepped stepped width uniformly.

4A to 4E are cross-sectional views illustrating a 3D nonvolatile memory device and a method of manufacturing the same according to the present invention. In particular, in Figs. 4A to 4E, a step formed at the edge of the gate pattern of the three-dimensional nonvolatile memory device and a method of forming the same will be described.

Referring to FIG. 4A, an interlayer insulating film 413a, 413b, 413c, 413d, 413e, and 413f and a gate polysilicon film 415a, 415b, and 415c are formed on top of a semiconductor substrate 401 including a device isolation structure and a bulk structure. , 415d, 415e, and 415f) form an alternately stacked structure. At this time, an oxide film can be used as the interlayer insulating films 413a, 413b, 413c, 413d, 413e, and 413f.

The number of stacked layers of the interlayer insulating films 413a, 413b, 413c, 413d, 413e, and 413f and the gate polysilicon films 415a, 415b, 415c, 415d, 415e, and 415f is the number of memory cells included in the string structure to be formed. Increases with increase.

Thereafter, an etching barrier pattern 451 is formed on the uppermost gate polysilicon film 415f. The etching barrier pattern 301 may be formed of an organic material including carbon (C), and may be formed of a photoresist pattern.

An etching gas is injected into the etching barrier pattern 301 described above using an etching mask to etch the gate polysilicon layer 415f on the uppermost layer in the first etching process. The etching gas used to etch the polysilicon layer 415f in the first etching process is combined with the silicon of the polysilicon layer 415f and the carbon of the etching barrier pattern 301 to form the first etching auxiliary layer 435a. It is desirable to include materials that can be made. The first etching auxiliary layer 435a may be formed by including at least one of carbon (C) and hydrogen (H) in the etching gas, and by increasing the content of carbon and hydrogen in the etching gas, the first etching auxiliary layer ( 435a) can be increased. In addition, the etching gas may further include at least one of HBr and HI.

When the gate polysilicon film 415f of the uppermost layer is etched using the above-described etching gas, an inclined sidewall is formed on the gate polysilicon film 415f, and a first sidewall of the inclined sidewall and the etch barrier pattern 301 is formed. An etching auxiliary layer 435a is formed. Here, the first etching auxiliary layer 435a is formed of a residue such as a polymer generated by an etching gas used in the process of performing the first etching process.

The sidewall inclination θ of the gate polysilicon film 415f described above is preferably controlled to 5 ° to 45 ° with respect to the surface of the semiconductor substrate 401 or the surface of the gate polysilicon film 415f. The width d1 of the portion of the gate polysilicon film 415f forming the inclination is preferably controlled to 40 nm to 1000 nm.

Thereafter, the remaining gate polysilicon film 415f under the inclined sidewall is etched by the second etching process. In the gate polysilicon film 415f etched through the second etching process, sidewalls perpendicular to the surface of the gate polysilicon film 415f or the surface of the semiconductor substrate 401 may be formed. To this end, in the second etching process, the ratio of carbon and hydrogen is etched using an etching gas having a smaller content than in the first etching process. The second etching process may be performed using an etching gas including at least one of HBr and HI.

The first and second etching processes described above may be performed in-situ or ex-situ.

Referring to FIG. 4B, the interlayer insulating layer 413f below is etched using the third etching process while the first etching auxiliary layer 435a remains. In this case, it is preferable to use an etching gas such that the sidewalls of the etched interlayer insulating film 413f can be perpendicular to the surface of the interlayer insulating film 413f or the surface of the semiconductor substrate 401. When the interlayer insulating film 413f is an oxide film, the interlayer insulating film etched by etching the interlayer insulating film 413f by using a gas containing C, F including C, F, Cl ₂ gas, and HBr gas such as CHF. The side wall of 413f can be formed vertically.

The first to third etching processes described above may be performed using plasma etching equipment. In this case, the plasma etching apparatus may be performed by using a capacitively coupled plasma (CCP) type, an inductively coupled plasma (ICP) type, a microwave plasma type, or a mixture of two or more characteristics. .

Referring to FIG. 4C, the gate polysilicon layer 415e exposed by the etching of the interlayer insulating layer 413f is etched using the first and second etching processes described above with reference to FIG. 4A. As a result, the gate polysilicon layer 415e is patterned to include a sidewall perpendicular to the inclined sidewall, and a second etch auxiliary layer 435b is formed on the sidewall of the inclined sidewall and the first etching auxiliary layer 435a. By the second etching auxiliary layer 435b, the gate polysilicon layer 415e is patterned to have a wider width than the gate polysilicon layer 415f thereon.

Referring to FIG. 4D, the interlayer insulating layer 413e under the second etching auxiliary layer 435b is etched by the third etching process described above with reference to FIG. 4B while the second etching auxiliary layer 435b remains. As a result, vertical sidewalls are formed on the etched interlayer insulating layer 413e. In this case, the interlayer insulating film 413e is patterned to have a wider width than the interlayer insulating film 413f thereon by the second etching auxiliary film 435b.

Referring to FIG. 4E, the first to third etching processes are repeated until the lowermost gate polysilicon film 415a and the interlayer insulating film 413a are etched. At this time, whenever the gate polysilicon film of each layer is patterned, an etch auxiliary film is formed on the inclined sidewall, so that the gate polysilicon film and the interlayer insulating film are patterned to a greater width toward the lower layer.

After completion of etching the interlayer insulating films 413a, 413b, 413c, 413d, 413e, and 413f and the gate polysilicon films 415a, 415b, 415c, 415d, 415e, and 415f, the etching formed as a result of the repetition of the first to third etching processes The auxiliary layers and the photoresist pattern are removed. As a result, stepped steps are formed at the edges of the patterned interlayer insulating films 413a, 413b, 413c, 413d, 413e, and 413f and the gate polysilicon films 415a, 415b, 415c, 415d, 415e, and 415f. In particular, the sidewalls of the gate polysilicon films 415a, 415b, 415c, 415d, 415e, and 415f have an upper sidewall inclined with respect to the semiconductor substrate 401 and a lower side connected with the upper sidewall and perpendicular to the semiconductor substrate 401. And sidewalls.

As described above, in the present invention, an etching auxiliary layer may be formed on the sidewall of the gate polysilicon layer while simultaneously etching the gate polysilicon layer in the first etching process. As a result, an inclination is formed on the upper sidewall of the gate polysilicon layer formed by the first etching process, and an etching auxiliary layer is formed. The etching width of the lower layer may be uniformly controlled when the lower layer is etched in the subsequent process by using the etching auxiliary layer. As a result, it is possible to equalize the steps formed at the edges of the structure in which the interlayer insulating film and the gate polysilicon film are alternately stacked.

In the above, the method for uniformizing the step height around the gate pattern of the NAND flash memory device including the 3D memory cell has been described. However, the present invention is not limited thereto. It can also be applied at the time of pattern formation.

As described above, the present invention can secure a step at a constant distance to the edge of the stacked structure, thereby improving the yield of the nonvolatile memory device by improving the bridge due to misalignment during subsequent contact structure formation. .

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a schematic perspective view of a nonvolatile memory device including a three-dimensional memory cell;

FIG. 2 is a schematic cross-sectional view of a memory cell region of a nonvolatile memory device including three-dimensional memory cells. FIG.

3A to 3C are cross-sectional views illustrating a method of patterning the gate patterns of each layer to have stepped steps.

4A to 4E are cross-sectional views illustrating a three-dimensional nonvolatile memory device and a method of manufacturing the same according to the present invention.

<Explanation of symbols for main parts of the drawings>

413a, 413b, 413c, 413d, 413e, 413f: interlayer insulating film

415a, 415b, 415c, 415d, 415e, 415f: polysilicon film

435a, 435b: etching aid film

Claims (18)

A plurality of polysilicon films stacked on top of the semiconductor substrate and having a step to which a contact structure is connected; And Interlayer insulating films stacked between layers of the plurality of polysilicon films; Each of the plurality of polysilicon films exposed by the step includes an upper sidewall inclined with respect to the semiconductor substrate and a lower sidewall connected to the upper sidewall and perpendicular to the semiconductor substrate, And the interlayer insulating layer includes sidewalls perpendicular to the semiconductor substrate. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And the inclined upper sidewall is formed at an angle of 5 ° to 45 ° with respect to the semiconductor substrate. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, And a width of the polysilicon layer forming the inclined upper sidewall is 40 nm to 1000 nm. Forming a stacked structure in which a plurality of interlayer insulating films and a plurality of polysilicon films are alternately stacked on the semiconductor substrate; Forming an etching barrier pattern on the stacked structure; Performing a first etching process such that residues generated by etching the polysilicon layer exposed by the etching barrier pattern are deposited on the etched surface of the polysilicon layer to form an etch auxiliary layer; Etching the polysilicon film exposed through the etching auxiliary layer by a second etching process to expose the interlayer insulating film; Etching the exposed region of the interlayer insulating layer by a third etching process; And Repeating the first to third etching processes to etch each of the plurality of interlayer insulating layers and the plurality of polysilicon layers to form a step portion to which a contact structure is connected to the plurality of polysilicon layers. Method of manufacturing a memory device. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein The etching barrier pattern is a method of manufacturing a nonvolatile memory device formed of an organic material. Claim 6 was abandoned when the registration fee was paid. The method of claim 4, wherein The etching barrier pattern is a method of manufacturing a nonvolatile memory device formed of a photoresist pattern. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 4, wherein The first etching process is a method of manufacturing a nonvolatile memory device using an etching gas containing at least one of carbon and hydrogen. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein The etching gas used in the first etching process has a greater content of carbon or hydrogen than the etching gas used in the second etching process. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 7, wherein The etching gas used in the first etching process further comprises at least one of HBr and HI. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 4, wherein And a sidewall inclined with respect to the semiconductor substrate is formed in the polysilicon layer by the first etching process. Claim 11 was abandoned upon payment of a setup registration fee. 11. The method of claim 10, And the inclined sidewalls are formed at an angle of 5 ° to 45 ° with respect to the semiconductor substrate. Claim 12 was abandoned upon payment of a registration fee. 11. The method of claim 10, And a width of the polysilicon layer forming the inclined sidewall is 40 nm to 1000 nm. Claim 13 was abandoned upon payment of a registration fee. The method of claim 4, wherein And a sidewall perpendicular to the semiconductor substrate is formed in the polysilicon layer by the second etching process. Claim 14 was abandoned when the registration fee was paid. The method of claim 4, wherein And a sidewall perpendicular to the semiconductor substrate is formed in the interlayer insulating layer by the third etching process. Claim 15 was abandoned upon payment of a registration fee. The method of claim 4, wherein The first and second etching processes may be performed in-situ or ex-situ. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 4, wherein The third etching process is a method of manufacturing a nonvolatile memory device using a gas containing at least one of a gas containing C, F, Cl ₂ gas, and HBr gas. Claim 17 has been abandoned due to the setting registration fee. The first to third etching process is a method of manufacturing a nonvolatile memory device using a plasma etching equipment. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 17, The plasma etching apparatus may include a capacitively coupled plasma (CCP) type, an inductively coupled plasma (ICP) type, a microwave plasma type, or a combination of two or more characteristics. Manufacturing method.

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