KR101003495B1 - Semiconductor device having 4?2 transistor and the method for manufacturing the same - Google Patents

Abstract

A semiconductor device having a 4F2 transistor of the present invention, and a method of manufacturing the same, include a semiconductor substrate having an active region defined by an isolation layer; A first trench formed in a vertical structure in the active region; A second trench formed in a direction orthogonal to the first trench; A buried bit line formed in one direction of the semiconductor substrate while partially filling the first trench; A word line including a gate metal film pattern formed in a direction orthogonal to the buried bit line while partially filling the second trench, and a gate electrode contacting each surface of the gate metal film pattern; An insulating film separating the word line and the buried bit line; And an interlayer insulating film filling all of the second trenches.

4F2 Transistor, Bulb Trench, Gate Electrode

Description

Semiconductor device having 4F2 transistor and method for manufacturing same

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a 4F2 transistor and a manufacturing method thereof.

As the degree of integration of semiconductor devices increases, design rules are decreasing. As such design rules decrease, development of highly integrated semiconductor memory devices, for example, dynamic random access memory (DRAM) devices, is reaching a limit. Accordingly, studies are being conducted to reduce the unit area of cells storing one bit. Currently, research is being conducted to increase the number of chips that can be implemented on wafers by reducing the chip area of DRAM devices by implementing 1K unit cells in 6F2 and 4F2 in 8F2, which is a standard for storing 1 bit. . If the same design rule is applied, 4F2 transistor is being researched that can form a highly integrated cell than the current level. In order to configure the 4F2 transistor, the source and drain portions of the cell transistor, that is, the source portion of the capacitor formation region where the charges are stored and the drain portion that discharges the charges to the bit line, must be formed in 1F2. To this end, a study on a vertical type cell transistor structure capable of forming a source portion and a drain portion within 1F2 has been studied. The vertical cell transistor has a structure in which an active region is vertically formed in a cylinder on a wafer to simultaneously form an impurity region and a gate. That is, by configuring the source region and the drain region portion formed in a horizontal shape at 8F2 in the vertical shape of the upper and lower portions, the 1K cell transistor operation can be implemented in the 4F2. Such a vertical cell transistor can reduce the chip area as compared to the 8F2 structure, but may cause problems in forming a device of 50 nm or less. For example, a problem may occur in which a pillar neck having a diameter of about 20 nm formed in a pillar neck etching process that forms the active region in a cylindrical shape and proceeds to fill a gate conductive layer may not withstand the load of the pillar and is broken. Accordingly, there is a need for a method capable of forming a highly integrated cell structure while stably forming an active region having a vertical shape.

A semiconductor device having a 4F2 transistor according to the present invention includes a semiconductor substrate having an active region defined by an isolation layer; A first trench formed in a vertical structure in the active region; A second trench formed in a direction orthogonal to the first trench; A buried bit line formed in one direction of the semiconductor substrate while partially filling the first trench; A word line including a gate metal layer pattern formed in a direction orthogonal to the buried bit line while partially filling the second trench, and a gate electrode contacting each surface of the gate metal layer pattern; An insulating layer separating the word line and the buried bit line; And an interlayer insulating film filling all of the second trenches.

In the present invention, the semiconductor substrate may further include a junction region including a first junction region, a second junction region, and a third junction region sequentially formed from the bottom of the semiconductor substrate. The n-type impurity is implanted into the first junction region and the third junction region, and the p-type impurity is implanted into the second junction region.

The active region is a device isolation layer formed to surround each surface of the active region and has a square structure.

The second trench is formed at a position spaced apart from the first trench by a predetermined height with the insulating layer, the buried bit line is formed of a metal film, and the gate electrode is formed including a polysilicon film.

A method of manufacturing a semiconductor device having a 4F2 transistor according to the present invention includes forming a device isolation film defining an active region in a semiconductor substrate; Forming a bulb trench including a hole-shaped upper trench and a bulb-shaped lower trench in a vertical direction in an active region of the semiconductor substrate; Forming a gate insulating layer pattern on the lower trench exposed surface of the bulb shape; Etching the semiconductor substrate on which the gate insulating layer pattern is formed to form a first trench extending in one direction of the semiconductor substrate; Forming a gate electrode filling the bulb-shaped lower trench separated into a hemispherical shape while the first trench is formed; Forming a buried bit line filling a portion of the first trench; Filling all of the first trenches in which the buried bit lines are formed with an insulating layer; Etching the semiconductor substrate in a direction orthogonal to the first trench in which the insulating film is buried to form a second trench; Forming a word line including the gate electrode and the gate metal layer pattern by forming a gate metal layer pattern partially filling the second trench; And forming an interlayer insulating film filling all of the second trenches in which the gate metal film pattern is formed to form transistors including the buried bit lines and the word lines.

The device isolation layer may be formed in a square structure surrounding each surface of the active region.

After the forming of the device isolation layer, the method may further include forming a junction region in the semiconductor substrate, wherein the junction region may include a first junction region, a second junction region, and a third junction region sequentially formed from the bottom of the semiconductor substrate. It is preferable to include a junction area. The first junction region and the third junction region may be formed by implanting n-type impurities, and the second junction region may be formed by implanting p-type impurities.

The forming of the gate electrode may include filling all of the first trenches with a semiconductor layer; And etching the semiconductor layers of the upper and lower portions of the first trench by performing an etch back process on the semiconductor layer to form a gate electrode in the bulb-shaped lower trench separated into the hemispherical shape. desirable.

Preferably, the buried bit line includes tungsten.

The second trench may be formed by etching to a point where an insulating film having a predetermined thickness is secured on the buried bit line.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

1A to 11C are views illustrating a method of manufacturing a semiconductor device having a 4F2 transistor according to an embodiment of the present invention. 12 is a plan view showing a 4F2 type cell transistor according to the present invention from above.

1A to 1C, an isolation layer 110 defining an active region 102 is formed in a semiconductor substrate 100. Specifically, an isolation trench of a predetermined depth is formed in the semiconductor substrate 100. Next, the device isolation trench is filled with an insulating material, and then a planarization process is performed to form the device isolation layer 110 defining the active region 102. The device isolation layer 110 defining the active region 102 may be formed of an oxide layer. In this case, the active region 102 may be formed in an island structure in which each surface is surrounded by the device isolation layer 110. 1A is a perspective view schematically illustrating an embodiment of the present invention, and FIG. 1B is a cross-sectional view illustrating a portion of FIG. 1A taken along the AA ′ direction of the x-axis, and FIG. 1C is a BB ′ of the y-axis. It is sectional drawing which shows the part cut out in the direction. The description thereof will be omitted below.

2A through 2B, the junction region 130 is formed in the active region 102 (see FIG. 1A) formed on the semiconductor substrate 100. The junction region 130 is formed in the vertical direction of the semiconductor substrate 100 by performing an ion implantation process for implanting impurities into the semiconductor substrate 100 and then performing heat treatment. The junction region 130 formed in the semiconductor substrate 100 is formed by diffusing to a position where a gate conductive film is to be formed thereafter, and according to the type of impurities, the first junction region 115, the second junction region 120, and the third junction. The regions 125 are sequentially formed from the bottom of the semiconductor substrate 100. Here, the first junction region 115 and the third junction region 125 are formed by implanting n-type impurities, and the second junction region 120 is formed by implanting p-type impurities. In this case, the first junction region 115 that is first implanted and formed at the bottom of the junction region 130 is a region that sends electric charges to a bit line to be formed later. Next, the second junction region 120 becomes a channel through which a signal passes from the source region when the gate electrode is turned on / turn off. In addition, the third junction region 125 formed at the top layer of the junction region 130 serves to connect the storage node to be formed later and the lower electrode.

3A through 3C, a bulb trench 145 is formed in the junction region 130 formed on the semiconductor substrate 100. Specifically, a resist film is applied and patterned on the semiconductor substrate 100 to form a resist film pattern (not shown). The resist film pattern exposes a portion of the semiconductor substrate 100 in a hole shape. The portion exposed by the resist film pattern is a portion in which the junction region 130 is formed in the semiconductor substrate 100. Next, an etching process using the resist film pattern as an etching mask is performed to form a trench in the semiconductor substrate 100. The hole-shaped trench is formed by etching to the depth where the second junction region 120 is located among the junction regions 130. Subsequently, an isotropic etching is performed in which the etching proceeds in all directions inside the hole-shaped trenches, and laterally expanded to form a bulb-shaped trench. Accordingly, a bulb trench 145 including an upper trench 135 having a hole shape and a lower trench 140 having a bulb shape is formed in the junction region 130. During the isotropic etching process, the lower trench 140 may be extended from the lower portion of the upper trench 135 in the hole shape to the inner side of the semiconductor substrate 100 by the kind of impurities constituting the junction region 130. ) Can be implemented. In the bulb trench 145, the lower trench 140 having a bulb shape extending into the semiconductor substrate 100 is a region where a gate conductive layer is to be disposed.

4A through 4C, the gate insulating layer pattern 150 is formed on the exposed surface of the bulb-shaped lower trench 140. Specifically, a gate insulating film is formed on the semiconductor substrate 100 and the trench 145. The gate insulating layer may be formed by supplying an oxide source on the semiconductor substrate 100 to grow the oxide layer. Next, the gate insulating film formed on the hole-shaped upper trench 135 and the semiconductor substrate 100 is etched to form a space on the exposed surface of the bulb-shaped lower trench 140 as shown in FIGS. 4B and 4C. The gate insulating layer pattern 150 is formed.

5A through 5C, a first mask layer pattern 155 is formed on the semiconductor substrate 100 to define a region in which a bit line is to be formed. Specifically, a first mask layer pattern 155 is formed to selectively expose the semiconductor substrate 100 by applying a resist film on the semiconductor substrate 100 and performing a lithography process including an exposure and development process. do. The first mask layer pattern 155 extends in a direction crossing the bit line to be formed later, for example, in the y-axis direction of the semiconductor substrate 100 to form a line shape. Next, an etching process using the first mask layer pattern 155 as an etching mask is performed to form the first trenches 160 in the semiconductor substrate 100. The first trench 160 formed in the semiconductor substrate 100 is formed deeper than the first junction region 115 formed in the bottom portion of the junction region 130. The first trench 160 extends in the y-axis direction of the semiconductor substrate 100 and is formed in a line shape. Next, the first mask layer pattern 155 is removed by performing a strip process. Accordingly, as shown in FIGS. 5B and 5C, the lower trench 140 having the bulb shape is separated by the first trench 160, and the lower trench having the hemisphere shape is formed at both sides of the first trench 160. 140a and 140b are formed.

6A through 6C, gate electrodes 165 may be formed to fill hemispherical lower trenches 140a and 140b. Specifically, all of the first trenches 160 are filled with a semiconductor layer. The semiconductor layer can be formed of a polysilicon film. Next, an etch back process is performed on the semiconductor layer. Then, while the semiconductor layers of the upper and lower portions of the first trench 160 are etched, the semiconductor layer remains only inside the semi-spherical lower trenches 140a and 140b among the bulb trenches 145 formed in the semiconductor substrate 100. 165) is formed. Accordingly, referring to FIG. 6B, which is cut out in the x-axis direction of the semiconductor substrate 100, the gate electrode 165 is formed on both sides of the first trench 160 in a hemispherical shape, and is shown in the y-axis direction. Referring to 6c, it can be seen that it is formed in a circular shape.

7A through 7C, buried bit lines 170 may be formed by partially filling the first trenches 160 formed in the semiconductor substrate 100 with bit line conductive materials. The buried bit line 170 is formed along the first trench 160 formed to extend in the y-axis direction of the semiconductor substrate. Specifically, all of the first trenches 160 are filled with bit line conductive materials. The bit line conductive material may include tungsten (W). Next, an etch back process is performed on the buried bit line conductive material. Then, the bit line conductive material on the upper and lower portions of the first trench 160 is etched to form a buried bit line 170 partially filling the bottom surface of the first trench 160. The buried bit line 170 is formed as a drain portion through which a signal from a storage node to be formed later exits through the buried bit line 170. As shown in FIGS. 7B and 7C, the buried bit line 170 may be etched back to have a sufficient distance from the gate electrode 165 to prevent the buried bit line 170 from affecting the gate electrode 165 during operation of the device. It is desirable to proceed. As the buried bit line 170 is formed, the bit line using a metal material, for example, tungsten, can be used, thereby reducing the bit line resistance than using silicon.

8A to 8C, all remaining portions of the first trench 160 are filled with the insulating layer 175. The insulating film 175 may be formed of a silicon oxide film (SiO ₂ ). In addition, a planarization process, for example, a chemical mechanical polishing (CMP) process, may be performed to polish the insulating layer 175 to expose the surface of the semiconductor substrate 100. The insulating layer 175 separates the gap between the buried bit line 170 and the gate line to be formed later. In addition, the bulb trench 145 is separated into hemispherical lower trenches 140a and 140b while the insulating layer 175 fills the remaining portion of the first trench 160.

9A through 9C, a second mask layer pattern 180 defining a region in which a gate line is to be formed is formed on the semiconductor substrate 100. Specifically, a resist film is coated on the semiconductor substrate 100, and a second mask layer pattern 180 for selectively exposing the semiconductor substrate 100 is formed by performing a lithography process including an exposure and development process. The second mask layer pattern 180 extends in a direction perpendicular to the buried bit line 170, for example, in the x-axis direction of the semiconductor substrate 100, and is formed in a line shape. Next, an etching process using the second mask layer pattern 180 as an etching mask is performed to form a second trench 185 in the semiconductor substrate 100. The second trench 185 extends in the y-axis direction of the semiconductor substrate 100 and is formed in a line shape. The second trench 185 may be etched only to the point where the insulating layer 175 having a predetermined thickness remains on the buried bit line 170 to prevent the buried bit line 170 and the gate line to be formed later. Meanwhile, the gate electrode 165 separated in the hemispherical shape by the second trench 185 formed in the y-axis direction of the semiconductor substrate 100 is also separated in the y-axis direction. Accordingly, the gate electrode 165 is separated in the x-axis direction and the y-axis direction. Next, the second mask layer pattern 180 is removed by performing a strip process.

10A through 10C, the gate metal film pattern 190 extending in the direction perpendicular to the buried bit line 170 is formed while partially filling the second trench 185. Specifically, the gate metal film is formed on the second trench 185 to fill the gate metal film. The gate metal film may be formed of a tungsten (W) film. Next, an etch back process is performed on the gate metal layer to etch by a predetermined depth d to form a gate metal layer pattern 190 partially filling the second trench 185. In this case, as shown in FIGS. 10B and 10C, each surface of the gate metal film pattern 190 may be separated by the first trench 160 (see FIG. 5B) and the second trench 185 (see FIG. 9C). In contact with the gate electrode 165. Accordingly, a word line 195 including a gate metal layer pattern 190 for connecting an electric signal to the gate electrode 165 and the gate electrode 165 is formed. That is, the word line 195 includes the gate metal film pattern 190 formed in the direction perpendicular to the buried bit line 170 and the gate electrode 165 formed in the vertical direction of the semiconductor substrate 100.

11A through 11C, the remaining portion of the second trench 185 is filled with the interlayer insulating film 200, and the planarization process is performed. The interlayer insulating layer 200 may insulate the storage node contact plug and the word line to be formed later, and may be formed of a silicon oxide (SiO ₂ ) layer. As a result, a 4F2 trench type cell transistor is formed on the semiconductor substrate 100. Next, although not shown in the drawing, a landing plug and a storage node electrode are formed on the active region to connect the buried bit line, the word line, and the upper electrode formed thereunder. Referring to FIG. 12 showing a 4F2 type cell transistor according to the present invention, the channel C of the cell transistor is formed along the gate electrode 165 in contact with each surface of the gate metal film pattern 190. do.

The semiconductor device having the 4F2 transistor and the manufacturing method thereof according to the present invention can prevent the problem of pattern collapse by forming the 4F2 transistor having a pile structure instead of the pillar structure. In addition, instead of the 4F2 transistor having a pillar structure requiring a space of 4.8F or more to secure a space for forming the buried bit line and pillar structure, the active region is formed in a square structure to secure a higher density chip size. Can be. In addition, since the bit line using a metal material is possible, the bit line resistance can be reduced compared to using silicon. In addition, there is an advantage that the driving speed of the device increases by increasing the channel length compared to the pillar structure.

1A to 11C are views illustrating a method of manufacturing a semiconductor device having a 4F2 transistor according to an embodiment of the present invention.

12 is a plan view showing a 4F2 type cell transistor according to the present invention from above.

Claims (15)

A semiconductor substrate having an active region defined by an isolation layer; A first trench extending vertically in the active region; A bulb trench formed to surround a central portion of the first trench; A buried bit line formed by partially filling a bottom portion of the first trench with a metal film; A gate metal film pattern filling the bulb trench; An insulating layer separating the gate metal layer pattern and the buried bit line formed on the buried bit line; A second trench formed in a direction orthogonal to the first trench and crossing the gate metal film pattern; A word line including a gate electrode contacting each surface of the gate metal film pattern formed in a direction orthogonal to the buried bit line while partially filling the second trench, and the gate metal film pattern; And And a 4F2 transistor including an interlayer insulating film filling all remaining portions of the second trench. The method of claim 1, The semiconductor substrate has a 4F2 transistor further comprising a junction region including a first junction region, a second junction region, and a third junction region sequentially formed from the bottom of the semiconductor substrate. The method of claim 2, And a 4F2 transistor in which the first junction region and the third junction region are implanted with n-type impurities and the second junction region is implanted with p-type impurities. The method of claim 1, The active region is a semiconductor device having a 4F2 transistor formed in a square structure with a device isolation film formed surrounding each surface of the active region. The method of claim 1, And the second trench has a 4F2 transistor formed at a position spaced apart from the first trench by a predetermined height with the insulating layer. delete The method of claim 1, The gate electrode has a 4F2 transistor formed including a polysilicon film. Forming an isolation layer defining an active region in the semiconductor substrate; Forming a bulb trench including a hole-shaped upper trench and a bulb-shaped lower trench in a vertical direction in an active region of the semiconductor substrate; Forming a gate insulating layer pattern on the lower trench exposed surface of the bulb shape; Etching the semiconductor substrate on which the gate insulating layer pattern is formed to form a first trench extending in one direction of the semiconductor substrate; Forming a gate electrode filling the bulb-shaped lower trench separated into a hemispherical shape while the first trench is formed; Forming a buried bit line filling a portion of the first trench; Filling all of the first trenches in which the buried bit lines are formed with an insulating layer; Etching the semiconductor substrate in a direction orthogonal to the first trench in which the insulating film is buried to form a second trench; Forming a word line including the gate electrode and the gate metal layer pattern by forming a gate metal layer pattern partially filling the second trench; And And forming a transistor including the buried bit line and the word line by forming an interlayer insulating film filling all of the second trenches in which the gate metal film pattern is formed. The method of claim 8, And the device isolation film has a 4F2 transistor formed in a square structure surrounding each side of the active region. The method of claim 8, And forming a junction region in the semiconductor substrate after forming the device isolation film. The method of claim 10, And the junction region comprises a 4F2 transistor including a first junction region, a second junction region, and a third junction region sequentially formed from the bottom of the semiconductor substrate. The method of claim 11, And a 4F2 transistor in which the first junction region and the third junction region are formed by implanting n-type impurities, and the second junction region is formed by implanting p-type impurities. The method of claim 8, wherein the forming of the gate electrode comprises: Filling all of the first trenches with a semiconductor layer; And Performing an etch back process on the semiconductor layer to etch the semiconductor layers in the upper and lower portions of the first trench to form a gate electrode in the bulb-shaped lower trench separated into the hemispherical shape. Method for manufacturing a semiconductor device having a. The method of claim 8, The buried bit line is a manufacturing method of a semiconductor device having a 4F2 transistor formed by containing tungsten. The method of claim 8, And the second trench is formed by etching to the point where an insulating film having a predetermined thickness is secured on the buried bit line.

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