KR100940650B1 - Contact of electro static discharge device and semiconductor device and manufacturing method of contact for electro static discharge device and semiconductor device - Google Patents

Abstract

In an embodiment, a method of forming a contact between an antistatic device and a semiconductor device may include a TEOS layer and a BPSG layer on an active region, a first polygate, an active region of a semiconductor device, and a second polygate in the form of a blanket trench. Forming a PMD layer; Forming a contact pattern opening a portion of the first polygate; A first etching process step of over-etching the BPSG layer by isotropic etching based on a time point at which the TEOS layer under the contact pattern is exposed to form a first polygate trench; Performing anisotropic etching to remove the TEOS layer inside the first polygate trench and to remove the TEOS layer on the active region of the semiconductor device excluding the second polygate.

According to the embodiment, the normal contact of the antistatic device and the blanket contact of the semiconductor device may be simultaneously implemented through a single mask and an etching process, thus reducing the production cost and maximizing the yield.

Antistatic (ESD) Devices, MOSFETs, Normal / Blanket Contacts, Isotropic / Anisotropic Etching

Description

Contact of electrostatic discharge device and semiconductor device and method of contact formation of antistatic device and semiconductor device {Contact of electro static discharge device and semiconductor device and manufacturing method of contact for electro static discharge device and semiconductor device}

The embodiment discloses a contact structure of an antistatic element and a semiconductor element.

The embodiment also discloses a method for forming a contact for an antistatic device and a semiconductor device.

When a semiconductor device such as an electrostatic discharge (ESD) device and a metal-oxide semiconductor field-effect transistor (MOSFET) is simultaneously implemented on one substrate, a normal contact is formed in the antistatic device area. In addition, a blanket contact is formed in the semiconductor device region.

When the normal contact and the blanket contact are formed using a single mask, TEOS (Tetraethyl orthosilicate; Si (C ₂ H ₅ O ₄ )) and BPSG (Borophosphosilicate Glass) are sequentially formed in the antistatic device region and the semiconductor device region. By depositing to form a polysilicon-metal dielectric (PMD) layer, a pattern is formed to form a normal contact on the antistatic device poly. In this case, the blanket contact region does not require a pattern.

In the case of the normal contact, a trench in the shape of a wine glass is formed for a subsequent metal gap fill. After the isotropic etching, the anisotropic etching is performed to form a trench of a desired profile.

However, after the etching process, the phenomenon that the PMD layer, which should be secured to a certain amount or more, is excessively removed after the etching process occurs, thereby preventing insulation on the contact. This phenomenon can be explained by the following factors.

First, due to the different contact structures, the PMD layer of the antistatic device region is formed to have a thickness of about 6500 GPa, and the PMD layer of the semiconductor device region is formed to have a thickness of about 5200 GPa. Most will have to be removed.

That is, the BPSG of about 1000 GPa or less should be managed to be etched on the trench poly of the semiconductor device region, but due to the difference in thickness during deposition, the BPSG of about 2000 GPa or more may be etched on the trench poly.

Therefore, it is impossible to simultaneously form the contact of the antistatic device while managing the BPSG loss (Loss) of the semiconductor device area to about 1000 mW or less.

Second, in order to improve the contactability of the contact formed on the poly of the antistatic device, a sufficient amount of etching must be processed by using a mask, whereas the contact of the semiconductor device region maintains the etch rate as low as possible, thereby insulating the insulating film on the trench poly. Should be made less loss. This causes a contradictory situation for the contact etching process.

FIG. 1 is a photograph taken after contact etching of forming only a semiconductor device and forming a semiconductor device and an antistatic device together.

FIG. 1A illustrates only a case of forming a semiconductor device, in which a trench poly (a2) is formed on a substrate (a1), and a certain amount of BPSG (a3) remains on the trench poly (a2). It can be seen that the remaining BPSG (a2) performs an insulating film function with the metal layer (a4).

This is because the process margin can be secured only by etching for the blanket contact of the semiconductor device region.

On the other hand, (b) in the case where the semiconductor element and the antistatic element are formed together, the semiconductor element region is photographed, and the trench poly (b2) is formed on the substrate b1, and all the BPSGs are formed on the trench poly (b2). You can see it removed. This is because a contradictory situation has arisen for the contact etching process as described above.

In an embodiment, the insulating film formed on the normal contact of the antistatic device is etched to the maximum to improve conductivity, and the insulating film formed on the blanket contact of the semiconductor device is etched to the minimum so that the contact between the antistatic device and the semiconductor device is improved in insulation. To provide.

The embodiment provides a method for forming a contact capable of simultaneously implementing a normal contact of an antistatic device and a blanket contact of a semiconductor device through a single mask and an etching process.

The contact between the antistatic device and the semiconductor device according to the embodiment may include a first polygate for an antistatic device and a second polygate for a semiconductor device; A PMD layer formed in a region including at least the first polygate and the second polygate; And a first polygate trench formed on the first polygate and forming a wine glass from the top to the bottom of the PMD layer.

In an embodiment, a method of forming a contact between an antistatic device and a semiconductor device may include a TEOS layer and a BPSG layer on an active region, a first polygate, an active region of a semiconductor device, and a second polygate in the form of a blanket trench. Forming a PMD layer; Forming a contact pattern opening a portion of the first polygate; A first etching process step of over-etching the BPSG layer by isotropic etching based on a time point at which the TEOS layer under the contact pattern is exposed to form a first polygate trench; Performing anisotropic etching to remove the TEOS layer inside the first polygate trench, and removing the TEOS layer on the active region of the semiconductor device excluding the second polygate.

According to the embodiment, the normal contact of the antistatic device and the blanket contact of the semiconductor device may be simultaneously implemented through a single mask and an etching process, thus reducing the production cost and maximizing the yield.

A method of forming a contact between an antistatic device and a semiconductor device and a method of forming a contact between the antistatic device and the semiconductor device will be described with reference to the accompanying drawings.For convenience of description, the contact between the antistatic device and the semiconductor device and its formation are described. The method will be described together.

2 is a side cross-sectional view illustrating a form after the PMD layer 140 is deposited to form a contact between an antistatic device and a semiconductor device according to an exemplary embodiment.

Referring to FIG. 2, there is shown a structure of an antistatic device and a semiconductor device according to an embodiment before forming a contact. The left area A is an area where an antistatic device is formed, and the right area B is based on a dotted line. ) Is an area where a semiconductor element such as a MOSFET is formed.

A P type well layer, an N type well layer, an N + region, a P + region and the like (the region of the antistatic element is not specifically illustrated) are formed in the left active region A of the semiconductor substrate 105, for example, a single crystal silicon substrate. And a first polygate 110 is formed.

A first gate insulating layer 112 is formed between the first polygate 110 and the substrate 105.

A source region, a drain region, a channel region, etc. (the region of the semiconductor element is not specifically illustrated) are formed in the right active region B of the substrate 105, and the second polygate 120 is formed.

A second gate insulating layer 122 is formed between the second polygate 120 and the substrate 105.

As such, the PMD layer 140 is formed on the substrate in a state where the first polygate 110 of the antistatic device and the second polygate 120 of the semiconductor device are formed.

The PMD layer 140 includes a TEOS layer and a BPSG layer, wherein the TEOS layer is stacked about 1500 mW, and the BPSG layer is formed to a thickness of about 5000 mW thereon.

The TEOS layer and the BPSG layer are similar oxide film materials, but it is difficult to distinguish them with the naked eye.

At this time, the antistatic device region A and the semiconductor device region B have different topologies, which affect the thickness of the PMD layer 140 and thus the PMD layer of about 6500 kPa (d1) on the first polygate 110. 140 is formed, but a PMD layer 140 of about 5200 kPa (d2) is formed on the substrate 105 including the second polygate 120.

3 is a side cross-sectional view illustrating a form after the contact pattern 150 of the antistatic device and the semiconductor device according to the embodiment is formed.

Next, a photolithography process is performed to form a contact pattern 150 on the PMD layer 140 of the first polygate 110.

The contact pattern 150 includes a photoresist, and opens a portion of the PMD layer 140 to form a trench that exposes the first polygate 110.

4 is a side cross-sectional view illustrating a form after a first etching process for forming a contact between an antistatic device and a semiconductor device according to an embodiment is processed.

Subsequently, the first etching process is processed, and the first etching process is performed by a dry etching apparatus of a plasma type, in which process parameters can be easily adjusted.

The process variables may be adjusted to implement different isotropic etching characteristics and profiles, and as shown in FIG. 4, the PMD layer 140 on the first polygate 110 is etched in the form of wine glass.

In this case, the first etching process is performed by excessively etching the BPSG layer 141 until the TEOS layer 142 of the PMD layer 140 is exposed, so that the inner wall of the wine glass trench 152 has a large inclination angle. do.

In addition, when the isotropic etching amount is increased by a predetermined level or more, the BPSG layer 141 on the contact pattern 150 is etched faster than the BPSG 141 on the blanket contact of the semiconductor device region.

This is commonly referred to as the "loading effect".

The loading effect is recognized as a problem by causing a difference in etching rate in a general etching process, but in the embodiment, the BPSG layer 141 on the contact pattern 150 and the BPSG on the second polygate 120 may be reversed by using the loading effect. The difference in thickness after etching of 141 may be minimized.

That is, the BPSG layer 141 on the first polygate 110 has a thickness of about 6500 GPa, and the BPSG layer 141 on the second polygate 120 has a thickness of about 5200 GPa. The BPSG layer 141 on the two polygates 120 may be managed to etch only 1000 Å or less layers.

Therefore, according to the embodiment, the loss of the BPSG layer 141 on the second polygate 120 can be managed at about 1000 Hz or less, and the contacts of the antistatic device and the semiconductor device can be simultaneously formed.

Referring to FIG. 4, it can be seen that all of the BPSG layers 141 remain on the blanket trenches on the second polygate 120 without being removed.

5 is a side cross-sectional view illustrating a form after a second etching process for forming a contact between an antistatic device and a semiconductor device according to an embodiment is processed.

Subsequently, a second etching process is processed, wherein the second etching process is performed by an anisotropic etching equipment.

That is, the etching process for forming the contact between the antistatic device and the semiconductor device according to the embodiment is processed through two different etching processes, and using an etching apparatus provided with an anisotropic etching chamber and an isotropic etching chamber is more effective. I can handle it easily.

The second etching process is performed in an EPD (Endpoint) method, and the main etching process is performed using the time point at which the surface of the substrate 105 is drawn as an etching end point, and then the over etching is performed as short as possible.

Accordingly, the TEOS layer 142 located on the bottom surface of the trench 152 in the antistatic element region is etched, and the TEOS layer on the substrate except for the blanket trench and the contact pattern 150 on the second polygate 120 ( 142 is etched away.

6 is a photograph of a contact structure of an antistatic device and a semiconductor device according to an embodiment.

FIG. 6A illustrates a contact of a semiconductor device region, in which the BPSG layer 141 on the blanket trench is etched only about 1200 Å and remains inside the trench.

FIG. 6 (b) shows the trench 152 of the antistatic element region after the contact pattern 150 is removed, which is wide wine glass, the TEOS layer 142 is removed, and the first polygate. It can be seen that 110 is exposed.

Subsequently, a metal layer may be formed on the entire surface of the substrate including the trench on the first polygate 110 and the blanket trench on the second polygate 120 to proceed with the metal wiring process.

The present invention has been described above with reference to the preferred embodiments, which are merely examples and are not intended to limit the present invention, and those skilled in the art to which the present invention pertains do not depart from the essential characteristics of the present invention. It will be appreciated that various modifications and applications are not possible that are not illustrated above. For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

FIG. 1 is a photograph taken after contact etching of forming only a semiconductor device and forming a semiconductor device and an antistatic device.

Figure 2 is a side cross-sectional view showing the form after the PMD layer is deposited to form a contact between the antistatic device and the semiconductor device according to the embodiment.

Figure 3 is a side cross-sectional view showing the form after the contact pattern of the antistatic element and the semiconductor element according to the embodiment.

4 is a side cross-sectional view illustrating a form after a first etching process for forming a contact between an antistatic device and a semiconductor device according to an embodiment is processed;

FIG. 5 is a side cross-sectional view illustrating a form after a second etching process for forming a contact between the antistatic device and the semiconductor device according to the embodiment is processed; FIG.

6 is a photograph of a contact structure of an antistatic device and a semiconductor device according to an embodiment;

Claims (9)

A contact formed in a region of a substrate including a first polygate for an antistatic element and a second polygate for a semiconductor element, the contact formed in a PMD layer including a TEOS layer and a BPSG layer, A first polygate trench formed on the first polygate, forming a wine glass from above to below the PMD layer, and removing the TEOS layer on an inner surface thereof; And And an antistatic device and a semiconductor device formed on a blanket trench formed on the substrate over the second polygate and having the TEOS layer and the BPSG layer formed on an inner surface thereof. delete Forming a PMD layer including a TEOS layer and a BPSG layer on the active region of the antistatic device, the first polygate, the active region of the semiconductor device, and the second polygate in the form of a blanket trench; Forming a contact pattern opening a portion of the first polygate; A first etching process step of over-etching the BPSG layer by isotropic etching based on a time point at which the TEOS layer under the contact pattern is exposed to form a first polygate trench; And performing a anisotropic etching process to remove the TEOS layer inside the first polygate trench and to remove the TEOS layer on the active region of the semiconductor device except for the second polygate. And contact forming method of a semiconductor device. The method of claim 3, wherein the first etching process is A method for forming a contact between an antistatic device and a semiconductor device, comprising a dry etching device of a plasma method capable of implementing various isotropic etching characteristics and profiles by adjusting process variables. The method of claim 3, wherein in the first etching process step, The first polygate trench is etched from the surface of the BPSG layer under the contact pattern to the bottom in the form of a wine glass, the method of forming a contact between the antistatic device and the semiconductor device. The method of claim 3, wherein in the first etching process step, The TEOS layer is exposed to an inner bottom of the first polygate trench, The method of forming a contact between an antistatic device and a semiconductor device, characterized in that the BPSG layer remains in the blanket trench of the second polygate. The method of claim 3, wherein the first etching process and the second etching process A method of forming a contact between an antistatic device and a semiconductor device, characterized in that the etching process is performed using an anisotropic etching chamber and an isotropic etching chamber together. The method of claim 3, wherein the second etching process The method of forming an contact between an antistatic device and a semiconductor device, wherein the process is performed in an EPD method, and the main etching process is performed using the time point at which the surface of the substrate is exposed as the etching end point, and the over etching is performed. The method of claim 3, Removing the contact pattern; And And depositing a metal in the substrate region including the first polygate trench and the blanket trench to perform a metal wiring process.

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