KR100653035B1 - Method of forming a dielectric spacer in a semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming an insulating film spacer of a semiconductor device, wherein the insulating material layer is thinly formed in the region where the gate electrode is narrow, and additionally, the insulating material layer is additionally formed only when the gap is wide to form a primary spacer, and then the entire surface is etched. By performing the process, the insulating film spacers are prevented from being connected to each other in the region where the gate electrode spacing is narrow. A method of forming an insulating film spacer is disclosed.

Insulator Spacer, Gate Electrode Spacing, Micro Loading Effect, LPD, SiOF

Description

Method for forming an insulating film spacer of a semiconductor device             

1 is a cross-sectional view of a device in a state where an insulating film spacer is formed on the sidewall of a gate electrode.

2 is a planar photograph and a sectional photograph in a state where an insulating film spacer is formed on sidewalls of a gate electrode.

3A to 3F are cross-sectional views of a device for explaining a method of forming an insulating film spacer of a semiconductor device according to the present invention.

<Explanation of symbols for main parts of the drawings>

11, 31: semiconductor substrate 12, 32: gate oxide film

13, 33: gate electrode 14, 300: insulating film spacer

14a: portion where insulating film spacers are connected 34: oxide film

35 nitride film 36 photoresist pattern

37: SiOF film

The present invention relates to a method of forming an insulating film spacer of a semiconductor device, and in particular, to form a thin insulating film spacer on the sidewall of the gate to prevent the insulating film spacer contact of the insulating film spacer in a narrow gate interval region. It is about.

In general, the source and the drain are formed in a lightly doped drain (LDD) structure in order to prevent short channel effects from occurring in the transistor.

Punch, breakdown, and leakage current of the gate oxide layer by hot carriers when the source and drain are formed in an LDD structure in which the concentration of impurities increases as the source and drain are moved away from the gate electrode. Can be prevented from occurring.

The source and the drain of the LDD structure are composed of a low concentration impurity region and a high concentration impurity region. The low concentration impurity regions are formed at shallow depths on both sides of the gate, and the high concentration impurity regions are formed on both sides of the insulating film spacers after the insulating film spacers are formed on the sidewalls of the gate electrodes.

The insulating film spacer is formed by forming an insulating material (for example, an oxide film or a nitride film) over the entire surface and then leaving the insulating material only on the sidewall of the gate electrode through a front surface etching process. At this time, the characteristics of the short channel effect and the reverse short channel effect vary greatly according to the width of the insulating layer spacer and the thermal history in the forming process.

In recent years, as semiconductor devices have been highly integrated, not only metal wirings but also the widths and spacings of gate electrodes have decreased, but the thickness of the insulating film spacers formed on the sidewalls of the gate electrodes has not decreased.

1 is a cross-sectional view of a device in which an insulating film spacer is formed on sidewalls of a gate electrode, and FIG. 2 is a plan view and a cross-sectional picture in a state in which insulating film spacers are formed on sidewalls of the gate electrode.

Referring to FIG. 1, there is an area having a large gap between the gate electrode 13 and an area having a narrow gap according to the pattern of the gate oxide film 12 and the gate electrode 13 formed on the semiconductor substrate 11.

When the design rule of the device is 0.13 μm, the gap A of the gate electrode 13 is 0.18 μm. In general, since the insulating film spacers 14 are formed to a thickness of about 0.08 μm, the insulating film spacers 14 are likely to be connected between the gate electrodes 13.

In particular, as the spacing of the gate electrode 13 decreases, the etching rate in a region where the spacing of the gate electrode 13 is narrow due to a micro-loading effect during the entire surface etching process for forming the insulating film spacer 14. This decreases, so that the thickness of the insulating film spacers 14 increases, so that the possibility that the insulating film spacers 14 are connected to each other becomes higher.

Referring to FIG. 2, it can be seen that the micro loading effect is generated during the entire surface etching process so that the insulating film spacers 14 are connected to each other 14a in the region where the gate electrode 13 is narrow.

As described above, when the insulating film spacers 14 are connected to each other, an insulating material remains on the semiconductor substrate 11 in the region where the source / drain is to be formed, or the semiconductor substrate 11 is not opened to form a source / drain. High concentration ion implantation process is not performed smoothly.

As a result, the impurity concentration of the source / drain decreases to increase the resistance, or, in severe cases, the impurity may not be injected, thereby causing a defect. In addition, since a salicide layer is not formed on the source / drain (not shown) on which the insulating film spacers 14 are formed, contact resistance with a contact plug to be formed in a subsequent process is increased, thereby deteriorating electrical characteristics.

The biggest problem that occurs when the insulating film spacers 14 are connected to each other is that the resistance of the source / drain or the contact resistance with the contact plug becomes uneven according to the distance between the gate electrodes 13. As a result, the overall electrical characteristics of the device is lowered, resulting in a problem that the reliability of the process is lowered.

Accordingly, in order to solve the above problem, the present invention is to form a thin insulating material layer in the region where the gate electrode is narrow and additionally form an insulating material layer only when the gap is wide to form a primary spacer and then perform a front etching process. By preventing the insulating film spacers from being connected to each other in the region where the gate electrode spacing is narrow, the insulating film spacer of the semiconductor device can improve the device characteristics and process reliability by securing the insulating film spacer length required for the device implementation when the electrode spacing is wide. The purpose is to provide a formation method.

In the method of forming an insulating film spacer of a semiconductor device according to the present invention, a thick insulating material layer is formed in a region having a wider interval than a narrow region of the gate electrode, and then a front etching process is performed based on the thickly formed insulating material layer. By forming a thinner insulating film spacer formed in a narrower region than an insulating film spacer formed in a wide interval, the insulating film spacers can be prevented from being connected to each other in a region where the gate electrode is narrow.

In the method of forming an insulating film spacer of a semiconductor device according to another exemplary embodiment of the present invention, a gate electrode is formed in a predetermined pattern, and the semiconductor substrate is divided into a first region having a wide interval and a second region having a narrow interval according to the distance between the gate electrodes. The step of providing the step, the step of sequentially forming an oxide film and a nitride film on the semiconductor substrate, the step of forming a photoresist pattern opening only the first region, and an insulating film made of silicon oxide on the nitride film of the first region And forming an insulating film spacer formed of a nitride film and an oxide film on the sidewall of the gate electrode by forming the photoresist pattern, removing the photoresist pattern, and performing an entire surface etching process.

In the above, the silicon oxide is SiOF, and the silicon oxide is formed by the LPD method. The LPD method is characterized in that SiOF is formed only on top of an insulating film containing silicon and oxide by dipping a semiconductor substrate in a mixed aqueous solution in which H ₃ BO ₃ is added to a supersaturated H ₂ SiF ₆ aqueous solution at room temperature.

After forming the insulating film, an insulating film entire surface etching process may be performed to leave the insulating film only on the sidewall of the nitride film of the first region. The entire surface of the insulating layer is etched while CHF ₃ , CF _4, and Ar are supplied while a bias of 200 to 400 W is applied to the chamber, and the chamber pressure is maintained at 800 to 1000 mTorr. In this case, the supply amount of CHF ₃ is 20 to 40 sccm, the supply amount of CF ₄ is 40 to 60 sccm, and the supply amount of Ar is 900 to 1100 sccm. In addition, the insulating film whole surface etching process is performed in the state which ensures the selection ratio of an insulating film and a nitride film sufficiently.

In the front surface etching process, the target etching thickness is set based on the total thicknesses of the insulating film, the nitride film, and the oxide film formed in the first region, so that the insulating film spacer of the second region is formed thinner than the insulating film spacer of the first region. The front etching process is performed while CHF ₃ , CF _4, and Ar are supplied while a bias of 200 to 400 W is applied to the chamber, and the pressure of the chamber is maintained at 800 to 1000 mTorr. At this time, the supply amount of CHF ₃ is 0 to ₄₀ sccm, the supply amount of CF ₄ is 80 to 100 sccm, the Ar supply amount is 900 to 1100 sccm.

On the other hand, it is determined whether the nitride film on the upper surface of the semiconductor substrate is completely etched through the EPD while the entire surface etching process is performed. When the etching of the nitride film is completed, the entire surface etching process is stopped, and the remaining HF-based solution remains on the semiconductor substrate. Remove the oxide film. This prevents etching damage from occurring in the semiconductor substrate.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

3A to 3F are cross-sectional views of devices for explaining a method of forming insulating film spacers of a semiconductor device according to the present invention.

Referring to FIG. 3A, the gate oxide layer 32 and the gate electrode 33 are formed on the semiconductor substrate 31 in a predetermined pattern. Depending on the region, low concentration ion implantation layers (not shown) are formed on both sides of the gate electrode 33 to form the source / drain in an LDD structure.

Referring to FIG. 3B, an oxide film 34 and a nitride film 35 for sequentially forming insulating film spacers are sequentially formed over the entire surface.

The first oxide film 34 is formed to have a thickness of 100 to 150 Å by thermal chemical vapor deposition (Thermal CVD) or plasma chemical vapor deposition (Plasma CVD), and the nitride film 35 is the same as the method of forming the oxide film 34. By a thickness of 600 to 800 kPa.

In this case, the thickness of the oxide film 34 and the nitride film 35 deposited on the isolated gate line is about 100 to about 200 microseconds in consideration of the film deposited in a subsequent liquid phase deposition (LPD) process. Form thin enough.

Referring to FIG. 3C, the photoresist pattern 36 is formed on a region where the gap between the gate electrodes 33 is tight, so that only the gate electrodes 33 having a large gap are exposed.

Referring to FIG. 3D, the SiOF film 37 is formed by the LPD method only on the exposed surface of the nitride film 35 without forming the photoresist pattern 36. At this time, the SiOF film 37 is formed to a thickness of 200 to 500 kPa.

A method of selectively forming the SiOF film 37 only on the exposed surface of the nitride film 35 by LPD (Liquid Phase Deposition) method will be described below.

Dipping a semiconductor substrate in a mixed aqueous solution of Boric Acid (H ₃ BO ₃ ) in a supersaturated aqueous solution of Hydrofluosilicic Acid (H ₂ SiF ₆ ) at room temperature results in SiOF (Fluorinate Silica Glass (FSG)) only on top of the insulating film containing silicon and oxide. Is grown.

At this time, since the SiOF film is not formed on the surface of the photoresist pattern, the SiOF film 37 is not formed by the photoresist pattern 36 in the region where the gap between the gate electrodes 33 is dense.

In the LPD (Liquid Phase Deposition) method, the photoresist pattern 36 is formed in a region where the gap between the gate electrodes 33 is dense, and the gap between the gate electrodes 33 is not dense using the above principle. The SiOF film 37 is selectively formed only on the surface of the nitride film 35 in the region. In addition, since the LPD method proceeds at room temperature, there is no thermal history, thereby preventing deterioration of device characteristics.

Referring to FIG. 3E, the SiOF film 37 is etched by the first front dry etching process and left only in the sidewall of the nitride film 35 in the form of a spacer. As a result, the overall thickness of the films 34, 35, and 37 formed on the sidewalls of the wide-gap gate electrodes 33 becomes thicker than the overall thickness of the films 34, 35 formed on the sidewalls of the narrow-gap gate electrodes 33. .

The removal of the SiOF film 37 formed by the LPD method on the upper part of the gate electrode 33 having a large interval in advance by the primary front side etching process is performed so that the film thickness formed on the gate electrode 33 is the gap between the gate electrode 33. It is difficult to set the target etching thickness in the subsequent secondary front side etching process for forming the insulating film spacer if it is different in this wide area and narrow area, which may cause damage to the surface of the semiconductor substrate 31.

In the above, the first front etching process is performed while CHF ₃ , CF _4, and Ar are supplied while a bias of 200 to 400 W is applied to the chamber. At this time, the pressure of the chamber is 800 to 1000mTorr, the flow rate of CHF ₃ supplied is 20 to 40sccm, the flow rate of CF ₄ is 40 to 60sccm, the flow rate of Ar is 900 to 1100sccm.

On the other hand, in order to prevent the thickness of the nitride film 35 formed on the upper portion of the gate electrode 33 having a wide interval due to over etching, the primary ratio is sufficiently secured while the selectivity between the oxide film and the nitride film is sufficiently secured. Conduct a full surface etch process.

Referring to FIG. 3F, after removing the photoresist pattern, a second front surface etching process is performed to form an insulating film spacer 300. In the process of performing the secondary front side etching process, the SiOF film is completely removed, and the insulating film spacer 300 including the oxide film 34 and the nitride film 35 is formed on the sidewall of the gate electrode.

In this case, the secondary front side etching process is performed such that the insulating layer spacer 300 having a target thickness is formed based on the total thickness of the films 34, 35, and 37 formed on the sidewalls of the gate electrode 33 having a wide interval. As a result, during the secondary front surface etching process, a larger amount is etched in a region where the interval between the gate electrodes 33 is narrower than that of the region where the gate electrode 33 is wider, so that the insulating layer spacer 300 formed on the sidewall of the narrow gate electrode 33 is etched. It is formed to a thickness thinner than the insulating film spacer 300 formed on the sidewall of the gate electrode 33 having a large interval. Therefore, it is possible to prevent the insulating film spacers 300 from being connected to each other by the micro loading phenomenon.

In the above, the secondary front side etching process is performed while CHF ₃ , CF _4, and Ar are supplied while a bias of 200 to 400 W is applied to the chamber. At this time, the pressure of the chamber is 800 to 1000mTorr, the flow rate of CHF ₃ supplied is 0 to 20sccm, the flow rate of CF ₄ is 80-100sccm, the flow rate of Ar is 900-1100sccm.

In addition, the second front surface etching process is performed to determine whether the nitride film 35 on the semiconductor substrate 31 is completely etched through end point detection (EPD), and when the etching of the nitride film 35 is completed, the second front surface etching is performed. Abort the process.

Thereafter, the oxide layer 34 remaining on the semiconductor substrate 31 is removed using a diluted HF-based solution. As a result, the insulating film spacer 300 is formed while preventing etching damage from occurring on the surface of the semiconductor substrate 31.

As described above, the present invention prevents the insulating film spacers from being connected to each other, so that the ion implantation process for forming the source / drain is performed smoothly, and thus the self-resistance of the source / drain can be prevented from increasing. The salicide layer may be smoothly formed on the top to reduce contact resistance.

Claims (13)

A method of forming an insulating film spacer of a semiconductor device in which an insulating material layer is formed over the entire surface including a gate, and then the insulating material layer is left only on the sidewalls of the gate to form an insulating film spacer. The insulating material layer is formed thicker in the area larger than the narrow area of the gate electrode, and then the entire surface etching process is performed based on the thicker insulating material layer, which is narrower than the insulating film spacer formed in the wide area of the gate electrode. The thinner insulating film spacer formed in the region can be prevented from being connected to each other in the region where the gate electrode is narrower. Providing a semiconductor substrate in which a gate electrode is formed in a predetermined pattern, and divided into a first region having a large spacing and a second region having a narrow spacing according to the spacing of the gate electrode; Sequentially forming an oxide film and a nitride film on the semiconductor substrate; Forming a photoresist pattern in which only the first region is opened; Forming an insulating film made of silicon oxide on the nitride film of the first region; Removing the photoresist pattern; And forming an insulating film spacer comprising the nitride film and the oxide film on a sidewall of the gate electrode by performing an entire surface etching process. The method of claim 2, The silicon oxide is SiOF, characterized in that the insulating film spacer forming method of a semiconductor device. The method of claim 2 or 3, The silicon oxide is formed by the LPD method, the insulating film spacer forming method of a semiconductor device. The method of claim 4, wherein In the LPD method, the semiconductor substrate is immersed in a mixed aqueous solution in which H ₃ BO ₃ is added to a supersaturated H ₂ SiF ₆ aqueous solution at room temperature, so that SiOF is formed only on top of the insulating film containing silicon and oxide. Spacer Formation Method. The method of claim 2, And forming the insulating film in an entire surface etching step after forming the insulating film, thereby leaving the insulating film only on the sidewalls of the nitride film in the first region. The method of claim 6, The insulating layer front side etching process is performed while CHF ₃ , CF _4, and Ar are supplied while a bias of 200 to 400 W is applied to the chamber, and the pressure of the chamber is 800 to 1000 mTorr. Way. The method of claim 7, wherein The supply amount of CHF ₃ is 20 to 40 sccm, the supply amount of CF ₄ is 40 to 60 sccm, and the supply amount of Ar is 900 to 1100 sccm. The method according to claim 6 or 7, And etching the entire surface of the insulating film in a state where the selectivity between the insulating film and the nitride film is sufficiently secured. The method of claim 2, In the front surface etching process, a target etching thickness is set based on the total thicknesses of the insulating film, the nitride film, and the oxide film formed in the first region, so that the insulating film spacer of the second region is thinner than the insulating film spacer of the first region. An insulating film spacer forming method of a semiconductor element. The method according to claim 2 or 10, The front surface etching process is performed while CHF ₃ , CF _4, and Ar are supplied while a bias of 200 to 400 W is applied to the chamber, and the pressure of the chamber is 800 to 1000 mTorr. . The method of claim 11, The supply amount of CHF ₃ is 0 to ₄₀ sccm, the supply amount of CF ₄ is 80 to 100 sccm, and the supply amount of Ar is 900 to 1100 sccm. The method of claim 2, It is determined whether the nitride film on the semiconductor substrate is completely etched through the EPD while performing the entire surface etching process, and when the etching of the nitride film is completed, the entire surface etching process is stopped and the semiconductor is diluted using a diluted HF-based solution. And removing the oxide film remaining on the substrate.

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