KR100946798B1 - Dynamic range enhanced Sigma-delta modulator - Google Patents

Abstract

It is an object of the present invention to obtain a high SNR by improving the operating range of the integrator and preventing saturation of the output. It is also an object to increase the SNR without using a high sampling frequency.

In order to achieve the above object, the present invention creates two ideas. One is feed-forward technology to improve the saturation problem of integrators. The other is a dual phase comparison to increase the signal-to-noise ratio without increasing the sampling frequency. The sigma-delta modulator of the present invention comprises a first integrator and a second integrator, the input signal is feedforwarded to the input of the second integrator and the input of the comparator via the first gain circuit and the output of the comparator is the first integrator and the first integrator. 2 negative feedback to the integrator. The comparator may also consist of two latched comparator elements.

Sigma Delta Modulator, Secondary System, Dynamic Range, ADC, DAC, Aliasing, Signal-to-Noise Ratio

Description

Dynamic range enhanced Sigma-delta modulator}

1 is a schematic block diagram of a sigma delta modulator of the prior art.

2 is a block diagram illustrating a secondary system to which a feed forward technique is applied according to an embodiment of the present invention.

Figure 3 is a graph comparing the output of the integrator with the embodiment of the present invention and the prior art.

4 is a graph showing the integrator output of an embodiment of the present invention with an input signal having a peak voltage of 4Vpp at a 5V power supply.

5 is a diagram illustrating a comparator according to an embodiment of the present invention.

6 is a signal diagram illustrating the operation of a comparator according to an embodiment of the present invention.

7 is a circuit diagram illustrating a design of a sigma-delta modulator according to an embodiment of the present invention.

8 is a circuit diagram illustrating an embodiment of the present invention implemented using an operational amplifier.

9 is a circuit diagram illustrating an embodiment of the present invention implemented using a transconductor.                 

FIG. 10A is a graph illustrating simulation results with a 4 ohm load using a 5V power supply in the circuit shown in FIG. 9.

FIG. 10B is a graph showing simulation results with a 4 ohm load with a 5V power supply in a sigma delta modulator of the prior art.

11 is a graph comparing the signal-to-noise ratio of the embodiment of the present invention and the prior art.

The present invention relates to a sigma-delta modulator with improved dynamic range. More specifically, it relates to a second order sigma-delta modulator for switched power amplifiers with improved dynamic range and increased signal-to-noise ratio.

The sigma-delta modulation theory proposed by Cutler in 1954 is widely used in the field of demanding analog / digital conversion systems with high resolution and dynamic range.

In conventional analog-to-digital converters (hereinafter referred to as ADCs), the resolution depends on the number of internal comparators and the resolution of the internal digital-to-analog converters (hereinafter referred to as DACs). To reduce the number of comparators, many architectures have been developed, such as pipelined ADCs, folding ADCs, interpolated ADCs and subranging ADCs. This technique drastically reduces the number of comparators to achieve high resolution. However, despite the reduced components, these techniques require the accuracy of the operation of analog circuits in particular, such as error amplifiers and comparators.

However, in sigma-delta modulation techniques, the resolution problem is solved through sampling frequency and noise shaping techniques. Thus, sigma-delta modulation is not impeded by the problem of accuracy in the analog portion. With sigma-delta modulation using a digital lowpass filter with very sharp transition band and very high stopband attenuation, it is possible to obtain high resolution. Sigma-delta technology is also used in some discrete time systems such as motor drivers, switched power amplifiers, and direct current / dc converters.

The sigma-delta modulation technique is well known to those skilled in the art, and will be briefly described with reference to the accompanying drawings.

1 shows a block diagram of a first order sigma-delta modulator.

In general, the modulator consists of two blocks: an integrator and a comparator. In particular, the number of integrators determines the order of the sigma-delta modulator.

The block diagram (b) of FIG. 1 shows a small signal linear model of a sigma delta modulator. As shown in block diagram (b) of FIG. 1, voltage Vin, voltage Vo and voltage Vn represent the input signal, output signal and quantization noise of the comparator, respectively. Herein, it is assumed that the quantization noise Vn is uncorrelated with the input signal, and when the loop equation is solved, a transfer function such as Equation 1 can be obtained.                         

As can be seen from Equation 1, the input signal is low pass because of the negative feedback loop and integrator, while the noise signal is high pass. Therefore, if you use a low pass filter, you will get high resolution or high signal-to-noise ratio (SNR) at the output. In general, SNR is proportional to the order, sampling frequency, and number of bits in the ADC. The SNR may be obtained from Equation 2.

In Equation 2, n is the number of bits of the comparator, k is the order, M is the over-sampling rate indicating the ratio of the sampling frequency and the Nyquist sampling frequency.

As mentioned above, the SNR is improved in proportion to the number of integrators. However, in higher order systems, excessive phase shift makes the entire system unstable. Although solutions for higher order systems are being studied, these stability issues are still considered problems in higher order systems. When a large input signal is applied, the gain of the comparator is reduced and the SNR is reduced. Thus, in switched power amplifier devices, higher order systems limit the dynamic range of input and output. In low voltage applications, the problem of low dynamic range is very serious. Here, the dynamic range may be expressed in decibels (dB) as a ratio between the highest signal and the lowest signal.

In a secondary system, the integrator output follows the input signal. Thus, the integrator output saturates at high input signals. The integrator has past and present information. Thus, the loss information causes an increase in distortion and a decrease in signal-to-noise ratio.

In order to achieve a high signal-to-noise ratio in the secondary system, a higher sampling frequency than the primary system is needed to compensate for the lack of orders. However, in power amplifiers, high frequency operation requires large output transistors, increasing switch losses and heat losses. Therefore, it is very important to drive with a more relaxed sampling frequency. Another way to increase the signal-to-noise ratio is to use a multi-bit ADC instead of the single-bit comparator derived in equation (2). However, this is not allowed in a digital amplifier because the output transistors exhibit only two levels of high and low states.

Therefore, the present invention proposes a design of a new secondary system in order to solve the above-mentioned problems of the prior art. That is, the present invention aims to obtain a high SNR by improving the dynamic range of the integrator and preventing saturation of the output. It is also an object to increase the SNR without using a high sampling frequency.

In order to achieve the above object, the present invention creates two ideas.

One is feed-forward technology to improve the saturation problem of integrators.

The other is a dual phase comparison to increase the signal-to-noise ratio without increasing the sampling frequency.

A sigma-delta modulator according to an aspect of the present invention for solving the above problems of the present invention comprises: a first integrator for integrating a first signal; A second integrator to integrate the second signal; A comparator comparing the magnitudes of the integrated second signal and the third signal and outputting the fourth signal; A first gain circuit that multiplies an input signal by a first gain value and outputs the fifth gain value as a fifth signal; And a second gain circuit that multiplies an input signal by a second gain value and outputs the third signal as the third signal. Here, the first signal is a signal obtained by subtracting the fourth signal fed back from the input signal, and the second signal is a signal obtained by subtracting the fourth signal fed back from the sum of the integrated first signal and the fifth signal.

Further, the comparator of the sigma-delta modulator according to another aspect of the present invention includes a first comparator element and a second comparator element driven by a clock having a phase inverted with each other. The first comparator element and the second comparator element are respectively compared with the integrated second signal and the third signal and output as the sixth and seventh signals, respectively.

Further, the first comparator element and the second comparator element may be latched comparators.

Here, the first and second integrators may be implemented as a switched capacitor integrator, or may be implemented as a transconductor.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. (When a part is connected to another part, this includes not only a directly connected part but also an electrically connected part with another element in between.)

Now according to an embodiment of the present invention will be described in detail with reference to the drawings.

2 illustrates a secondary system to which a feed forward technique is applied according to an embodiment of the present invention.

As shown in FIG. 2, an embodiment of the present invention includes a first integrator 100, a second integrator 110, two feed forward paths, and two gain circuits 120 and 130 connected in series. ).

The input signal Vin is added to the output of the primary integrator 100 and the adder 150 via the feedforward gain circuit 120. In addition, the input signal Vin is subtracted from the signal fed back from the comparator 160 and input to the first integrator. In addition, the input signal Vin is input to the comparator through the feed forward gain circuit 130.

 The gain FA of the feed forward gain circuit 120 helps to reduce the swing of the first integrator. The second integrator swing is limited by the gain FB. At the output of the first integrator, the input signal information is mixed with the past information of the integrator and the fed back signal. The absolute value of the output signal is proportional to the input signal. Thus, by supplying an input signal to the second integrator and using an additional feed forward path with gain FA, the input component of the first integrator is greatly reduced. The feed forward signal is amplified by the second integrator. Thus, the second integrator output is affected by the input signal.

 To compensate the input element, a feed forward signal is applied to another pin of the comparator (eg, negative input of the comparator). In general, the negative input pin is biased to a constant voltage. However, in the circuit according to the embodiment of the present invention, a variable signal instead of a constant voltage is applied to the negative input. Thus, the plus pin swing of the comparator is relatively reduced. As a result, the maximum value of the output swing of the second integrator becomes almost independent of the input signal.

Figure 3 shows the output of the integrator before and after applying the embodiment of the present invention. Here, output A shows the output of the second integrator in the conventional modulator, and output B shows the output of the second integrator in the embodiment of the present invention. The output C shows the output of the first integrator in the conventional modulator, and the output D shows the output of the first integrator in the embodiment of the present invention. As can be easily seen in Figure 3 according to an embodiment of the present invention the output of the first integrator and the second integrator is kept more constant than the prior art.

Figure 4 shows the integrator output of an embodiment of the present invention with an input signal with a peak voltage of 4Vpp at a 5V supply.                     

In FIG. 4, output E is the output of the second integrator and output F is the output of the first integrator. Considering the maximum +/- 5V signal swing range, it can be seen that the swings of the first and second integrators do not exceed 2Vpp and 5Vpp, respectively.

5 illustrates a comparator according to an embodiment of the present invention.

Comparator A 210 and Comparator B 220 are latched comparators. The comparator operates as a comparator during the high level of the clock CLK, and otherwise as a latch.

In-phase and out-of-phase clocks composed of inverters are applied to comparators A and B, respectively. The voltage difference between the output VOL of comparator A and the output VOL of comparator B becomes the final output Vo of comparator.

6 is a signal diagram illustrating the operation of a comparator according to an embodiment of the present invention.

As shown in FIG. 6, the output (VOA) transition of comparator A 210 occurs on the falling edge of the clock. On the other hand, the output (VOB) transition of comparator B 220 occurs on the rising edge of the clock. Here, the comparator A is in the comparison mode and the comparator B is in the latch mode during the period T1. During the period T2, the comparator A is in the latch mode and the comparator B is in the comparison mode. Thus, during one clock period (T1 + T2), the outputs undergo two transitions.

Hereinafter, Table 1 shows the state of the output Vo during one cycle T1 + T2.

VOA VOB VO 0 0 0 0 VDD -VDD VDD 0 VDD VDD VDD 0

As shown in Table 1, the output Vo has three signal levels. The comparator according to an embodiment of the present invention improves the signal-to-noise ratio and the dynamic range of the input.

7 is a block diagram illustrating a design of a sigma-delta modulator according to an embodiment of the present invention.

A sigma-delta modulator according to an embodiment of the present invention includes differential integrators 101 and 102 and a feed forward gain circuit. In addition, the dual phase comparators 230 and 240 shown in FIG. 6 are included.

The above-described gains FA and FB may be selected to be 1 and 0.5, respectively. First and second integrators 101 and 102, which are differential integrators, are used to implement embodiments of the present invention.

The first integrator 101 has two inputs. One is for signal input and the other is for feedback input. These signals are differentially integrated.

The second integrator has a third differential input because it requires an additional feed-forward input. The entire feedback loop, which encompasses the local feedback loop via the first and second integrators, must be a negative feedback loop to satisfy stable operation.

On the other hand, it is preferable to use a switched capacitor integrator in the integrator because the sigma-delta modulator handles the sampled data at the output. In addition, the single gain frequency of the switched capacitor integrator is adaptively controlled by the switching frequency. Thus, even when the input bandwidth changes, it is possible for the modulator to exhibit the same signal-to-noise ratio only by changing the sampling frequency.

However, analog low pass filters are required to prevent aliasing in the frequency domain. Op amps used in switched capacitor integrators, on the other hand, require high bandwidth, high slew rate and high gain. Thus, continuous time integrators can be effective on some devices with fixed bandwidths.

8 and 9 illustrate digital amplifiers implemented using operational amplifiers and transconductors, respectively.

In FIG. 8, the first integrator and the second integrator are implemented in the form of an operational amplifier.

Resistors R11 and R12 are used to form the overall negative feedback. Resistors R3, R4, R5, and R6 are for feed forward operation. Since each resistance value is 0.5R, the feed forward gains FA and FB are 1 and 0.5, respectively. The outputs of the comparators are used by the gate drivers 300 and 310 to drive the output transistors.

The feedback signal is sensed at the output of the power transistor, not at the output of the comparator, as shown in FIG. Therefore, the distortion caused by the output PMOS is compensated by the negative feedback loop. Smoothing filters L1, L2, C5 and C6 help to reconstruct the smooth audible signal at the speaker.

In order to use op amps in the circuit, negative feedback using capacitors, resistors, and the like is generally required. Thus, the use of operational amplifiers with high gain as well as high bandwidth is desirable.

However, it is very difficult to meet both of these requirements. Therefore, considering the design efficiency, it is preferable to select a gm-C type integrator consisting of a transconductor and a capacitor as shown in FIG. Since the gm-C integrator is implemented without a negative feedback method, it satisfies the requirements of simplicity and low power consumption. The first integrator utilizes two integral input transconductors GM1 and GM2. Here, transconductance is GM. Thus, the output current is proportional to GM. As a result, in FIG. 7, the transconductor operates like a resistor. The second transconductor GM2 has three integral inputs to obtain a feed forward input. The third transconductor GM3 is used with a resistor R1 to make a gain FB. In this case, the resistance value R1 is half of 1 / GM. Therefore, the gain FB is set to 0.5. Thus, the same gain circuit implementation as that shown in FIG. 8 is possible.

FIG. 10A shows a simulation result with a 4 ohm load with a 5V power supply in the circuit shown in FIG. 9.

10B shows the output of a conventional secondary system.

Comparing the reconstructed waveform using the L-C filter in Figures 10a and 10b, it can be seen that according to the embodiment of the present invention has a larger dynamic range than the prior art.

11 is a graph comparing the signal-to-noise ratio of the embodiment of the present invention and the prior art.

Here, the signal-to-noise ratio SNR1 shows the signal-to-noise ratio of the prior art, and the signal-to-noise ratio SNR2 shows the signal-to-noise ratio in the embodiment of the present invention.

As can be seen in Figure 11, in the embodiment of the present invention it is possible to increase the signal to noise ratio by about 10dB compared to the prior art.

Thus, in the embodiment of the present invention, the dynamic range is about 12 dB wider than the prior art. The clock frequency is 2MHz and the signal bandwidth is 20khz. In this case, the total sampling rate is 50. Therefore, in the embodiment of the present invention, a high signal-to-noise ratio can be obtained despite the relaxed sampling rate.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

By the configuration of the present invention described above, it is possible to implement a sigma-delta modulator with improved dynamic range than the prior art, it is possible to increase the signal-to-noise ratio with a relaxed sampling frequency.

Claims (7)

In a sigma-delta modulator: A first integrator for integrating the first signal; A second integrator to integrate the second signal; A comparator comparing the magnitudes of the integrated second signal and the third signal and outputting the fourth signal; A first gain circuit that multiplies an input signal by a first gain value and outputs the fifth gain value as a fifth signal; And A second gain circuit that multiplies an input signal by a second gain value and outputs the second gain as the third signal, The first signal is a signal obtained by subtracting the fourth signal fed back from the input signal, And the second signal is a signal obtained by subtracting the fourth signal fed back from the sum of the integrated first signal and the fifth signal. The method of claim 1, The comparator comprises a first comparator element and a second comparator element driven by a clock having a phase inverted with each other, And the first comparator element and the second comparator element compare the integrated second signal and the third signal, respectively, and output as sixth and seventh signals, respectively. The method of claim 2, And the first comparator element and the second comparator element are latched comparators. 3. The sigma-delta modulator of claim 2 wherein the first gain value is 1 and the second gain value is 0.5. 4. The sigma-delta modulator of claim 3 wherein the first and second integrators are integrators comprising a fully differential operational amplifier and first and second capacitors. The method of claim 3, wherein The first integrator includes a first transconductor and a second transconductor having the same first conductance, and a second capacitor and a third capacitor connected in parallel to the outputs of the first transconductor and the second transconductor, respectively. and, The second integrator comprises a third transconductor having the first conductance, And a first resistor connected in parallel to the output terminal of the third transconductor is one-half the reciprocal of the first conductance. In the sigma-delta modulation method: Inputting a differential input signal; Integrating the first differential signal; Integrating a second differential signal; Adding a fifth differential signal generated by multiplying a differential input signal by a first gain value to the integrated first differential signal; Comparing a third differential signal generated by multiplying a differential input signal by a second gain value, respectively, with the integrated second differential signal; Driving the first and second latch type comparators in phases inverted from each other such that a difference between the sixth signal and the seventh signal, which are output signals, has three state values;  Feeding back the output signal to generate a first differential signal that is differential from an input signal and to generate a second differential signal that is differential from the sum of the third differential signal and the integrated first differential signal; Modulation method.

Images