KR100945576B1 - Thin film transistor array panel for a liquid crystal display and manufacturing method thereof - Google Patents

Abstract

Forming a gate double layer including a gate line, a gate electrode, and a gate end on the substrate as a gate double layer, forming a gate insulating film on the gate wiring, and successively depositing a semiconductor layer, a contact layer, and a data double layer on the gate insulating film Photo-etching the data double layer and the contact layer to form a data line and a contact layer pattern including a data line, a source electrode, a drain electrode, and a data end; depositing a passivation layer on the data line; Forming a pattern, wherein the gate bilayer forming the gate end is referred to as a first gate end and a second gate end, and the data bilayer forming the data end is referred to as a first data end and a second data end. Insulating protective film, semiconductor layer and gate through etching process using a mask And forming a first contact opening patterning the first gate end to expose the second gate end, and forming a passivation layer over the second data end and patterning over the first data end to reveal the second contact opening. And simultaneously patterning the passivation layer on the portion of the second drain electrode and the portion of the first drain electrode to form a third contact hole exposing a portion of the second drain electrode, and widening the second and third contact holes to form a stepped step well. Forming a pixel electrode electrically connected to the drain electrode.

Thin Film Transistor Boards, Step Well, Cr / Al Data Wiring

Description

Thin film transistor array panel for liquid crystal display device and manufacturing method thereof

1 is a diagram illustrating regions of a substrate for manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a layout view schematically illustrating devices and wirings formed on a thin film transistor substrate for one liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and is an enlarged view of one pixel and pads in FIG. 2.

4 and 5 are cross-sectional views of the thin film transistor substrate shown in FIG. 3 taken along lines IV-IV 'and V-V'.

6 is a cross-sectional view of a thin film transistor substrate in a first stage of manufacture in accordance with an embodiment of the invention,

FIG. 7A is a layout view of a thin film transistor substrate in a next step of FIG. 6;

7B and 7C are cross-sectional views taken along the lines 'b-'b' and 'c-'c' in FIG. 7A, respectively.

8A and 8B are cross-sectional views of the thin film transistor substrate in the next steps of FIGS. 7A-7C,

9A is a layout view of a thin film transistor substrate in the next steps of FIGS. 8A and 8B;

9B and 9C are cross-sectional views taken along the lines 'b-'b' and 'c-'c' in FIG. 9A, respectively.

10A and 10B are cross-sectional views of the thin film transistor substrate in the following steps of FIGS. 9A to 9C;

11A is a layout view of a third mask,

FIG. 11B is a cross-sectional view of the third mask and a cross-sectional view taken along lines XIb-XIb 'and XIc-XI' of the thin film transistor substrate in FIG. 11A, illustrating a photosensitive film applied thereto;

12A is a layout view of a thin film transistor substrate in the next steps of FIGS. 10A and 10B;

12B and 12C are cross-sectional views taken along lines XIIb-XIIb 'and XIIc-XIIc' of FIG. 12A, respectively;

13A and 13B are cross-sectional views of the thin film transistor substrate in the following steps of FIGS. 12A-12C,

14A and 14B are cross-sectional views taken along the lines IIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively, and are cross-sectional views at the next steps of FIGS. 13A and 13B.

15A and 15B are cross-sectional views taken along line XIIb-XIIb 'and XIIC-XIIc' in FIG. 12A, respectively, and are cross-sectional views at the next steps of FIGS. 14A and 14B.                 

16A and 16B are cross-sectional views taken along lines XIIb-XIIb 'and XIIc-XIIc' in FIG. 12A, respectively, and are cross-sectional views at the next steps of FIGS. 15A and 15B.

<Description of the symbols for the main parts of the drawings>

121; Gate line 123; Gate electrode

125; Gate pad 140; Gate insulating film

150; Semiconductor layer 163; Source contact layer pattern

165; Drain contact layer pattern 173; Source electrode

175; Drain electrode 175; Data pad

181; First contact 182; Second contact hole

183; Third contact 190; Pixel electrode

The present invention relates to a method of etching a thin film and a method of manufacturing a thin film transistor substrate for a liquid crystal display device using the same.

In general, a liquid crystal display device is composed of two substrates, and two or more kinds of electrodes for generating an electric field are formed on one or both of the substrates to display an image by adjusting a voltage applied to the electrodes.

Among the two substrates, the thin film transistor substrate for a liquid crystal display device has a thin film transistor formed on the substrate and a pixel electrode controlled by the substrate.

The thin film transistor substrate is manufactured through film formation and photolithography processes of thin films over several layers, and photolithography recovery is representative of the number of manufacturing processes. Therefore, how much stable the device is formed through the small number of photolithography processes is an important factor in determining the manufacturing cost.

 In addition, in the conventional general photolithography process, the photoresist film is divided into two parts, that is, a part irradiated to light and a part that is not exposed, and then developed, so that the photoresist film is not present at all or has a constant thickness, and thus the etching depth is constant. However, by exposing a positive photoresist film by using a mask having a grid with only a specific part, a technique has been developed to reduce the amount of light irradiated to the grid part and form a photoresist pattern having a part having a thickness smaller than other parts. . When etching in this state, the etching depth of the lower photoresist layer is changed.

However, the etching process using such a mask with a grid also has a limited area that can be processed as a grid mask, so even if it is not possible to process a wide area or even diarrhea, it is difficult to process the grid portion to have a uniform etching depth. have. In addition, ion implantation and thin film etching methods using the thickness difference of the photosensitive film formed by controlling the thickness of the barrier layer of the mask to be different are known, but these also have the same problem.

In addition, in the large liquid crystal display, there is a problem that the resistance of the data wiring is increased.

The present invention has been made to solve the above problems, and an object thereof is to provide a new photolithography method for thin films.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to the present invention includes forming a gate wiring including a gate line, a gate electrode, and a gate end on a substrate as a gate double layer, and forming a gate insulating film over the gate wiring. Forming a semiconductor layer, a contact layer, and a data double layer on the gate insulating layer; photo-etching the data double layer and the contact layer to form a data line including a data line, a source electrode, a drain electrode, and a data end; Forming a contact layer pattern, depositing a passivation layer on the data line, forming a photoresist pattern having a different thickness on the passivation layer, and a gate bilayer forming the gate end is referred to as a first gate end and a second gate end. Data duplication forming the data ends Is a first data end and a second data end, wherein the passivation layer, the semiconductor layer, the gate insulating layer, and the first gate end are patterned through an etching process using the photoresist pattern as a mask to expose the second gate end. Forming a first contact, forming a protective layer over the second data end and a second contact hole overlying the first data end to reveal the second data end, and at the same time the protective film over a portion of the second drain electrode; Patterning a portion of the first drain electrode to form a third contact hole exposing a portion of the second drain electrode; widening the second and third contact holes to form a stepped step well; It is preferable to include the step of forming a pixel electrode connected to.

In addition, forming a photoresist pattern having a different thickness may include applying a photoresist layer on the passivation layer, a screen display mask for patterning a photoresist layer corresponding to a gate line, a gate electrode, a data line, a source electrode, and a drain electrode; And exposing and developing the photoresist using a peripheral mask for patterning the photoresist having a different transmittance from the display mask and corresponding to the gate end and the data end.

The forming of the step well may include forming a protective pattern and a semiconductor pattern by patterning the photosensitive layer and the protective layer at the gate end and a semiconductor layer below the same, and simultaneously removing the photosensitive layer and the protective layer at the side surfaces of the second and third contact holes. It is preferable to widen the second and third contact holes to form a step well in the form of steps.

The forming of the step well may include etching the passivation layer, the second data end portion, and a part of the second drain electrode by using the photoresist pattern as a mask, so as to widen the photoresist pattern in the second and third contact holes. Etching back, it is preferable to include the step of etching the protective film in the second, the third contact hole to match the photosensitive film pattern in the widened second, third contact.

In the pixel electrode forming step, it is preferable to simultaneously form an auxiliary gate end and an auxiliary data end respectively connected to the gate end and the data end through the first and second contact holes.                     

The gate double layer may be formed of Cr / Al, and the data double layer may be formed of Cr / Al.

In order to achieve the above object, a thin film transistor substrate for a liquid crystal display of the present invention includes a substrate, first and second gate lines, first and second gate electrodes, and first and second gate ends formed on the substrate. A gate wiring, a gate insulating film formed on the gate wiring, a semiconductor layer formed on the gate insulating film, a contact layer, first and second data lines, first and second source and drain electrodes, and first and second A data wiring including a second data end, a protective film formed on the data wiring, a first contact hole formed to expose the first gate end, a second contact hole formed to expose the first data end, A third contact hole formed to expose a portion of the first drain electrode, a step well in a step shape formed in the second and third contact holes, and It is preferable to include the pixel electrode formed so that the former drain electrode may be covered.

It also preferably includes an auxiliary gate end and an auxiliary data end filling the first and second contact holes so as to be connected to the gate end and the data end, respectively.

Further, the first gate line, the first gate electrode, the first gate end, and the first data line, the first source electrode, the first drain electrode, and the first data end are formed of a Cr layer, and the second gate The line, the second gate electrode, the second gate end, and the second data line, the second source electrode, the second drain electrode, and the second data end are preferably made of an Al layer.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

First, the structure of a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5.

As shown in FIG. 1, several panel regions for a liquid crystal display are simultaneously formed on one insulating substrate. For example, as shown in FIG. 1, four liquid crystal display panel regions 50a, 50b, 50c, and 50d are formed in one glass substrate 10, and the panel region is a thin film transistor panel. The 50a, 50b, 50c, and 50d include screen display portions 41, 51, 61, and 71 and peripheral portions 42, 52, 62, and 72 made up of a plurality of pixels. In the screen displays 41, 51, 61, and 71, thin film transistors, wirings, and pixel electrodes are repeatedly arranged in a matrix form, and peripheral parts 42, 52, 62, and 72 are elements connected to driving elements. That is, pads and other static electricity protection circuits are disposed.

However, when forming such a liquid crystal display device, a stepper exposure device is generally used, and when the exposure device is used, the screen display parts 41, 51, 61, and 71 and the peripheral parts 42, 52, 62, and 72 are divided into various zones. The photosensitive film coated on the thin film is exposed using the same mask or another photomask for each zone, and after exposure, the entire substrate is developed to form a photosensitive film pattern, and then a specific thin film pattern is formed by etching the lower thin film. By repeatedly forming such a thin film pattern, a thin film transistor substrate for a liquid crystal display device is completed.

FIG. 2 is a layout view schematically illustrating an arrangement of a thin film transistor substrate for a liquid crystal display device formed in one panel region in FIG. 1.

As shown in FIG. 2, the screen display unit 41 surrounded by the line 4 includes a plurality of thin film transistors 5, a pixel electrode 190 and a gate line 121 electrically connected to each thin film transistor 5. Wiring and the like including the data line 171 are formed. A gate end 125 connected to the end of the gate line 121 and a data end 179 connected to the end of the data line 171 are disposed at the periphery 42 outside the screen display. The gate end 125 is generally referred to as a gate pad ( 125 and data end 179 is generally referred to as data pad 179. In order to prevent device destruction due to electrostatic discharge, the gate line shorting bar 6 and the data line shorting band (6) are electrically connected to the gate line 121 and the data line 171 to make an equipotential. 7) is arranged, and the gate line short circuit 6 and the data line short circuit 7 are electrically connected through the short circuit connection part 8. These short-circuit bands 6 and 7 are later removed, and the line cutting the substrate when removing them is indicated by the reference numeral H.

A contact hole 9 is drilled through the insulating film in order to connect the shorting line connecting portion 8 between the gate line shorting band 6 and the data line shorting band 7 and an insulating film (not shown).

3 to 5 are enlarged views of thin film transistors, pixel electrodes, wirings, and peripheral pads of the screen display unit of FIG. 3, FIG. 3 is a layout view, and FIGS. 4 and 5 are lines IV-IV ′ of FIG. 3. A cross-sectional view taken along the line VV '.

First, gate wirings 121, 123, and 125 are formed on the insulating substrate 110. The gate wires 121, 123, and 125 are connected to the scan signal lines or the gate lines 121 and the ends of the gate lines 121 extending in the horizontal direction, and receive the scan signals from the outside and transfer them to the gate lines 121. The gate pad 125 and the gate electrode 123 of the thin film transistor that is part of the gate line 121 are included.

The gate wirings 121, 123, and 125 are made of a gate double layer of the first gate wirings 211, 231, and 251 and the second gate wirings 212, 232, and 252. That is, the gate wirings 121, 123, 125 are made of a double layer of Cr / Al or Cr / Al-Nd alloy. That is, the gate wirings 121, 123, and 125 are double layers formed of Cr gate wirings 211, 231, and 251 and Al gate wirings 212, 232, and 252. Cr gate wirings 211, 231, and 251 are formed on the insulating substrate 110, and Al gate wirings 212, 232, and 252 are formed on the Cr gate wirings 211, 231, and 251. Therefore, the gate electrode 123 is a double layer of the Cr gate electrode 231 which is the first gate electrode and the Al gate electrode 232 which is the second gate electrode, and the gate line 121 is the Cr gate line 211 which is the first gate line. ) And the Al gate line 212 serving as the second gate line. The gate pad 125 is also formed of a double layer of a Cr gate pad 251 that is a first gate pad and an Al gate pad 252 that is a second gate pad. However, the gate pad 125 is formed such that a portion of the Al gate pad 252 is removed to form a step well shape so that a portion of the Cr gate pad 251 is exposed.                     

The gate wirings 121, 123, and 125 may be formed of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo), or molybdenum-tungsten (MoW) alloy, chromium (Cr), and tantalum (Ta). It may be formed of a single layer made, but may be formed of a double layer or a triple layer as in the present invention. In the case of forming a double layer, it is preferable that one layer is made of a material having good contact properties with another material, and the other layer is formed of a material having low resistance, so that the Cr layer 211, 231 and 251 are used, and Al layers 211, 232 and 252 are used as materials having low resistance.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate lines 121, 123, and 125 to cover the gate lines 121, 123, and 125.

A semiconductor pattern 150 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating layer 140, and is heavily doped with n-type impurities such as phosphorous (P) on the semiconductor pattern 150. Ohmic contact layer patterns 161, 163, 165, and 169 made of amorphous silicon are formed.

Data lines 171, 173, 175, and 179 are formed on the contact layer patterns 161, 163, 165, and 169. The data line extends in the horizontal direction from the data line 171 formed in the vertical direction, the data pad 179 connected to one end of the data line 171 to receive an image signal from the outside, and the data line 171. Two extension lines, the source electrode 173.

Since the source electrode 173, which is two extension lines extending in the horizontal direction from the data line 171, is formed spaced apart from each other by a predetermined interval, the two extension lines and the data line 171 formed in the vertical direction have a c-shape. In addition, the data line is separated from the data line 171, the data pad 179, and the source electrode 173, a part of which is disposed on the gate electrode 123, and is located in the c-shaped groove of the source electrode 173. A drain electrode 175.

The data wires 171, 173, 175, and 179 are composed of data double layers of the first data wires 711, 731, 751, and 791 and the second data wires 712, 732, 752, and 792. That is, the data lines 171, 173, 175, and 179 are formed of a double layer made of a conductive material of Cr / Al or Cr / Al-Nd alloy. The source electrode 173 is a double layer formed of the first source electrode 731 and the second source electrode 732. That is, the source electrode 173 is a double layer formed of the Cr source electrode 731 and the Al source electrode 732. The Cr source electrode 731 is formed on the contact layer 163, and the Al source electrode 732 is formed on the Cr source electrode 731. Similarly, the drain electrode 175 is a double layer formed of the first drain electrode 751 and the second drain electrode 752. That is, the drain electrode 175 is a double layer formed of the Cr drain electrode 751 and the Al drain electrode 752. A Cr drain electrode 751 is formed on the contact layer 163, and an Al drain electrode 752 is formed on the Cr drain electrode 751. The data line 171 is a double layer formed of a Cr data line 711 as a first data line and an Al data line 712 as a second data line. The data pad 179 is also a double layer formed of a Cr data pad 791 as a first data pad and an Al data pad 792 as a second data pad. However, the data pad 179 is formed such that a portion of the Al data pad 792 is removed to form a step well shape so that a portion of the Cr data pad 791 is exposed.

In addition, data wiring made of a conductive material such as Mo, MoW alloy, or Ta is also possible. As in the present invention, when forming a double layer, it is preferable that one layer is made of a material having good contact properties with other materials, and the other layer is formed of a material having low resistance, and thus has good contact properties with other materials. Cr layers 711, 731, 751, and 791 are used, and Al layers 712, 732, 752, and 792 are used as materials having low resistance. When a double layer of Cr / Al is used as the data wiring, the resistance of the data wiring is lowered, which is useful for large liquid crystal displays.

The contact layer patterns 163 and 165 lower the contact resistance between the semiconductor pattern 150 at the bottom thereof and the data lines 171, 173, 175 and 179 at the top thereof, and the data lines 171, 173 and 175. , 179). That is, the data line portion, the source portion, and the data pad portion contact layer patterns 161, 163, and 169 are the same as the data line, the source electrode, and the data pads 171, 173, and 179, and the drain portion contact layer pattern 165 is formed as follows. It is the same as the drain electrode 175.

The semiconductor pattern 150 has a shape similar to that of the data lines 171, 173, 175, and 179 and the contact layer patterns 161, 163, 165, and 169. Specifically, the source electrode 173 and the drain electrode 175 are separated from the channel portion 154 of the thin film transistor, and the source contact layer pattern 163 and the drain contact layer pattern 165 are also separated. The semiconductor pattern 150 for the thin film transistor is connected here without disconnection to create a channel of the thin film transistor. On the other hand, the semiconductor pattern 150 is also extended to the peripheral portion is formed over the entire peripheral portion.

The data line, the source electrode, the data pad part and the drain electrode 171, 173, 179, and 175 and the semiconductor pattern 150 are covered with the passivation layer 180, and the passivation layer 180 is formed of the data pad 179 and the drain electrode ( It has a second contact hole 182 and a third contact hole 183 exposing a portion of 175. The second contact hole and the third contact hole 182 and 183 are formed in a step well shape. That is, the Al layer on the Cr layers 251, 791, 751 in the second contact hole and the third contact hole is removed, and the protective layer 180 on the Al layer is removed in a wider width than the removed Al layer. . Thus, part of the Al layer is exposed at the edges of the contacts, and the Cr layer is exposed inside the edges of the contacts. That is, the second contact holes and the third contact holes 182 and 183 are formed in a step shape.

Therefore, by forming the second and third contact holes in the form of a step well, disconnection due to a severe step can be prevented, and contact characteristics are improved by allowing a large area to be contacted.

The passivation layer 180 may be made of an organic insulating material such as silicon nitride (SiN) or acrylic, and may cover the channel portion 154 disposed between at least the source electrode 173 and the drain electrode 175 of the semiconductor pattern 150. It protects you.

The pixel electrode 190 is formed on the gate insulating layer 140 in the region surrounded by the gate line 121 and the data line 171. The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the third contact hole 183, receives an image signal from the thin film transistor, and generates an electric field together with the reference electrode of the upper plate. oxide) is made of a transparent conductive material. Meanwhile, an auxiliary gate pad 95 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 through the first contact hole and the second contact hole 181 and 182, respectively, are formed on the gate pad 125 and the data pad 179. They are not essential to supplement the adhesion between the pads 125 and 179 and the external circuit device and to protect the pads, and their application is optional.

Although transparent ITO is used as an example of the material of the pixel electrode 190, an opaque conductive material may be used in the reflective liquid crystal display.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6 to 20B and 3 to 5.

First, as shown in FIG. 6, the Cr layer 201 is deposited on the insulating substrate 110 by sputtering or the like. Then, the Al layer 202 is deposited on the Cr layer 201 with a thickness of 1,000 kPa to 3,000 kPa by the method of sputtering or the like. That is, a gate double layer of Cr and Al is formed.

Next, as shown in FIGS. 7A to 7C, a double layer of Cr and Al is dry or wet etched using a first mask to form a gate line 121, a gate pad 125, and a gate electrode on the insulating substrate 110. A gate wiring including 123 is formed. In this case, as shown in FIGS. 7B and 7C, the gate electrode 123 is formed of a double layer of the Cr gate electrode 231 and the Al gate electrode 232, and the gate pad 125 is formed of the Cr gate pad 251. A double layer of the Al gate pad 252 is formed.

Next, as shown in FIGS. 8A to 8B, the gate insulating layer 140, the semiconductor layer 150, and the contact layer 160 are respectively 1,500 mV to 5,000 mV, 500 mV to 1,500 mV, using chemical vapor deposition. Continuous deposition is performed at a thickness of 300 mW to 600 mW, followed by formation of data bilayers 701 and 702. The data double layer is defined as a first conductor layer 701 and a second conductor layer 702 from below. The Cr conductor layer 701 is deposited by sputtering or the like as the first conductor layer. As the second conductor layer, an Al conductor layer 702 is deposited on the Cr conductor layer 701 at a thickness of 1,000 mV to 3,000 mV by sputtering or the like.

Next, as shown in FIGS. 9A to 9C, the Cr and Al conductor layers 701 and 702 shown in FIGS. 8A and 8B and the contact layer 160 below are patterned by using a second mask. The line 171, the data pad 179, the source electrode 173, and the drain electrode 175 and the data line contact layer pattern under the data line, the data pad contact layer pattern, the source contact layer pattern, and the drain contact layer pattern (161, 169, 163, 165) are formed. The data line 171, the data pad 179, the source electrode 173, and the drain electrode 175 are called data lines 170. In this case, as shown in FIG. 9B, the data line 171 is formed of a double layer of the Cr data line 711 and the Al data line 712, and the data pad 179 is formed of the Cr data pad 791 and Al. The double layer of the data pad 792 is formed. The source electrode 173 and the drain electrode 175 are also formed of a double layer of the Cr source electrode 731, the Al source electrode 732, the Cr drain electrode 751, and the Al drain electrode 752, respectively.                     

Next, as shown in FIGS. 10A to 10B, silicon nitride (SiN) is deposited by a CVD method or spin-coated an organic insulating material to form a protective film 180 having a thickness of 3,000 Å or more.

Next, as shown in FIGS. 15A to 15C, the passivation layer 180, the data line 170, the semiconductor layer 150, and the gate insulating layer 140 are patterned using a third mask to form the first, second, and third layers. 3 pattern including these contact holes 181, 182, and 183 is formed.

In this case, in the peripheral portion P, the passivation layer 180, the semiconductor layer 150, the gate insulating layer 140, and the Al gate pad 252 on the gate pad 125 are removed, and the passivation layer on the data pad 179 is removed. 180 and Al data pad 792 are also removed. However, in the screen display unit D, only the passivation layer 180 and the semiconductor layer 150 should be removed to form a semiconductor layer pattern such that a channel is formed only in a required portion. However, the passivation layer 180 and the Al conductor layer 752 on a part of the drain electrode 175 are also removed to form the third contact hole 183.

To this end, photoresist patterns having different thicknesses are formed according to portions, and lower layers are etched using the etching mask, which will be described in detail with reference to FIGS. 11A to 14B.

First, as shown in FIG. 11B, a photoresist film 5000, preferably a positive photoresist film, is applied on the passivation layer 180 to a thickness of 5,000 kPa to 30,000 kPa, and then a third mask (as shown in FIG. 11A). 1000, 2000). The photosensitive film 5000 after exposure is as shown in FIG. 11B. That is, the C3 portion exposed to light in the photoresist film 5000 of the screen display unit D and the C1 and C2 portions exposed to light in the photoresist film 5000 of the peripheral portion P react with light only from a surface to a certain depth. Is decomposed and the polymer remains underneath. However, differently from the photosensitive film 5000 of the screen display unit D, the portion B3 exposed to the light corresponding to the third contact hole 183 and the photosensitive film B1 exposed to the light from the photosensitive film 5000 of the peripheral portion P, All of the B2 portion reacts with light to the state where the polymer is decomposed. Here, the portions B1, B2, B3, C1, C2, and C3 exposed to light in the screen display unit D or the peripheral portion P are portions where the passivation layer 180 is to be removed.

To this end, structures of the screen display part mask 1000 used for the screen display part D and the peripheral part mask 2000 used for the peripheral part P must be formed differently from the conventional masks.

As shown in FIG. 11B, the masks 1000 and 2000 are usually disposed on the mask substrates 1010 and 2010, the opaque pattern layers 1020 and 2020 formed of chromium thereon, and predetermined regions of the mask substrate. The grid layers 1030 and 2030 are formed.

The grating layer is formed of a slit or a lattice-like fine pattern having a size smaller than the resolution of the light source, and has a lower light transmittance than the openings B1, B2, and B3 of the mask substrate.

After exposing the photoresist film in this manner, the photoresist film pattern 5000 is formed as shown in FIGS. 12A to 12C. That is, the photosensitive film is not formed on a part of the gate pad 125, the data pad 179, and the drain electrode 175. In addition, a thick photoresist layer A is formed on a portion of the data pad 179 and the data line, the source electrodes 171 and 173, and the drain electrode 175 in the screen display unit D. A thin photosensitive film C 'is formed in the C1, C2, and C3 regions.

At this time, the thickness of the thin photosensitive film C 'may be about 1/4 to 1/7 level of the initial thickness, that is, about 350 kPa to 10,000 kPa, more preferably 1,000 kPa to 6,000 kPa. For example, the initial thickness of the photosensitive film may be 25,000 kPa to 30,000 kPa, and the transmittance of the C1 to C3 region may be 30% so that the thickness of the thin photosensitive film C 'may be 3,000 kPa to 5,000 kPa. However, since the thickness to be left must be determined according to the etching process conditions, the light transmittance of the grating layer of the mask must be adjusted according to the processing conditions.

Such a thin photosensitive film C 'may be formed through reflow after exposing and developing the photosensitive film in a conventional manner.

13A to 13B, etching of the passivation layer 180, the Al data pad 179 and the Al drain electrode 175 is performed using the photoresist pattern 5000 as a mask. At this time, the gate pad is etched with respect to the passivation layer 180, the semiconductor layer 150, the gate insulating layer 140, and the Al gate pad 252.

Thereafter, as shown in FIGS. 14A and 14B, an etch back process is performed. At this time, the portion A of the photoresist pattern 5000 must remain without being completely removed, and the wall surface of the photoresist patterns of the B2 and B3 portions is etched to widen the second and third contact holes. The C ′ portion of the photoresist pattern 5000 is completely removed.

Next, as shown in FIGS. 15A and 15B, the passivation layer 180 is etched on the wall surface thereof so as to widen the second and third contact holes according to the widened photoresist pattern. Therefore, part of the Al data pad 179 and the Al drain electrode 175 under the passivation layer 180 are partially exposed. Therefore, a stepped contact hole is formed. In addition, only the passivation layer 180 and the semiconductor layer 150 under the C ′ portion of the photoresist pattern 5000 are removed, and the gate insulating layer 140 is not removed.

Therefore, the semiconductor pattern 150 of the screen display unit D and the first contact hole 181 of the peripheral portion P may be formed using only the passivation layer 180 and the semiconductor layer 150 through one mask process and several etching methods. Can be removed and formed.

In addition, the second contact hole 182 of the peripheral portion P and the third contact hole 183 of the screen display portion D may partially cover the passivation layer 180, the Al data pad 179, and the Al drain electrode 175. Can be removed and formed simultaneously.

Finally, as shown in FIGS. 16A and 16B, the photoresist pattern of the remaining portion A is removed, and as shown in FIGS. 3 to 5, an ITO layer having a thickness of 400 kV to 500 kV is deposited and a fourth film is deposited. Etching is performed using a mask to form the pixel electrode 190, the auxiliary gate pad 95, and the auxiliary data pad 97.

As described above, the second contact hole 182 and the third contact hole 183 are formed by using a mask together with the passivation layer pattern 180 and the semiconductor pattern 150. The contact hole 182 and the third contact hole 183 may be formed together when patterning other films in addition, which are within the scope naturally conceivable to those skilled in the art.

In addition, in the present embodiment, a case where the pixel electrode of a wide surface shape is present is illustrated, but the pixel electrode may be formed in a line shape, and the reference electrode for driving the liquid crystal molecules together with the pixel electrode is formed on the same substrate as the pixel electrode. May be formed

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

The method of manufacturing a thin film transistor substrate according to the present invention reduces the number of manufacturing processes of the thin film transistor substrate for a liquid crystal display device through a new photolithography method of a thin film, and simplifies the process to lower the manufacturing cost and increase the yield.

In addition, it is possible to etch a large area to different depths while having a uniform etching depth for one etching depth.

In addition, by forming the data wiring in a double layer of Cr / Al, the resistance of the data wiring can be lowered, and the second and third contact holes can be formed in a step well shape to prevent disconnection due to severe stepping.

Claims (11)

delete delete delete delete delete delete delete delete delete Board, A gate wiring including first and second gate lines, first and second gate electrodes, and first and second gate ends formed on the substrate; A gate insulating film formed on the gate wiring, A data line including a semiconductor layer, a contact layer, first and second data lines, first and second source and drain electrodes, and first and second data ends formed on the gate insulating layer in order; A protective film formed on the data wiring; A first contact hole formed to expose a boundary line of the first gate end, a second contact hole formed to expose the first data end portion, a third contact hole formed to expose the first drain electrode, Step wells formed in the stepped second and third contact holes, A pixel electrode formed to cover the drain electrode Including, The passivation layer includes an opening exposing a gate insulating layer formed on the gate line, and the passivation layer has the same planar pattern as the semiconductor. Board, A gate wiring including first and second gate lines, first and second gate electrodes, and first and second gate ends formed on the substrate; A gate insulating film formed on the gate wiring, A data line including a semiconductor layer, a contact layer, first and second data lines, first and second source and drain electrodes, and first and second data ends formed on the gate insulating layer in order; A protective film formed on the data wiring; A first contact hole formed to expose a boundary line of the first gate end, a second contact hole formed to expose the first data end portion, a third contact hole formed to expose the first drain electrode, Step wells formed in the stepped second and third contact holes, A pixel electrode formed to cover the drain electrode Including, The passivation layer includes an opening exposing a gate insulating layer formed on the gate line, the first contact hole is formed in the gate insulating layer, And the second contact hole and the third contact hole are formed in the passivation layer.

Images