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KR100935773B1 - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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KR100935773B1
KR100935773B1 KR1020070121143A KR20070121143A KR100935773B1 KR 100935773 B1 KR100935773 B1 KR 100935773B1 KR 1020070121143 A KR1020070121143 A KR 1020070121143A KR 20070121143 A KR20070121143 A KR 20070121143A KR 100935773 B1 KR100935773 B1 KR 100935773B1
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poly gate
dummy oxide
gate
forming
drain
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KR20090054338A (en
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조용수
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7847—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 더미 산화막 폴리 게이트를 이용하여 얕은 소오스/드레인 LDD 접합층 구조의 익스텐션을 미리 형성시킨 후, 실리콘 질화막(Si3N4)을 이용한 응력 기억을 적용하여 서멀에 의한 응력 완화를 최소화함으로써, 누설 전류가 증가하게 되는 요인을 개선하고 이로 인하여 고집적 회로에서 파워 증가를 억제할 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device, wherein an extension of a shallow source / drain LDD junction layer structure is formed in advance using a dummy oxide poly gate, and then stress memory using a silicon nitride film (Si 3 N 4 ) is applied. By minimizing the stress relaxation caused by the thermal, it is possible to improve the factor causing the leakage current to increase and thereby suppress the increase in power in the highly integrated circuit.

실리콘 질화막, 더미 산화막 게이트, MOSFET Silicon Nitride, Dummy Gate, MOSFET

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}Method of manufacturing a semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

본 발명은 누설 전류(leakage current; Ioff)의 열화없이 성능을 개선하기 위한 MOSFET 소자의 제조 방법에 관한 것이다. The present invention relates to a method for fabricating a MOSFET device for improving performance without deterioration of leakage current (Ioff).

주지된 바와 같이, MOSFET(Metal Oxide Silicon Field Effect Transistor, 이하, MOSFET라 함)는 게이트(gate) 전극, 소오스/드레인(source/drain) 전극이 절연층(dielectric layer)을 사이에 두고 실리콘 기판에 형성된 구조를 갖는다.As is well known, MOSFETs (Metal Oxide Silicon Field Effect Transistors, hereinafter referred to as MOSFETs) include a gate electrode and a source / drain electrode on a silicon substrate with an insulating layer interposed therebetween. Has a formed structure.

현재 반도체 소자의 소형화, 경량화, 박막화의 추세에 따라 MOSFET의 크기또한 축소(scale down)되고 있는데, 이러한 트랜지스터의 축소는 게이트전극의 유효 채널 길이(channel length)를 감소시켜 소오스와 드레인 사이의 펀치쓰루(punch-through) 특성을 열화시키는 쇼트 채널 효과(short channel effect)를 발생시킨다.As the size of semiconductor devices becomes smaller, lighter, and thinner, MOSFETs are also scaled down, which reduces the effective channel length of the gate electrode, resulting in punch-through between the source and drain. It generates a short channel effect that degrades the punch-through characteristic.

이를 해결하기 위하여 MOSFET의 소오스 및 드레인에 얕은 접합을 이용하는 LDD(Lightly Doped Drain) 구조가 등장하게 되었다. In order to solve this problem, a lightly doped drain (LDD) structure using shallow junctions to source and drain of a MOSFET has been introduced.

도 1은 일반적인 반도체 소자의 MOSFET 구조를 나타낸 단면도로서, 이를 참 조하여 종래의 MOSFET 제조 방법을 설명하면 다음과 같다. 1 is a cross-sectional view showing a MOSFET structure of a general semiconductor device, referring to the conventional MOSFET manufacturing method as follows.

즉, 반도체 기판으로서 실리콘 기판(10)에 소자분리 및 웰 공정을 진행한 후에 기판 전면에 게이트 절연막(12)을 형성한다. 게이트 절연막(12) 위에 도프트 폴리실리콘을 증착하고 이를 패터닝하여 게이트 전극(14)을 형성한다. 그리고 게이트 절연막(12) 및 게이트 전극(14) 전면에 버퍼 절연막(buffer dielectric layer)(16)으로서 실리콘 산화막(SiO2)을 얇게 형성한다. 그 다음 LDD 임플란트 공정을 진행하여 게이트 전극(14) 양쪽 기판내에 저농도의 불순물(n-/p-)이 주입된 얕은 LDD 접합층(18)을 형성한다. 그리고 게이트 전극(14)의 버퍼 절연막(16) 측벽에 절연물질, 예컨대 실리콘 질화막(Si3N4)으로 스페이서(spacer)(20)를 형성한 후에, 소오스/드레인 임플란트 공정을 진행하여 스페이서(20) 양쪽 기판내 에 고농도의 불순물(n+/p+)이 주입된 소오스/드레인 접합층(22)을 형성한다. 이와 같이 제조된 MOSFET는 기판 표면의 채널 사이에 LDD(18) 구조의 소오스/드레인 접합층(22)을 갖으며 LDD 접합층(18) 상부에 게이트 절연막(12)을 사이에 두고 도전성을 갖는 게이트 전극(14)이 형성되어 있으며 게이트 전극(14)의 측벽에 절연물질로 이루어진 스페이서(20)가 형성되어 있다.That is, after the device isolation and the well process are performed on the silicon substrate 10 as a semiconductor substrate, the gate insulating film 12 is formed on the entire surface of the substrate. Doped polysilicon is deposited on the gate insulating layer 12 and patterned to form the gate electrode 14. A thin silicon oxide film (SiO 2 ) is formed as a buffer dielectric layer 16 over the gate insulating film 12 and the gate electrode 14. The LDD implant process is then performed to form a shallow LDD junction layer 18 into which low concentrations of impurities (n- / p-) are implanted into both substrates of the gate electrode 14. After the spacer 20 is formed on the sidewall of the buffer insulating layer 16 of the gate electrode 14 by using an insulating material, for example, silicon nitride (Si 3 N 4 ), the source / drain implant process is performed to perform the spacer 20. The source / drain junction layer 22 into which high concentrations of impurities (n + / p +) are implanted is formed in both substrates. The MOSFET manufactured as described above has a source / drain junction layer 22 having an LDD 18 structure between channels on a substrate surface, and a conductive gate having a gate insulating layer 12 interposed therebetween on the LDD junction layer 18. The electrode 14 is formed and a spacer 20 made of an insulating material is formed on the sidewall of the gate electrode 14.

그러나, 상기한 바와 같이 동작되는 배경 기술에서 65㎚ 이하의 고집적화가 진행되면서 종래 MOSFET에서 게이트 산화막 두께 감소와 채널 농도의 증가로 캐리어 이동이 감소하게 되어 결국 누설 전류(Ioff)를 증가시키는 요인으로 작용한다. 이는 직접도가 증가하는 제품에서 파워(Power) 증가를 유발하는 직접적인 원인이 되는 문제점이 있다. However, in the background technology operated as described above, as the high integration of 65 nm or less proceeds, carrier movement is reduced due to the decrease in the thickness of the gate oxide film and the increase in the channel concentration in the conventional MOSFET, which eventually increases the leakage current (Ioff). do. This is a problem that is a direct cause of the increase in power (Power) in a product that has increased directness.

이에, 본 발명의 기술적 과제는 상술한 바와 같은 문제점을 해결하기 위해 안출한 것으로, 더미 산화막 폴리 게이트를 이용하여 얕은 소오스/드레인 LDD 접합층 구조의 익스텐션(extension)을 미리 형성시킨 후, 실리콘 질화막(Si3N4)을 이용한 응력 기억(stress memorized)을 적용하여 서멀(thermal)에 의한 응력 완화를 최소화함으로써, 누설 전류(Ioff)가 증가하게 되는 요인을 개선하고 이로 인하여 고집적 회로에서 파워 증가를 억제할 수 있는 반도체 소자의 제조 방법을 제공한다. Accordingly, the technical problem of the present invention is to solve the above-described problems, and after forming the extension of the shallow source / drain LDD junction layer structure using a dummy oxide poly gate, the silicon nitride film ( By applying stress memorized with Si 3 N 4 ) to minimize thermal stress relaxation, it improves the factor of increasing leakage current (Ioff), thereby suppressing the power increase in high density circuit Provided are a method of manufacturing a semiconductor device.

본 발명의 실시예에 따른 반도체 소자의 제조 방법은, 웰 임플란트 공정이 실시된 기판에 더미 산화막 폴리 게이트를 형성하는 단계와, 상기 형성된 더미 산화막 폴리 게이트에 대하여 LDD(Lightly Doped Drain) 임플란트 공정 및 열처리 공정을 진행하여 상기 더미 산화막 폴리 게이트 양쪽 기판내에 익스텐션(extension) 을 형성하는 단계와, 상기 익스텐션이 형성된 더미 산화막 폴리 게이트 상부에 절연물질을 형성하고, 상기 더미 산화막 폴리 게이트를 선택적으로 제거하는 단계와, 상기 제거된 영역에 게이트 산화막 및 폴리 게이트를 순차적으로 형성하며, 상기 절연물질을 선택적으로 제거하는 단계와, 상기 폴리 게이트의 측벽에 스페이서를 형성시킨 다음에, 소오스/드레인 임플란트 공정을 진행하여 상기 스페이서 양쪽 기판내에 소오스/드레인 접합층을 형성하는 단계를 포함한다.A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a dummy oxide poly gate on a substrate on which a well implant process is performed, and performing a lightly doped drain (LDD) implant process and heat treatment on the formed dummy oxide poly gate. Forming an extension in both substrates of the dummy oxide poly gate by forming a process; forming an insulating material on the dummy oxide poly gate in which the extension is formed, and selectively removing the dummy oxide poly gate; And sequentially forming a gate oxide film and a poly gate in the removed region, selectively removing the insulating material, forming a spacer on the sidewall of the poly gate, and then performing a source / drain implant process. Source / drain junction layers in both spacers Forming a step.

상기 절연물질은, 실리콘 질화막(Si3N4)인 것을 특징으로 한다.The insulating material is characterized in that the silicon nitride film (Si 3 N 4 ).

상기 실리콘 질화막은, NMOS의 경우 저압력 화학기상증착 공정을 사용하며, PMOS의 경우 플라즈마 화학 증착 공정을 사용하여 형성하는 것을 특징으로 한다.The silicon nitride film is formed using a low pressure chemical vapor deposition process in the case of NMOS, and plasma chemical vapor deposition in the case of PMOS.

상기 더미 산화막 폴리 게이트는, 100㎚∼180㎚ 범위의 두께로 형성하는 것을 특징으로 한다.The dummy oxide film poly gate is formed to have a thickness in the range of 100 nm to 180 nm.

상기 익스텐션은, 소오스/드레인 LDD 접합층인 것을 특징으로 한다.The extension is characterized in that the source / drain LDD junction layer.

상기 폴리 게이트는, 화학기상증착에 의해 형성되는 것을 특징으로 한다.The poly gate is formed by chemical vapor deposition.

상기 폴리 게이트는, CMP 공정에 의해 평탄화되는 것을 특징으로 한다.The poly gate is flattened by a CMP process.

본 발명은 더미 산화막 폴리 게이트를 이용하여 얕은 소오스/드레인 LDD 접합층 구조의 익스텐션을 미리 형성시킨 후, 실리콘 질화막(Si3N4)을 이용한 응력 기억을 적용하여 서멀에 의한 응력 완화를 최소화함으로써, 누설 전류가 증가하게 되 는 요인을 개선하고 이로 인하여 고집적 회로에서 파워 증가를 억제할 수 있는 효과가 있다.According to the present invention, an extension of a shallow source / drain LDD junction layer structure is formed in advance using a dummy oxide poly gate, and then stress stress using a silicon nitride film (Si 3 N 4 ) is applied to minimize stress relaxation by thermal. This improves the factor that increases leakage current and, therefore, has the effect of suppressing the increase in power in highly integrated circuits.

이하 첨부된 도면을 참조하여 본 발명의 동작 원리를 상세히 설명한다. 하기에서 본 발명을 설명함에 있어서 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, when it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.

도 2a 내지 도 2h는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 각 공정별 수직 단면도이다.2A to 2H are vertical cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

즉, 도 2a에 도시된 바와 같이, 반도체 기판(P-Substrate)(예컨대, 실리콘 기판)(201)에 서멀 산화막(thermal oxide)(203)을 형성한 다음에, 형성된 서멀 산화막(203) 상부 전면에 웰 임플란트 공정(205)을 실시한다. 이때, 서멀 산화막(203)은 5㎚∼15㎚ 범위의 두께로 형성하는 것이 바람직하다.That is, as shown in FIG. 2A, a thermal oxide 203 is formed on a semiconductor substrate P-substrate (for example, a silicon substrate) 201, and then the entire upper surface of the formed thermal oxide 203 is formed. The well implant process 205 is performed. At this time, the thermal oxide film 203 is preferably formed to a thickness of 5nm to 15nm range.

다음으로, 웰 임플란트 공정 후, 형성된 서멀 산화막(203)을 식각 공정(예컨대, 습식방식)을 사용하여 제거한 다음에, 화학기상증착(Chemical Vapor Deposition, 이하, CVD라 함) 공정을 이용하여 산화막을 도포하고, 도포된 산화막 상부에 폴리 게이트 영역을 정의하기 위한 PR 패턴을 형성하며, 형성된 PR 패턴을 마스크로 식각 공정(예컨대, 건식 방식)을 실시하여 도포된 산화막을 선택적으로 제거하여 일 예로, 도 2b에 도시된 바와 같이 더미 산화막 폴리 게이트(207)를 형성한다. 여기서, 더미 산화막 폴리 게이트(207)는 100㎚∼180㎚ 범위의 두께로 형성하는 것이 바람직하다.Next, after the well implant process, the formed thermal oxide film 203 is removed using an etching process (for example, a wet method), and then the oxide film is formed by using a chemical vapor deposition (hereinafter, referred to as CVD) process. And forming a PR pattern to define a poly gate region on the applied oxide film, and selectively removing the applied oxide film by performing an etching process (eg, a dry method) using the formed PR pattern as a mask. As shown in 2b, the dummy oxide poly gate 207 is formed. Here, the dummy oxide poly gate 207 is preferably formed to a thickness in the range of 100 nm to 180 nm.

이후, 형성된 더미 산화막 폴리 게이트(207)에 대하여 LDD 임플란트 공정(209)을 진행한 다음에, 불순물을 활성화 시키기 위해 급속 열처리 프로세싱(Rapid Thermal Processing, 이하, RTP라 함)을 이용하여 일 예로, 도 2c에 도시된 바와 같이 더미 산화막 폴리 게이트(207) 양쪽 기판내에 얕은 소오스/드레인 LDD 접합층 구조의 익스텐션(extension)(211)을 형성한다. Thereafter, the LDD implant process 209 is performed on the formed dummy oxide poly gate 207, and then rapid thermal processing (hereinafter referred to as RTP) is used to activate impurities. As shown in 2c, an extension 211 of a shallow source / drain LDD junction layer structure is formed in both substrates of the dummy oxide poly gate 207.

다음에, 채널(channel)에 응력(stress)을 기억(memorized)하기 위하여 익스텐션(211)이 형성된 더미 산화막 폴리 게이트(207) 상부에 CVD를 이용하여 실리콘 질화막(Si3N4)을 전면 형성한 다음에 CMP(Chemical Mechanical Polishing) 공정을 실시하여 일 예로, 도 2d에 도시된 바와 같이 더미 산화막 폴리 게이트(207)가 노출되는 높이까지 평탄화시킨 실리콘 질화막(Si3N4)(213)을 형성한다. 여기서, CVD 공정을 실시하여 실리콘 질화막(Si3N4)(213)을 형성할 경우, NMOS의 경우 저압력 화학기상증착(Low Pressure Chemical Vapor Deposition, 이하, LPCVD라 함) 공정을 사용하며, PMOS의 경우 플라즈마 화학 증착(Plasma Enhanced Chemical Vapor Deposition, 이하, PECVD라 함) 공정을 선택적으로 사용하고, 실리콘 질화막(Si3N4)(213) 대신에 실리콘 카본(SiC)를 사용할 수 있는 것이 바람직하다.Next, a silicon nitride film (Si 3 N 4 ) is entirely formed on the dummy oxide poly gate 207 having the extension 211 formed thereon by using CVD to memorize stress in the channel. Next, a chemical mechanical polishing (CMP) process is performed to form a silicon nitride film (Si 3 N 4 ) 213 planarized to a height at which the dummy oxide poly gate 207 is exposed, as shown in FIG. 2D. . Here, in the case of performing the CVD process to form a silicon nitride film (Si 3 N 4 ) 213, in the case of NMOS, a low pressure chemical vapor deposition (hereinafter referred to as LPCVD) process is used, PMOS In the case of Plasma Enhanced Chemical Vapor Deposition (hereinafter referred to as PECVD) process is optionally used, it is preferable to use silicon carbon (SiC) in place of the silicon nitride film (Si 3 N 4 ) 213. .

다음으로, 실리콘 질화막(Si3N4)(213)을 형성한 상태에서 식각 공정(예컨대, 습식 방식)을 이용하여 일 예로, 도 2e에 도시된 바와 같이 더미 산화막 폴리 게이트(207)를 선택적으로 제거(215)한다. Next, using an etching process (eg, a wet method) in a state in which a silicon nitride film (Si 3 N 4 ) 213 is formed, the dummy oxide poly gate 207 may be selectively selected as shown in FIG. 2E, for example. Remove 215.

이어서, 더미 산화막 폴리 게이트(207)를 제거한 다음에 세정(cleaning) 공정을 진행하고, 제거(215)된 영역에 게이트 산화막(217)을 성장시킨 후, CVD를 이용하여 폴리 실리콘을 도포한 다음에, 평탄화 공정인 CMP(Chemical Mechanical Polishing)를 실시하여 일 예로, 도 2f에 도시된 바와 같이 폴리 게이트(219)를 형성한다. Subsequently, the dummy oxide poly gate 207 is removed, followed by a cleaning process, the gate oxide film 217 is grown in the removed 215 region, and then polysilicon is applied by CVD. For example, the poly gate 219 is formed by performing CMP (Chemical Mechanical Polishing), which is a planarization process.

다음으로, 폴리 게이트(219)가 형성된 실리콘 질화막(Si3N4)(213)에 대하여 식각 공정(예컨대, 습식 방식)을 실시하여 일 예로, 도 2g에 도시된 바와 같이 실리콘 질화막(Si3N4)(213)을 선택적으로 제거한다. Next, an etching process (eg, a wet method) is performed on the silicon nitride film (Si 3 N 4 ) 213 on which the poly gate 219 is formed. For example, as illustrated in FIG. 2G, the silicon nitride film (Si 3 N) is used. 4 ) 213 is selectively removed.

마지막으로, 실리콘 질화막(Si3N4)(213)을 제거하는 공정에서 발생되는 폴리 에지 게이트 산화막을 회복시키기 위하여 저온(예컨대, 750℃ 이하)에서 측벽 산화막(oxidation) 공정과 TEOS 및 실리콘 질화막(Si3N4)을 이용하여 폴리 게이트(219)의 측벽에 스페이서(221)를 형성시킨 다음에, 소오스/드레인 임플란트 공정(223)을 진행하여 일 예로, 도 2h에 도시된 바와 같이 스페이서(219) 양쪽 기판내에 고농도 의 불순물(n+/p+)이 주입된 소오스/드레인 접합층(225)을 형성한다. 여기서, TEOS는 15㎚∼25㎚ 범위의 두께로 형성하고, 실리콘 질화막(Si3N4)은 50㎚∼80㎚ 범위의 두께로 형성하는 것이 바람직하다.Finally, in order to recover the poly-edge gate oxide film generated in the process of removing the silicon nitride film (Si 3 N 4 ) 213, the sidewall oxidation process and the TEOS and silicon nitride film ( The spacer 221 is formed on the sidewall of the poly gate 219 using Si 3 N 4 , and then the source / drain implant process 223 is performed to, for example, the spacer 219 as shown in FIG. 2H. The source / drain junction layer 225 implanted with a high concentration of impurities (n + / p +) is formed in both substrates. Here, TEOS is formed to a thickness of 15㎚~25㎚ range, silicon nitride (Si 3 N 4) is preferably formed to a thickness of 50㎚~80㎚ range.

이상 설명한 바와 같이, 본 발명은 더미 산화막 폴리 게이트를 이용하여 얕은 소오스/드레인 LDD 접합층 구조의 익스텐션을 미리 형성시킨 후, 실리콘 질화막(Si3N4)을 이용한 응력 기억을 적용하여 서멀에 의한 응력 완화를 최소화함으로써, 누설 전류가 증가하게 되는 요인을 개선하고 이로 인하여 고집적 회로에서 파워 증가를 억제할 수 있다. As described above, in the present invention, an extension of a shallow source / drain LDD junction layer structure is formed in advance using a dummy oxide poly gate, and then a stress caused by thermal is applied by applying a stress memory using a silicon nitride film (Si 3 N 4 ). By minimizing mitigation, it is possible to improve the factor that increases leakage current and thereby suppress power increase in highly integrated circuits.

한편 본 발명의 상세한 설명에서는 구체적인 실시예에 관해 설명하였으나, 본 발명의 범위에서 벗어나지 않는 한도 내에서 여러 가지 변형이 가능함은 물론이다. 그러므로 본 발명의 범위는 설명된 실시예에 국한되지 않으며, 후술되는 특허청구의 범위뿐만 아니라 이 특허청구의 범위와 균등한 것들에 의해 정해져야 한다. Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

도 1은 반도체 소자의 MOSFET 구조를 나타낸 단면도,1 is a cross-sectional view showing a MOSFET structure of a semiconductor device,

도 2a 내지 도 2h는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 각 공정별 수직 단면도.2A to 2H are vertical cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

201 : 반도체 기판 203 : 서멀 산화막201: semiconductor substrate 203: thermal oxide film

205 : 웰 임플란트 공정 207 : 더미 산화막 폴리 게이트205 well implant process 207 dummy oxide poly gate

209 : LDD 임플란트 공정 211 : 익스텐션209: LDD implant process 211: Extension

213 : 실리콘 질화막(Si3N4) 217 : 게이트 산화막213: silicon nitride film (Si 3 N 4 ) 217: gate oxide film

219 : 폴리 게이트 221 : 스페이서219 poly gate 221 spacer

223 : 소오스/드레인 임플란트 공정223 source / drain implant process

225 : 소오스/드레인 접합층225: source / drain bonding layer

Claims (7)

삭제delete 삭제delete 웰 임플란트 공정이 실시된 기판에 더미 산화막 폴리 게이트를 형성하는 단계와, Forming a dummy oxide poly gate on the substrate subjected to the well implant process; 상기 형성된 더미 산화막 폴리 게이트에 대하여 LDD(Lightly Doped Drain) 임플란트 공정 및 열처리 공정을 진행하여 상기 더미 산화막 폴리 게이트 양쪽 기판내에 익스텐션(extension)을 형성하는 단계와,Performing an LDD (Lightly Doped Drain) implant process and a heat treatment process on the formed dummy oxide poly gate to form an extension in both substrates of the dummy oxide poly gate; 상기 익스텐션이 형성된 더미 산화막 폴리 게이트 상부에 실리콘 질화막(Si3N4) 또는 실리콘 카본(SiC)을 형성하고, 상기 더미 산화막 폴리 게이트를 선택적으로 제거하는 단계와, Forming a silicon nitride film (Si 3 N 4 ) or silicon carbon (SiC) on the dummy oxide poly gate on which the extension is formed, and selectively removing the dummy oxide poly gate; 상기 제거된 영역에 게이트 산화막 및 폴리 게이트를 순차적으로 형성하며, 상기 실리콘 질화막 또는 실리콘 카본을 선택적으로 제거하는 단계와, Sequentially forming a gate oxide film and a poly gate in the removed region, and selectively removing the silicon nitride film or silicon carbon; 상기 폴리 게이트의 측벽에 스페이서를 형성시킨 다음에, 소오스/드레인 임플란트 공정을 진행하여 상기 스페이서 양쪽 기판내에 소오스/드레인 접합층을 형성하는 단계Forming a spacer on the sidewalls of the poly gate, and then performing a source / drain implant process to form a source / drain junction layer in both substrates of the spacer; 를 포함하며,Including; 상기 실리콘 질화막 또는 실리콘 카본은, NMOS의 경우 저압력 화학기상증착(low pressure chemical vapor deposition) 공정을 사용하며, PMOS의 경우 플라즈마 화학 증착(plasma enhanced chemical vapor deposition) 공정을 사용하여 형성하는 반도체 소자의 제조 방법.The silicon nitride film or silicon carbon is a low pressure chemical vapor deposition process in the case of NMOS, and a plasma enhanced chemical vapor deposition process in the case of PMOS. Manufacturing method. 웰 임플란트 공정이 실시된 기판에 더미 산화막 폴리 게이트를 형성하는 단계와, Forming a dummy oxide poly gate on the substrate subjected to the well implant process; 상기 형성된 더미 산화막 폴리 게이트에 대하여 LDD(Lightly Doped Drain) 임플란트 공정 및 열처리 공정을 진행하여 상기 더미 산화막 폴리 게이트 양쪽 기판내에 익스텐션(extension)을 형성하는 단계와,Performing an LDD (Lightly Doped Drain) implant process and a heat treatment process on the formed dummy oxide poly gate to form an extension in both substrates of the dummy oxide poly gate; 상기 익스텐션이 형성된 더미 산화막 폴리 게이트 상부에 절연물질을 형성하고, 상기 더미 산화막 폴리 게이트를 선택적으로 제거하는 단계와, Forming an insulating material on the dummy oxide poly gate on which the extension is formed, and selectively removing the dummy oxide poly gate; 상기 제거된 영역에 게이트 산화막 및 폴리 게이트를 순차적으로 형성하며, 상기 절연물질을 선택적으로 제거하는 단계와, Sequentially forming a gate oxide film and a poly gate in the removed region, and selectively removing the insulating material; 상기 폴리 게이트의 측벽에 스페이서를 형성시킨 다음에, 소오스/드레인 임플란트 공정을 진행하여 상기 스페이서 양쪽 기판내에 소오스/드레인 접합층을 형성하는 단계Forming a spacer on the sidewalls of the poly gate, and then performing a source / drain implant process to form a source / drain junction layer in both substrates of the spacer; 를 포함하며, Including; 상기 더미 산화막 폴리 게이트는, 100㎚∼180㎚ 범위의 두께로 형성하는 반도체 소자의 제조 방법.The dummy oxide film poly gate is formed in a thickness of 100 nm to 180 nm. 삭제delete 웰 임플란트 공정이 실시된 기판에 더미 산화막 폴리 게이트를 형성하는 단계와, Forming a dummy oxide poly gate on the substrate subjected to the well implant process; 상기 형성된 더미 산화막 폴리 게이트에 대하여 LDD(Lightly Doped Drain) 임플란트 공정 및 열처리 공정을 진행하여 상기 더미 산화막 폴리 게이트 양쪽 기판내에 익스텐션(extension)을 형성하는 단계와,Performing an LDD (Lightly Doped Drain) implant process and a heat treatment process on the formed dummy oxide poly gate to form an extension in both substrates of the dummy oxide poly gate; 상기 익스텐션이 형성된 더미 산화막 폴리 게이트 상부에 절연물질을 형성하고, 상기 더미 산화막 폴리 게이트를 선택적으로 제거하는 단계와, Forming an insulating material on the dummy oxide poly gate on which the extension is formed, and selectively removing the dummy oxide poly gate; 상기 제거된 영역에 게이트 산화막 및 폴리 게이트를 순차적으로 형성하며, 상기 절연물질을 선택적으로 제거하는 단계와, Sequentially forming a gate oxide film and a poly gate in the removed region, and selectively removing the insulating material; 상기 폴리 게이트의 측벽에 스페이서를 형성시킨 다음에, 소오스/드레인 임플란트 공정을 진행하여 상기 스페이서 양쪽 기판내에 소오스/드레인 접합층을 형성하는 단계Forming a spacer on the sidewalls of the poly gate, and then performing a source / drain implant process to form a source / drain junction layer in both substrates of the spacer; 를 포함하며,Including; 상기 폴리 게이트는, 화학기상증착(chemical vapor deposition)에 의해 형성되는 반도체 소자의 제조 방법.The poly gate is a method of manufacturing a semiconductor device is formed by chemical vapor deposition (chemical vapor deposition). 웰 임플란트 공정이 실시된 기판에 더미 산화막 폴리 게이트를 형성하는 단계와, Forming a dummy oxide poly gate on the substrate subjected to the well implant process; 상기 형성된 더미 산화막 폴리 게이트에 대하여 LDD(Lightly Doped Drain) 임플란트 공정 및 열처리 공정을 진행하여 상기 더미 산화막 폴리 게이트 양쪽 기판내에 익스텐션(extension)을 형성하는 단계와,Performing an LDD (Lightly Doped Drain) implant process and a heat treatment process on the formed dummy oxide poly gate to form an extension in both substrates of the dummy oxide poly gate; 상기 익스텐션이 형성된 더미 산화막 폴리 게이트 상부에 절연물질을 형성하고, 상기 더미 산화막 폴리 게이트를 선택적으로 제거하는 단계와, Forming an insulating material on the dummy oxide poly gate on which the extension is formed, and selectively removing the dummy oxide poly gate; 상기 제거된 영역에 게이트 산화막 및 폴리 게이트를 순차적으로 형성하며, 상기 절연물질을 선택적으로 제거하는 단계와, Sequentially forming a gate oxide film and a poly gate in the removed region, and selectively removing the insulating material; 상기 폴리 게이트의 측벽에 스페이서를 형성시킨 다음에, 소오스/드레인 임플란트 공정을 진행하여 상기 스페이서 양쪽 기판내에 소오스/드레인 접합층을 형성하는 단계Forming a spacer on the sidewalls of the poly gate, and then performing a source / drain implant process to form a source / drain junction layer in both substrates of the spacer; 를 포함하며,Including; 상기 폴리 게이트는, CMP(chemical mechanical polishing) 공정에 의해 평탄화되는 반도체 소자의 제조 방법.The poly gate is a method of manufacturing a semiconductor device is planarized by a chemical mechanical polishing (CMP) process.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9653572B2 (en) 2015-01-30 2017-05-16 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device

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