KR100818404B1 - Method for forming ega mark for photo process in a semiconductor device - Google Patents
Method for forming ega mark for photo process in a semiconductor device Download PDFInfo
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- KR100818404B1 KR100818404B1 KR1020060132126A KR20060132126A KR100818404B1 KR 100818404 B1 KR100818404 B1 KR 100818404B1 KR 1020060132126 A KR1020060132126 A KR 1020060132126A KR 20060132126 A KR20060132126 A KR 20060132126A KR 100818404 B1 KR100818404 B1 KR 100818404B1
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 230000008569 process Effects 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 75
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 68
- 239000010937 tungsten Substances 0.000 claims abstract description 68
- 238000000206 photolithography Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 description 33
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
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- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
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Abstract
Description
도 1은 종래 반도체 소자 제조를 위한 포토공정 처리 흐름도,1 is a flow chart of a photo process for manufacturing a conventional semiconductor device;
도 2는 종래 텅스텐 CMP 공정으로 인해 디싱된 EGA 마크와 정상적인 EGA 마크 예시도,2 is a diagram illustrating an EGA mark and a normal EGA mark dished due to a conventional tungsten CMP process;
도 3은 본 발명의 실시 예가 적용되는 EGA 마크의 데이터 베이스 이미지 예시도,3 is an exemplary database image of an EGA mark to which an embodiment of the present invention is applied;
도 4는 종래 텅스텐 CMP 공정으로 인해 디싱된 EGA 마크의 공정 단면 예시도,4 is an exemplary cross-sectional view of an EGA mark dished due to a conventional tungsten CMP process;
도 5a 내지 도 5b는 본 발명의 실시 예에 따른 반도체 포토공정을 위한 EGA 마크 형성 공정 단면도.5A to 5B are cross-sectional views of an EGA mark forming process for a semiconductor photo process according to an embodiment of the present invention.
<도면의 주요 부호에 대한 간략한 설명><Brief description of the major symbols in the drawings>
500 : 제1산화막 502 : EGA 마크 영역500: first oxide film 502: EGA mark region
504 : 텅스텐 플러그 506 : 제2산화막504: tungsten plug 506: second oxide film
508 : 포토레지스트막 508: photoresist film
본 발명은 반도체 포토공정에 관한 것으로, 특히 반도체 소자 제조를 위한 포토공정 중 EGA 정렬 때 사용되는 EGA 마크에서의 텅스텐-잔존물(W-residue) 및 디싱(dishing)을 방지하여 인라인(in-line)에서 EGA 정렬 불량으로 인한 웨이퍼 손실을 방지시킬 수 있는 EGA 마크 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor photo process, and in particular, to prevent tungsten-residue and dishing in the EGA mark used during EGA alignment during the photo process for semiconductor device fabrication, thereby preventing in-line. The present invention relates to an EGA mark formation method which can prevent wafer loss due to misalignment of EGA.
통상적으로 반도체 소자를 제조하기 위한 공정은 크게 반도체 웨이퍼 상에 물질막을 형성하는 증착공정과, 상기 물질막에 패턴을 정의하는 포토리소그라피(Photo-lithography) 공정과, 위 포토리소그라피 공정에 의해 형성된 패턴에 따라 위 물질막을 패터닝하는 식각공정 및 위 반도체 기판 또는 물질막에 전도성을 부여하기 위해 불순물을 주입하는 공정으로 구성된다.In general, a process for manufacturing a semiconductor device is largely a deposition process for forming a material film on a semiconductor wafer, a photo-lithography process for defining a pattern on the material film, and a pattern formed by the photolithography process. Accordingly, an etching process for patterning the gas material layer and a process of injecting impurities to impart conductivity to the semiconductor substrate or the material film.
도 1은 위와 같은 반도체 소자 제조를 위한 공정 중 특히 포토공정의 일반적인 처리 흐름을 도시한 것이다. 위 도 1을 참조하여, 종래 반도체 포토공정의 동작을 살펴보면, 소프트 베이크(softbake)(S100)가 끝난 웨이퍼(wafer)는 스텝퍼(stepper)의 OF 검출기로 이동된 후에 가장 먼저 웨이퍼 노치 정렬(wafer notch alignment)(S102)이 실시되고, 웨이퍼 노치 정렬이 완료된 후에는 웨이퍼 스테이지(wafer stage)로 이동되어 웨이퍼 EGA 정렬(wafer EGA alignment)(S104)이 실시되게 된다. 1 illustrates a general process flow of a photo process, in particular, a process for manufacturing a semiconductor device as described above. Referring to FIG. 1, the operation of the conventional semiconductor photo process, the wafer after softbake (S100) is moved to the OF detector of the stepper (wafer) first wafer notch alignment (wafer notch) After the alignment (S102) is performed, and the wafer notch alignment is completed, the wafer is moved to the wafer stage to perform the wafer EGA alignment (S104).
이어 웨이퍼 EGA 정렬된 웨이퍼에 대한 패턴 노광(wafer pattern exposure)(S106)이 실시되고, 패턴 노광이 완료된 웨이퍼는 트랙의 웨이퍼 에지 노광(Wafer Edge Exposure : WEE) 유닛(unit)으로 이동하여서, WEE 공정(S108)이 실시된다. Subsequently, a wafer pattern exposure S106 is performed on the wafer EGA aligned wafer, and the wafer on which the pattern exposure is completed is moved to a wafer edge exposure (WEE) unit of the track, thereby performing a WEE process. (S108) is performed.
그러나 위와 같은 종래 포토공정에서는 EGA 정렬 시 EGA 마크에 그 전 공정인 텅스텐 CMP에 의해 잔존물(residue)이 자주 발생된다. 도 2에는 종래 텅스텐 CMP에 의해 EGA 마크에 텅스텐 잔존물이 발생한 이미지(a)와 정상적인 EGA 마크 이미지(b)를 도시하였다. 위 도 2의 (a)에서 보여지는 바와 같은 EGA 마크상 텅스텐 잔존물 발생은 텅스텐 CMP 시 발생하는 디싱(dishing)이 원인이 되는데, 이러한 문제가 EGA 마크에 발생되는 경우, 후속 단계인 포토(photo) 노광(exposure)을 진행할 수 없어 불필요하게 웨이퍼(wafer)를 폐기시키게 되는 등의 문제점이 있었다.However, in the conventional photo process as described above, residues are frequently generated by tungsten CMP, which is the previous process, on the EGA mark during EGA alignment. 2 shows an image (a) and a normal EGA mark image (b) in which tungsten residues are generated in an EGA mark by conventional tungsten CMP. The generation of tungsten residue on the EGA mark as shown in FIG. 2 (a) above is caused by dishing occurring in the tungsten CMP. When such a problem occurs in the EGA mark, the next step is photo. There was a problem that the exposure could not proceed and the wafer was discarded unnecessarily.
따라서, 본 발명의 목적은 반도체 소자 제조를 위한 포토공정 중 EGA 정렬 때 사용되는 EGA 마크에서의 텅스텐-잔존물(W-residue) 및 디싱(dishing)을 방지하여 인라인(in-line)에서 EGA 정렬 불량으로 인한 웨이퍼 손실을 방지시킬 수 있는 EGA 마크 형성방법을 제공함에 있다.Accordingly, an object of the present invention is to prevent tungsten-residue and dishing in the EGA mark used in the EGA alignment during the photolithography process for manufacturing a semiconductor device, thereby preventing EGA alignment in-line. The present invention provides a method for forming an EGA mark that can prevent wafer loss caused by the wafer.
상술한 목적을 달성하기 위한 본 발명은 반도체 포토공정을 위한 EGA 마크 형성 방법으로서, (a)반도체 기판상 제1산화막 상부에 포토공정을 위한 EGA 마크 영역을 식각 형성시키는 단계와, (b)상기 EGA 마크가 형성된 제1산화막 상부에 텅스텐 플러그를 증착시켜 상기 EGA 마크내 텅스텐 플러그를 충진시키는 단계와, (c)상기 텅스텐 플러그 상부에 제2산화막을 증착시키는 단계와, (d)상기 제2산화막을 포토리소그라피 공정을 통해 패터닝 식각하여 상기 EGA 마크 상부의 텅스텐 플러그에만 제2산화막을 잔존시키는 단계와, (e)상기 EGA 마크외 영역의 상기 제1산화막상 증착된 텅스텐 플러그와 상기 제2산화막을 텅스텐 CMP를 통해 제거시키는 단계를 포함하는 것을 특징으로 한다.In accordance with another aspect of the present invention, there is provided a method for forming an EGA mark for a semiconductor photo process, comprising: (a) etching an EGA mark region for a photo process on an upper surface of a first oxide layer on a semiconductor substrate, and (b) Depositing a tungsten plug on the first oxide film on which the EGA mark is formed to fill the tungsten plug in the EGA mark, (c) depositing a second oxide film on the tungsten plug, and (d) the second oxide film Patterning and etching through the photolithography process so that the second oxide film remains only on the tungsten plug on the EGA mark, and (e) forming the tungsten plug and the second oxide film deposited on the first oxide film outside the EGA mark. And removing through tungsten CMP.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.
도 3은 본 발명의 실시 예가 적용되는 EGA 마크(mark)의 데이터 베이스(Data Base) 이미지(image)의 일 예를 도시한 것으로, 텅스텐 CMP후 후속공정인 포토(photo) 또는 노광(exposure)을 위한 EGA 마크는 위 도 3에서 보여지는 같이, 산화막 영역은 약 18μm로 형성되며, 텅스텐 플러그가 증착되는 EGA 마크는 2μm로 형성된다.3 illustrates an example of a database image of an EGA mark to which an embodiment of the present invention is applied. FIG. 3 illustrates a photo or exposure after tungsten CMP. As shown in FIG. 3, the EGA mark is formed in an oxide region of about 18 µm, and the EGA mark in which a tungsten plug is deposited is formed in 2 µm.
위 도 3에서와 같이 EGA 마크(300)간 산화막(302) 간격이 18μm로 비교적 넓게 형성됨으로 인해 EGA 마크내 텅스텐 플러그 증착 후 텅스텐 CMP 공정 시, 도 4에서 보여지는 바와 같이, 디싱(dishing)에 의해 산화막(302) 영역에 텅스텐 잔존물(W-residue)(304)이 남게됨으로서 후속 포토 장비에서 웨이퍼 정렬이 어렵게 되는 문제점이 있었음은 전술한 바와 같다.As shown in FIG. 3, the
이를 위해 본 발명에서는 EGA 마크상 텅스텐 플러그 증착시키고, 텅스텐 상부에 얇게 산화막을 증착시킨 후, 텅스텐 플러그 상부에 얇게 증착된 산화막을 포토리소그라피 공정을 통해 텅스텐 플러그가 채워진 EGA 마크 부분만 남도록 식각하 여 이후, 텅스텐 CMP 공정시 위 산화막에 의해 텅스텐 플러그가 채워진 EGA 마크내 텅스텐 플러그는 손실되지 않으면서도 EGA 마크간 산화막 영역에 잔존되는 텅스텐 잔존물이 완전히 식각되도록 한다. To this end, in the present invention, after depositing a tungsten plug on the EGA mark, and depositing a thin oxide film on the top of the tungsten, the thin film deposited on the tungsten plug is etched to leave only the portion of the tungsten plug filled with the tungsten plug through a photolithography process. In the tungsten CMP process, the tungsten plug in the tungsten plug filled with the above oxide film is completely etched while the tungsten plug remaining in the oxide region between the EGA marks is not lost.
이때 위와 같은 텅스텐 CMP시 텅스텐 플러그 상부에 증착되는 산화막과 텅스텐의 식각 선택비가 약 1:50이 되므로, 위 산화막은 텅스텐 CMP시 식각정지층으로써 작용하게 되며, 위 텅스텐 플러그가 채워진 EGA 마크 상부에 증착된 산화막은 텅스텐 CMP를 오버 폴리싱(over polishing)하여도 EGA 마크쪽의 텅스텐은 오버 폴리싱되지 않도록 하는 작용을 하게 된다.At this time, since the etch selectivity of the oxide film deposited on the tungsten plug during tungsten CMP and the tungsten etching selectivity is about 1:50, the oxide film acts as an etch stop layer during the tungsten CMP, and is deposited on the top of the EGA mark filled with the tungsten plug. The oxide film acts to prevent the tungsten on the EGA mark from being overpolished even if the tungsten CMP is over polished.
도 5a 내지 도 5d는 본 발명의 실시 예에 따라 EGA 마크의 산화막 영역내 텅스텐 잔존물(W-residue) 및 디싱(dishing)을 방지하여 포토 공정에서 웨이퍼 정렬 실패를 방지시키는 EGA 마크 형성방법의 공정 단면도를 도시한 것이다. 이하 위 도 5a 내지 도 5d를 참조하여 본 발명의 EGA 마크 형성 공정을 상세히 설명하기로 한다.5A to 5D are cross-sectional views of an EGA mark forming method for preventing wafer alignment failure in a photo process by preventing tungsten residue (W-residue) and dishing in an oxide region of an EGA mark according to an embodiment of the present invention. It is shown. Hereinafter, the EGA mark forming process of the present invention will be described in detail with reference to FIGS. 5A to 5D.
먼저, 도 5a에서 보여지는 바와 같이, 위 도 3에서 도시된 바와 같은 EGA 마크 데이터 베이스(data base) 이미지(image)와 같은 간격으로 반도체 기판의 제1산화막(oxide)(500) 상부에 형성된 EGA 마크(502) 내에 텅스텐 플러그(504)를 증착시킨 후, 위 증착된 텅스텐 플러그(504) 상부에 제2산화막(506)을 얇은 두께로 증착시킨다.First, as shown in FIG. 5A, an EGA formed on an upper portion of the
그런 후, 위 도 5b에서 보여지는 바와 같이, 위 텅스텐 플러그(504) 상부에 얇게 증착되는 제2산화막(oxide)(506) 상부 전면에 포토레지스트막(photo resist layer)(508)을 도포시킨 후, 위 EGA 마크(502)가 형성된 영역에만 포토레지스트막(508)이 남도록 포토리소그라피(photo-lithography) 공정을 통해 패터닝(patterning)시킨다.Thereafter, as shown in FIG. 5B, after the
이어, 위 도 5c에서와 같이, 위 패터닝(patterning)된 포토레지스트막(508)을 마스크로 하여 위 EGA 마크(mark)(502)가 형성된 영역 외의 제2산화막(506)을 식각하여 텅스텐 플러그가 채워진 EGA 마크(502) 상부에만 제2산화막(506)이 남도록 한다.Subsequently, as shown in FIG. 5C, the tungsten plug is etched by etching the
그런 후, 위 도 5d에서와 같이, 텅스텐 CMP 공정을 수행하여 EGA 마크(502)외의 제1산화막(500) 영역에 증착된 텅스텐 플러그와 EGA 마크(502) 상부에 남겨진 제2산화막(506)을 차례로 식각시켜, EGA 마크(502)내 증착된 텅스텐 플러그(504)외에 제1산화막(500) 영역에 디싱에 의한 텅스텐 잔존물이 발생하지 않도록 한다. Thereafter, as shown in FIG. 5D, the tungsten plug deposited on the region of the
즉, 위 EGA 마크(502) 상부에 패터닝 형성된 제2산화막(506)은 텅스텐 CMP(Chemical Mechanical Polishing)시 텅스텐 플러그(W-plug)(504)와의 식각 선택비(etch ratio)가 약 1:50이 되므로, 위 제2산화막(506)은 텅스텐 CMP시 식각 정지막(stop layer)으로써 작용할 수 있게 된다. That is, the
따라서 위와 같은 EGA 마크(502) 상부에 남은 제2산화막(506)에 의해 텅스텐 CMP(Chemical Mechanical Polishing)를 오버 폴리싱(over polishing) 수행하는 경우에도 EGA 마크(502)내 증착된 텅스텐 플러그(504)는 오버 폴리싱에 의한 영향을 받지 않게 된다.Therefore, even when overpolishing tungsten chemical mechanical polishing (CMP) by the
상기한 바와 같이, 본 발명에서는 반도체 포토 공정 시 EGA 정렬을 위한 EGA 마크 형성방법에 있어서, EGA 마크상 텅스텐 플러그(W-plug) 증착시키고, EGA 마크상부에만 얇은 산화막을 패터닝 증착시킨 후, 텅스텐 CMP 공정을 진행시킴으로써, 텅스텐 CMP 공정시 위 산화막에 의해 텅스텐 플러그가 채워진 EGA 마크(mark)내 텅스텐 플러그는 손실되지 않으면서도 EGA 마크간 산화막 영역에 잔존되는 텅스텐 잔존물이 완전히 식각시킬 수 있어 EGA 마크의 텅스텐 잔존물 및 디싱을 방지시켜 후속 포토 공정시 EGA 정렬 불량으로 인한 웨이퍼 손실을 방지시킬 수 있게 된다.As described above, in the present invention, in the EGA mark forming method for EGA alignment in the semiconductor photo process, tungsten plug (W-plug) is deposited on the EGA mark, and a thin oxide film is patterned on only the EGA mark, followed by tungsten CMP. By proceeding the process, the tungsten plug in the EGA mark filled with the tungsten plug by the above oxide film during the tungsten CMP process can be completely etched without remaining lost in the tungsten residue in the oxide region between the EGA marks. Residue and dishing can be prevented to prevent wafer loss due to EGA misalignment in subsequent photo processes.
한편 상술한 본 발명의 설명에서 실시 예에는 구체적인 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, the embodiments of the present invention described above have been described in detail, but various modifications can be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.
이상에서 설명한 바와 같이, 본 발명에서는 반도체 포토 공정 시 EGA 정렬을 위한 EGA 마크 형성방법에 있어서, EGA 마크상 텅스텐 플러그 증착시키고, EGA 마크상부에만 얇은 산화막을 패터닝 증착시킨 후, 텅스텐 CMP 공정을 진행시킴으로써, 텅스텐 CMP 공정시 위 산화막에 의해 텅스텐 플러그가 채워진 EGA 마크내 텅스텐 플러그는 손실되지 않으면서도 EGA 마크간 산화막 영역에 잔존되는 텅스텐 잔존물이 완전히 식각시킬 수 있어 EGA 마크의 텅스텐 잔존물 및 디싱을 방지시켜 후속 포토 공정시 EGA 정렬 불량으로 인한 웨이퍼 손실을 방지시킬 수 있는 이점이 있다.As described above, in the present invention, in the method of forming an EGA mark for EGA alignment during a semiconductor photo process, a tungsten plug is deposited on an EGA mark, and a thin oxide film is patterned on only the EGA mark, followed by a tungsten CMP process. In the tungsten CMP process, the tungsten plug in the tungsten plug filled with the above oxide film can be completely etched away from the tungsten residue remaining in the oxide region between the EGA marks without losing the tungsten plug. In the photo process, there is an advantage of preventing wafer loss due to misalignment of the EGA.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000053448A (en) * | 1999-01-12 | 2000-08-25 | 루센트 테크놀러지스 인크 | Method for making an integrated circuit including alignment marks |
| KR20010064079A (en) * | 1999-12-24 | 2001-07-09 | 박종섭 | A method for forming alignment mark with improved alignment accuracy |
| KR20010070511A (en) * | 2000-01-11 | 2001-07-25 | 추후제출 | Process for producing adjusting marks |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000053448A (en) * | 1999-01-12 | 2000-08-25 | 루센트 테크놀러지스 인크 | Method for making an integrated circuit including alignment marks |
| KR20010064079A (en) * | 1999-12-24 | 2001-07-09 | 박종섭 | A method for forming alignment mark with improved alignment accuracy |
| KR20010070511A (en) * | 2000-01-11 | 2001-07-25 | 추후제출 | Process for producing adjusting marks |
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