KR100780642B1 - Method for fabricating the same of semiconductor device with dual poly gate - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor device having a dual poly gate for forming a gate electrode having a low specific resistance while preventing boron out diffusion, and a method of manufacturing the same. The present invention provides a method for forming a gate insulating film on a semiconductor substrate. Forming a first P-type polysilicon electrode on the gate insulating film, forming a first barrier layer on the first P-type polysilicon electrode, and forming a second P-type poly on the first barrier layer Forming a silicon electrode, forming a second barrier layer on the second P-type polysilicon electrode, forming a metal electrode on the second barrier layer, and forming the first electrode layer through a predetermined thermal process And inducing a reaction of the second P-type polysilicon electrode to form a third barrier layer which serves to suppress diffusion barrier and increase resistance, and further, NMOS and PMOS are positively defined. Forming an N-type polysilicon electrode on an NMOS, a first P-type polysilicon electrode on a PMOS, a first barrier layer on each of the polysilicon electrodes, and a first layer of the PMOS Forming a second P-type polysilicon electrode on the barrier layer, forming a second barrier layer on the entire surface including the second P-type polysilicon electrode, and forming a metal electrode on the second barrier layer And inducing a reaction between the first barrier layer and the second P-type polysilicon electrode through a predetermined thermal process to form a third barrier layer which serves to suppress diffusion barrier and increase resistance. In the dual poly gate, the boron out diffusion phenomenon is eliminated, and the high-speed device characteristics are improved by forming a gate electrode having a low electrode, thereby improving device characteristics and reliability.

Dual Poly Gate, Boron Out Diffusion, Poly Depletion, Thermal Process

Description

Method of manufacturing a semiconductor device having a dual poly gate {METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE WITH DUAL POLY GATE}

1 is a cross-sectional view illustrating a general dual poly gate;

2 is a graph comparing inversion capacitances of dual poly gates;

3 and 4 are a cross-sectional view and a graph for comparing a semiconductor device having a dual poly gate according to the prior art,

5A to 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a first embodiment of the present invention;

6A to 6F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a second preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

51 semiconductor substrate 52 gate insulating film

53 polysilicon electrode 54 tungsten silicide

55: titanium 55a: titanium silicide

56: second P-type polysilicon electrode 57: mask pattern

58: tungsten nitride film 59: tungsten

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a dual poly gate.

As the semiconductor devices are highly integrated, the pitch between gates is reduced in the process of processing a CMOS device using a silicon wafer. In the conventional CMOS device, a polysilicon film doped with n-type impurities is used as each gate electrode of the NMOS and PMOS devices. In this case, the NMOS device has a surface channel characteristic, whereas the PMOS device has a buried channel characteristic. However, when the width (half width) of the gate electrode is narrowed to 100 nm or less due to the buried channel characteristic of the PMOS device, there is a problem in that a short channel effect appears.

Accordingly, a dual gate structure has been proposed in which a gate electrode of a PMOS device is formed of a polysilicon layer doped with P-type impurities in a CMOS device process having a narrow gate channel length, so that the PMOS device has surface channel characteristics. . Such a double gate structure has an effect of reducing the short channel effect.

1 is a cross-sectional view illustrating a general dual poly gate.

Referring to FIG. 1, a gate insulating film 12 is formed on a semiconductor substrate 11 in which NMOS and PMOS are defined, and an N-type polysilicon film doped with phosphorus (P) in each NMOS on the gate insulating film 12. (13b), P-type polysilicon film 13a doped with boron was formed in PMOS. Subsequently, metal electrodes (Xix) 14 were formed on each of the polysilicon films 13a and 13b.

Although the dual poly gate has the effect of reducing the short channel effect, the threshold voltage shift and fluctuation due to boron penetration into the channel region appear, and the interface between the gate insulating layer 12 and the polysilicon layers 13a and 13b is observed. There is a problem in that deterioration of device characteristics due to poly silicon depletion occurs.

The phenomenon due to boron penetration into the channel region can be reduced by nitriding the surface of the gate insulating film 12, but the polysilicon depletion phenomenon caused by the out diffusion of boron toward the metal electrode cannot be prevented.

2 is a graph comparing inversion capacitances of dual poly gates.

Referring to FIG. 2, an inversion capacitance of an N-type polysilicon electrode of an NMOS and a P-type polysilicon electrode of a PMOS may be compared. Looking at the graph, in the case of PMOS, since the boron is out-diffused to the metal electrode, the capacitance value of the PMOS is smaller than the capacitance value of the NMOS due to the polysilicon depletion phenomenon. This means that the capacitive equivalent thickness (CET) of the gate insulating film is increased. In the case of semiconductor devices having a gate-to-gate spacing of 100 nm or less, the threshold voltage change value becomes large, resulting in deterioration of device characteristics. .

In addition, tungsten is used instead of tungsten silicide to secure high-speed device characteristics of semiconductor devices. However, when tungsten is directly formed as a metal electrode on the polysilicon electrode, a volume expansion occurs due to siliconization during a subsequent thermal process, and a stress reaction occurs, thereby causing a diffusion barrier between the tungsten and the polysilicon electrode. Diffusion Barrier) film is formed.

3 and 4 are cross-sectional views and graphs for comparing semiconductor devices having dual poly gates according to the prior art. For convenience of description, only the PMOS region of the semiconductor device is illustrated in FIG. 3.

As shown in FIG. 3, the P-type polysilicon electrode 32 is formed on the semiconductor substrate 31 in the PMOS region, and the gate electrode 33 is formed on the P-type polysilicon electrode 32. At this time, the gate electrode 33 is formed of tungsten / tungsten nitride film (a), tungsten / tungsten nitride film / tungsten silicide (b) and tungsten / tungsten nitride film / TiN / Ti (c) on which the metal electrode tungsten and barrier metal are stacked do.

Reference will be made to FIG. 4 to compare the gate electrodes 33.

Referring to FIG. 4, gate resistances (a), gate oxide film reliability (b), and poly depletion rate (c) of each gate electrode 33 are compared.

First, in terms of the gate resistance (a), the use of tungsten nitride film / tungsten silicide and tungsten nitride film / TiN / Ti as the barrier metal shows better characteristics than that of the tungsten nitride film. This suppresses the formation of a Si-N insulating film in which the tungsten nitride film / tungsten silicide and tungsten nitride film / TiN / Ti are additionally inserted into the upper part of the polysilicon electrode and the barrier metal inserted in the upper tungsten nitride film can be formed by decomposition of nitrogen during the thermal process. Because.

In terms of Gate Oxide Integrity (GOI) (b), tungsten nitride film / TiN / Ti is the worst and tungsten nitride film / tungsten silicide is the best. This is because the tungsten silicide on the polysilicon electrode relieves the stress applied by the hard mask nitride film on the gate electrode.

In terms of poly depletion rate (c), the highest polydepletion rate is due to the highest boron out diffusion in the tungsten nitride film / tungsten silicide.

As described above, the use of tungsten / tungsten nitride film / tungsten silicide / polysilicon electrode as the gate electrode is most advantageous in terms of gate resistance and gate oxide film reliability. However, in the case of a semiconductor device having dual poly gates, deteriorated poly silicon depletion occurs in the P-type polysilicon electrode, resulting in deterioration of device characteristics.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and provides a semiconductor device having a dual poly gate for forming a gate electrode having a low specific resistance while preventing boron out diffusion, and a method of manufacturing the same. There is a purpose.

The present invention provides a method of forming a gate insulating film on a semiconductor substrate, forming a first P-type polysilicon electrode on the gate insulating film, and forming a first barrier layer on the first P-type polysilicon electrode. Forming a second P-type polysilicon electrode on the first barrier layer, forming a second barrier layer on the second P-type polysilicon electrode, and forming a metal electrode on the second barrier layer And inducing a reaction between the first barrier layer and the second P-type polysilicon electrode through a predetermined thermal process to form a third barrier layer that serves to suppress diffusion barrier and increase resistance. Forming an N-type polysilicon electrode in an NMOS and a first P-type polysilicon electrode in a PMOS on a semiconductor substrate on which a PMOS is defined, and forming a first barrier layer on each polysilicon electrode, wherein the PMOS Forming a second P-type polysilicon electrode on the first barrier layer of the second semiconductor layer; forming a second barrier layer on the entire surface including the second P-type polysilicon electrode; and forming a metal electrode on the second barrier layer. And forming a third barrier layer that serves to suppress diffusion and resistance increase by inducing a reaction between the first barrier layer and the second P-type polysilicon electrode through a predetermined thermal process.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Example  One

5A to 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a first embodiment of the present invention.

As shown in FIG. 5A, a gate insulating film 52 is formed on a semiconductor substrate 51 in which NMOS and PMOS are defined. Although not illustrated, the semiconductor substrate 51 may include an isolation layer and a well.

Subsequently, a polysilicon electrode 53 is formed on the gate insulating film 52. The polysilicon electrode 53 may be an undoped polysilicon electrode 53 or an N-type doped polysilicon electrode 53.

Subsequently, the first photoresist film pattern 54 is formed on the polysilicon electrode 53 to open the polysilicon electrode 53a of the PMOS.

Subsequently, the first P-type polysilicon electrode 53a is formed by doping the P-type impurity to the polysilicon electrode 53a of the PMOS using the first photoresist pattern 54 as an ion implantation mask. Here, boron may be used as the P-type impurity.

Next, the first photosensitive film pattern 54 is removed. The first photoresist pattern 54 may be removed by dry etching, but preferably by oxygen plasma.

As shown in FIG. 5B, the second photoresist film pattern 55 is formed on the polysilicon electrode 53a of the PMOS to open the polysilicon electrode 53b of the NMOS.

Next, the N-type polysilicon electrode 53b is formed by doping the N-type impurity on the polysilicon electrode 53b of the NMOS with the second photoresist pattern 54 as an ion implantation mask. Here, phosphorus (Phosphorus) may be used as the N-type impurity.

Next, the second photosensitive film pattern 55 is removed. The second photoresist pattern 55 may be removed by dry etching, but preferably by oxygen plasma.

As shown in FIG. 5C, tungsten silicide (Six, 54) and titanium (Ti, 55) are sequentially formed on the polysilicon electrodes 53a and 53b. Here, the tungsten silicide 54 and the titanium 55 serve to serve as a diffusion barrier of tungsten, which is formed on the upper part, and are chemical vapor deposition (CVD) and physical vapor deposition (Physical Vapor Deposition). PVD) and Atomic Layer Deposition (ALD). The tungsten silicide 54 is formed to have a thickness of 50 kPa to 100 kPa and titanium 55 to 30 kPa to 60 kPa.

Subsequently, a second P-type polysilicon electrode 56 is formed on the titanium 55. Here, the second P-type polysilicon electrode 56 is formed by chemical vapor deposition (SiHCl ₃ + H ₂ → Si + 3HCl), but is injected by injecting a gas containing P-type impurities, preferably a boron element. It may be formed by doping with (In-Situ). The second P-type polysilicon electrode 56 is formed at least 50 GPa (10 GPa-50 GPa).

As described above, the second P-type polysilicon electrode 56 is capable of supplying boron short to the first P-type polysilicon electrode 53a of the lower PMOS by diffusing boron to the bottom during the subsequent thermal process. The phenomenon can be suppressed, and the increase in resistance can be suppressed by forming titanium silicide (TiSix) in combination with the titanium 55.

As shown in FIG. 5D, a mask pattern 57 for opening the second P-type polysilicon electrode 56 of the NMOS is formed, and the second P-type polysilicon electrode 56 of the NMOS is formed with the mask pattern 57. Is etched to leave only the second P-type polysilicon electrode 56 of the PMOS.

The reason for removing the second P-type polysilicon electrode 56 in the NMOS region is that when the second P-type polysilicon electrode 56 is formed in the NMOS region, poly-doped N-type impurity in the lower NMOS region is formed during a subsequent thermal process. This is because boron is diffused to the silicon electrode 53b and a counter doping phenomenon may occur to change the flat band voltage.

As shown in FIG. 5E, the mask pattern 57 is removed. The mask pattern 57 may be removed by dry etching, preferably by oxygen plasma.

Subsequently, tungsten nitride films 58 and tungsten 59 are sequentially formed on the uppermost layers of each of the NMOS and PMOS. Here, the tungsten nitride film 58 is formed as a diffusion barrier for suppressing silicon compounding of the upper tungsten 59 and the lower second P-type polysilicon electrode 56 in a subsequent thermal process to be at least 50 GPa.

As shown in FIG. 5F, a thermal process is performed, and the second P-type polysilicon electrode 56 and titanium 55 in the PMOS region are completely reacted until only titanium silicide 55a is present. While the titanium silicide 55a is formed, the borons of the second P-type polysilicon electrode 56 are boron out diffused to the bottom or top.

The thermal process is performed at a temperature not exceeding 600 ° C. (100 ° C. to 600 ° C.), which is a temperature at which nitrogen in the tungsten nitride film 58 is decomposed, that is, a temperature sufficiently lower than 800 ° C. to form the titanium silicide 55 a. No silicon compounding occurs during the process.

In addition, since the second P-type polysilicon electrode 56 and the titanium 55 in the PMOS region do not remain in the thermal process, and both are changed to titanium silicide 55a, even if nitrogen inside the tungsten nitride film 58 is decomposed in a subsequent process. Since no polysilicon is present, the Si-N insulating film is not formed.

Therefore, during the thermal process, boron is diffused into the upper and lower portions of the second P-type polysilicon electrode 56 to prevent polydepletion due to the boron-out diffusion of the first P-type polysilicon electrode 53a of the lower PMOS, while preventing titanium. Since the silicide 55a is formed to suppress the increase in resistance, high speed operation characteristics of the device are enabled.

Example  2

6A to 6E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a second exemplary embodiment of the present invention.

As shown in FIG. 6A, a gate insulating film 62 is formed on a semiconductor substrate 61 in which NMOS and PMOS are defined. Although not illustrated, the semiconductor substrate 61 may include an isolation layer and a well.

Next, a polysilicon electrode 63 is formed on the gate insulating film 62. Here, the polysilicon electrode 63 may be an undoped polysilicon electrode 63 or an N-type doped polysilicon electrode 63.

Subsequently, the first photoresist film pattern 64 is formed on the polysilicon electrode 63 to open the polysilicon electrode 63a of the PMOS.

Subsequently, the first P-type polysilicon electrode 63a is formed by doping P-type impurities into the polysilicon electrode 63a of the PMOS using the first photoresist pattern 64 as an ion implantation mask. Here, boron may be used as the P-type impurity.

Next, the first photosensitive film pattern 64 is removed. The first photoresist pattern 64 may be removed by dry etching, but preferably by oxygen plasma.

As shown in FIG. 6B, the second photoresist film pattern 65 is formed on the first P-type polysilicon electrode 63a of the PMOS to open the polysilicon electrode 63b of the NMOS.

Subsequently, the N-type polysilicon electrode 63b is formed by doping the N-type impurity to the polysilicon electrode 63b of the NMOS with the second photoresist pattern 64 as an ion implantation mask. Here, phosphorus (Phosphorus) may be used as the N-type impurity.

Subsequently, the second photosensitive film pattern 65 is removed. The second photoresist pattern 65 may be removed by dry etching, but preferably by oxygen plasma.

As shown in FIG. 6C, tungsten silicide (Six, 64) and titanium (Ti, 65) are sequentially formed on the polysilicon electrodes 63a and 63b. Here, the tungsten silicide 64 and the titanium 65 serve as a diffusion barrier of tungsten, which is formed on the upper part, and are chemical vapor deposition (CVD) and physical vapor deposition (Physical Vapor Deposition). PVD) and Atomic Layer Deposition (ALD). Further, tungsten silicide 64 is formed to have a thickness of 50 kPa to 100 kPa and titanium 65 to 30 kPa to 60 kPa.

Subsequently, an undoped polysilicon 66 is formed on the titanium 65. The undoped polysilicon 66 is formed by chemical vapor deposition (SiHCl ₃ + H ₂ → Si + 3HCl), but without injecting a gas containing boron element in situ as shown in FIG. 5C, and undoped polysilicon 66 ). The undoped polysilicon 66 is formed at least 50 kPa or less (10 kPa to 50 kPa).

As shown in FIG. 6D, a mask pattern 67 is formed to open the undoped polysilicon 66 of the PMOS, and the mask pattern 67 is formed into P on the undoped polysilicon 66 of the PMOS using an ion implantation mask. A second impurity polysilicon electrode 66a is formed only in the PMOS region by ion implantation of a type impurity, preferably boron.

The reason why the second P-type polysilicon electrode 66a is formed only in the PMOS region is that when the P-type polysilicon is formed in the NMOS region, the polysilicon electrode 63b doped with the N-type impurity in the lower NMOS region during the subsequent thermal process is performed. This is because boron diffuses to cause counter doping, causing a change in the flat band voltage.

As shown in FIG. 6E, the mask pattern 67 is removed. The mask pattern 67 may be removed by dry etching, preferably by oxygen plasma.

Next, the tungsten nitride film 68 and the tungsten 69 are sequentially formed on the polysilicon electrodes 66 and 66a. In this case, the tungsten nitride film 68 serves as a diffusion barrier to suppress siliconization of the upper tungsten 69 and the lower polysilicon 66, 66a in a subsequent thermal process, and is formed at least 50 GPa. do.

As shown in FIG. 6F, the thermal process is performed, until the polysilicon 66, 66a and the titanium 65 are completely reacted, so that only the titanium silicide 65a is present. While the titanium silicide 65a is formed, the borons of the second P-type polysilicon electrode 66a are boron out diffused to the bottom or top.

The thermal process is performed at a temperature not exceeding 600 ° C. (100 ° C. to 600 ° C.), which is a temperature at which nitrogen in the tungsten nitride film 68 is decomposed, that is, a temperature sufficiently lower than 800 ° C. to form the titanium silicide 65a. No silicon compounding occurs during the process.

In addition, since the polysilicon 66, 66a and titanium 65 did not remain during the thermal process, and both were changed to titanium silicide 65a, even though nitrogen in the tungsten nitride film 68 was decomposed in the subsequent process, the polysilicon did not exist. Si-N insulating film is not formed.

Therefore, during the thermal process, boron is diffused into the upper and lower portions of the second P-type polysilicon electrode 66 to prevent polydepletion due to the boron out diffusion of the first P-type polysilicon electrode 63a of the lower PMOS, while preventing titanium. The silicide 65a is formed to suppress the increase in resistance, thereby enabling the high-speed operation characteristics of the device.

In the present invention described above, P-type polysilicon is formed in the middle of the diffusion barrier layer formed between the polysilicon electrode and tungsten, which is a metal electrode, and boron is out-diffused from the P-type polysilicon formed in the middle during the thermal process so that the polysilicon of the polysilicon electrode The depletion phenomenon is suppressed, and polysilicon formed between titanium and the diffusion barrier layer forms titanium silicide by silicon compounding, thereby increasing resistance.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The semiconductor device having a dual poly gate and a method of manufacturing the same according to the present invention eliminate the boron out diffusion phenomenon in the dual poly gate and improve the device characteristics and reliability by improving the high speed device characteristics by forming a gate electrode having a low electrode. It is effective to improve.

Claims (18)

Forming a gate insulating film on the semiconductor substrate; Forming a first P-type polysilicon electrode on the gate insulating film; Forming a first barrier layer on the first P-type polysilicon electrode; Forming a second P-type polysilicon electrode on the first barrier layer; Forming a second barrier layer on the second P-type polysilicon electrode; Forming a metal electrode on the second barrier layer; And Inducing a reaction between the first barrier layer and the second P-type polysilicon electrode through a predetermined thermal process to form a third barrier layer that serves to suppress diffusion barriers and increase resistance; Gate electrode manufacturing method of a semiconductor device comprising a. The method of claim 1, The first barrier layer is formed by stacking a silicide-based first layer and a metal-based second layer, and reacting the second layer with the second P-type polysilicon electrode by the thermal process. Gate electrode manufacturing method. The method of claim 2, And in the thermal process, the second layer and the second P-type polysilicon electrode react with each other to form silicide. The method of claim 3, Wherein the first layer is formed of tungsten silicide and the second layer is made of titanium. The method according to any one of claims 1 to 4, The thermal process is a method for manufacturing a gate electrode of a semiconductor device, characterized in that performed at 100 ℃ to 600 ℃. The method of claim 1, The first and second P-type polysilicon electrodes are formed by injecting boron gate electrode manufacturing method of a semiconductor device. The method of claim 1, And the second barrier layer is formed of a tungsten nitride film. Forming a gate insulating film on a semiconductor substrate having an NMOS region and a PMOS region defined therein; Forming a first polysilicon electrode comprising a region doped with an N-type impurity corresponding to the NMOS region and a region doped with a P-type impurity corresponding to the PMOS region; Forming a first barrier layer on the first polysilicon electrode; Forming a second polysilicon electrode doped with a P-type impurity that is located only on an area doped with the P-type impurity of the first polysilicon electrode on the first barrier layer; Forming a second barrier layer on the entire surface including the second polysilicon electrode; Forming a metal electrode on the second barrier layer; And Inducing a reaction between the first barrier layer and the second polysilicon electrode through a predetermined thermal process to form a third barrier layer that serves to suppress diffusion barriers and increase resistance; Method of manufacturing a semiconductor device having a dual poly gate comprising a. The method of claim 8, The first barrier layer is formed by stacking a silicide-based first layer and a metal-based second layer, wherein the second layer and the second polysilicon electrode react by the thermal process. Method of manufacturing a semiconductor device. The method of claim 9, And in the thermal process, both the second layer and the second polysilicon electrode react to form silicide. The method of claim 10, Wherein the first layer is formed of tungsten silicide and the second layer is formed of titanium. The method according to any one of claims 8 to 11, The thermal process is carried out at 100 ℃ to 600 ℃ manufacturing method of a semiconductor device having a dual poly gate. The method of claim 8, And a first polysilicon electrode and a second polysilicon electrode formed of a region doped with a P-type impurity corresponding to the PMOS region, wherein the first polysilicon electrode and the second polysilicon electrode are formed by injecting boron. The method of claim 8, The second barrier layer is a semiconductor device manufacturing method having a dual poly gate, characterized in that formed by a tungsten nitride film. The method of claim 8, Forming a second polysilicon electrode on the first barrier layer of the PMOS, Forming a polysilicon layer doped with P-type impurities in situ on the first barrier layer; Forming a mask pattern to open the polysilicon layer of the NMOS; Etching the polysilicon layer of the NMOS using the mask pattern as an etch mask to leave a polysilicon layer doped with P-type impurities only in the PMOS; And Removing the mask pattern Method of manufacturing a semiconductor device having a dual poly gate, characterized in that it comprises a. The method of claim 8, Forming a second polysilicon electrode on the first barrier layer of the PMOS, Forming an undoped polysilicon layer on the first barrier layer; Forming a mask pattern to open the undoped polysilicon layer of the PMOS; Forming a second polysilicon electrode by implanting P-type impurities into the undoped polysilicon layer of the PMOS using the mask pattern as an ion implantation mask; And Removing the mask pattern Method of manufacturing a semiconductor device having a dual poly gate, characterized in that it comprises a. The method according to claim 15 or 16, And the second polysilicon electrode is formed between 10 kV and 50 kV. The method according to claim 15 or 16, The P-type impurity is a manufacturing method of a semiconductor device having a dual poly gate, characterized in that using the boron.

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