KR100432789B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100432789B1 KR100432789B1 KR10-2002-0038731A KR20020038731A KR100432789B1 KR 100432789 B1 KR100432789 B1 KR 100432789B1 KR 20020038731 A KR20020038731 A KR 20020038731A KR 100432789 B1 KR100432789 B1 KR 100432789B1
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- film
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- 239000004065 semiconductor Substances 0.000 title abstract description 15
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 54
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 35
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 35
- 238000010438 heat treatment Methods 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 20
- 239000010936 titanium Substances 0.000 claims abstract description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 37
- 239000010941 cobalt Substances 0.000 claims description 30
- 229910017052 cobalt Inorganic materials 0.000 claims description 30
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 30
- 239000011229 interlayer Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 7
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000002159 abnormal effect Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910008484 TiSi Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- KPSZQYZCNSCYGG-UHFFFAOYSA-N [B].[B] Chemical compound [B].[B] KPSZQYZCNSCYGG-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관하여 개시한다. 본 발명은, 실리콘 기판에 소오스 영역, 드레인 영역 및 게이트 전극을 포함하는 트랜지스터를 형성하는 단계와, 상기 트랜지스터가 형성된 상기 실리콘 기판 상에 금속막 및 캡핑막을 증착하는 단계와, 제1 열처리 공정을 실시하여 금속 실리사이드막을 형성하는 단계와, 상기 금속 실리사이드막을 형성하지 않은 미반응된 상기 금속막 및 상기 캡핑막을 선택적으로 제거하는 단계와, 상기 금속 실리사이드막을 상변이 시키기 위하여 제2 열처리 공정을 실시하는 단계와, 상기 금속 실리사이드막이 형성된 실리콘 기판 상에 티타늄막을 증착하는 단계와, 제3 열처리 공정을 실시하여 티타늄 실리사이드막을 형성하는 단계와, 상기 티타늄 실리사이드막을 형성하지 않은 미반응된 상기 티타늄막을 제거하는 단계 및 상기 티타늄 실리사이드막을 상변이 시키기 위하여 제4 열처리 공정을 실시하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법을 제공한다.The present invention discloses a method for manufacturing a semiconductor device. The present invention includes forming a transistor including a source region, a drain region, and a gate electrode on a silicon substrate, depositing a metal film and a capping film on the silicon substrate on which the transistor is formed, and performing a first heat treatment process. Forming a metal silicide film, selectively removing the unreacted metal film and the capping film that do not form the metal silicide film, and performing a second heat treatment process to phase change the metal silicide film; Depositing a titanium film on the silicon substrate on which the metal silicide film is formed, performing a third heat treatment process to form a titanium silicide film, removing the unreacted titanium film that does not form the titanium silicide film, and Phase change of titanium silicide film It provides a method for producing a semiconductor device comprising the steps of: conducting a fourth heat treatment step to group.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 코발트 실리사이드막 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a cobalt silicide film of a semiconductor device.
일반적으로, 반도체 소자의 집적도가 증가함에 따라 불순물 영역인 접합영역(Junction)의 깊이가 줄어들어 게이트 전극의 선폭이 감소하고 있는 추세이다. 이로 인해, 반도체 소자에서 요구되는 면저항을 구현하는데 많은 어려움이발생하고 있다. 이러한 반도체 소자의 면저항을 개선시키기 위해 접합영역과 게이트 전극 상에 텅스텐 실리사이드(WSi)보다 비저항이 낮은 코발트 실리사이드(CoSi2)를 동시에 형성하는 살리사이드(Salicide; Self Aligned Silicide) 공정을 실시하고 있다. 살리사이드 공정시 게이트 전극 부분에서는 게이트 전극용 도프트 폴리실리콘(Doped Poly Silicon)과 코발트(Co)가 반응하여 코발트 실리사이드막이 형성되고, 또한 반도체 기판의 접합영역(소오스 영역 및 드레인 영역)과의 계면에서는 반도체 기판의 실리콘과 반응하는 코발트 실리사이드막이 형성된다.In general, as the degree of integration of semiconductor devices increases, the depth of the junction region, which is an impurity region, decreases, thereby decreasing the line width of the gate electrode. As a result, there are many difficulties in implementing the sheet resistance required in the semiconductor device. In order to improve the sheet resistance of the semiconductor device, a salicide (Selficide) process is performed to simultaneously form cobalt silicide (CoSi 2 ) having a lower resistivity than tungsten silicide (WSi) on the junction region and the gate electrode. In the salicide process, a doped polysilicon and a cobalt (Co) for the gate electrode react with each other to form a cobalt silicide layer, and also interface with a junction region (source region and drain region) of the semiconductor substrate. In this case, a cobalt silicide film is formed which reacts with silicon of the semiconductor substrate.
그러나, 코발트 실리사이드막은 후속 열공정, 예컨대 층간절연막의 증착 및 어닐링 공정에서 N+액티브 영역의 코발트 실리사이드막 상에 이상 산화막이 두껍게 형성된다. 상기 이상 산화막은 층간절연막을 형성한 후, N+액티브 영역과 전기적으로 연결되는 콘택을 형성할 때, 콘택 오픈 페일(Contact Open Fail)을 발생시킬 수 있다.However, in the cobalt silicide film, an abnormal oxide film is thickly formed on the cobalt silicide film in the N + active region in a subsequent thermal process such as deposition and annealing of the interlayer insulating film. After forming the interlayer insulating layer, the abnormal oxide layer may generate a contact open fail when forming a contact electrically connected to the N + active region.
본 발명이 이루고자 하는 기술적 과제는 N+액티브 영역의 코발트 실리사이드막 상에 이상 산화막이 두껍게 형성되는 것을 억제할 수 있는 반도체 소자의 제조방법을 제공함에 있다.An object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress the formation of a thick abnormal oxide film on the cobalt silicide film of the N + active region.
도 1 내지 도 15는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위하여 도시한 단면도들이다.1 to 15 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
<도면의 주요 부분에 부호의 설명><Description of the symbols in the main part of the drawing>
110: NMOS 게이트 전극 112: PMOS 게이트 전극110: NMOS gate electrode 112: PMOS gate electrode
114, 116: 저농도 접합영역 120, 122: 고농도 접합영역114, 116: low concentration junction region 120, 122: high concentration junction region
124: 코발트막 126: 캡핑막124: cobalt film 126: capping film
128, 128a: 코발트 실리사이드막 130: 티타늄막128, 128a: cobalt silicide film 130: titanium film
132, 132a: 티타늄 실리사이드막 138: 티타늄 산화막132 and 132a: titanium silicide film 138: titanium oxide film
상기 기술적 과제를 달성하기 위하여 본 발명은, 실리콘 기판에 소오스 영역, 드레인 영역 및 게이트 전극을 포함하는 트랜지스터를 형성하는 단계와, 상기 트랜지스터가 형성된 상기 실리콘 기판 상에 금속막 및 캡핑막을 증착하는 단계와, 제1 열처리 공정을 실시하여 금속 실리사이드막을 형성하는 단계와, 상기 금속 실리사이드막을 형성하지 않은 미반응된 상기 금속막 및 상기 캡핑막을 선택적으로 제거하는 단계와, 상기 금속 실리사이드막을 상변이 시키기 위하여 제2 열처리 공정을 실시하는 단계와, 상기 금속 실리사이드막이 형성된 실리콘 기판 상에 티타늄막을 증착하는 단계와, 제3 열처리 공정을 실시하여 티타늄 실리사이드막을 형성하는 단계와, 상기 티타늄 실리사이드막을 형성하지 않은 미반응된 상기 티타늄막을 제거하는 단계 및 상기 티타늄 실리사이드막을 상변이 시키기 위하여 제4 열처리 공정을 실시하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법을 제공한다.According to an aspect of the present invention, there is provided a method including forming a transistor including a source region, a drain region, and a gate electrode on a silicon substrate, depositing a metal film and a capping film on the silicon substrate on which the transistor is formed; And forming a metal silicide film by performing a first heat treatment process, selectively removing the unreacted metal film and the capping film that do not form the metal silicide film, and performing a second phase change on the metal silicide film. Performing a heat treatment process, depositing a titanium film on a silicon substrate on which the metal silicide film is formed, and performing a third heat treatment process to form a titanium silicide film, and the unreacted non-reacted titanium silicide film. Steps and phases of removing titanium film It provides a method of manufacturing a semiconductor device comprising the step of performing a fourth heat treatment step for the phase change of the titanium silicide film.
상기 금속막은 코발트막이고, 상기 금속 실리사이드막은 코발트 실리사이드막일 수 있다.The metal layer may be a cobalt layer, and the metal silicide layer may be a cobalt silicide layer.
상기 제1 열처리 공정은 400 내지 650℃의 온도에서 실시하고, 상기 제2 열처리 공정은 700 내지 850℃의 온도에서 실시하며, 상기 제3 열처리 공정은 600 내지 750℃의 온도에서 실시하고, 상기 제4 열처리 공정은 700 내지 850℃의 온도에서 실시하는 것이 바람직하다.The first heat treatment process is carried out at a temperature of 400 to 650 ℃, the second heat treatment process is carried out at a temperature of 700 to 850 ℃, the third heat treatment process is carried out at a temperature of 600 to 750 ℃, 4 The heat treatment step is preferably carried out at a temperature of 700 to 850 ℃.
상기 제4 열처리 공정을 실시하는 단계 후에, 상기 실리콘 기판 상에 질화막을 형성하는 단계와, 상기 질화막 상에 층간절연막을 형성하면서 상기 티타늄 실리사이드막 상에 얇은 티타늄 산화막이 형성되도록 하는 단계 및 상기 층간절연막 내에 상기 티타늄 실리사이드막과 연결되는 콘택 플러그를 형성하는 단계를 더 포함할 수 있다.After performing the fourth heat treatment process, forming a nitride film on the silicon substrate, forming an interlayer insulating film on the nitride film, and forming a thin titanium oxide film on the titanium silicide film and the interlayer insulating film The method may further include forming a contact plug in the titanium silicide layer.
상기 트랜지스터의 형성은, 상기 실리콘 기판에 트렌치 구조의 소자 분리막을 형성하는 단계와, 상기 실리콘 기판에 불순물을 이온주입하여 웰을 형성하는 단계와, 상기 웰에 불순물을 이온주입하여 저농도 접합영역을 형성하는 단계와, 상기 실리콘 기판 상에 게이트 산화막 및 게이트 전극을 형성하는 단계와, 상기 게이트 산화막 및 게이트 전극 측벽에 스페이서를 형성하는 단계 및 상기 웰에 불순물을 이온주입하여 고농도 접합영역을 형성하는 단계를 포함하여 이루어진다.The transistor may be formed by forming a device isolation layer having a trench structure in the silicon substrate, implanting impurities into the silicon substrate to form a well, and implanting impurities into the well to form a low concentration junction region. Forming a gate oxide film and a gate electrode on the silicon substrate, forming a spacer on sidewalls of the gate oxide film and the gate electrode, and implanting impurities into the wells to form a high concentration junction region. It is made to include.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시예를 상세하게 설명하기로 한다. 그러나, 이하의 실시예는 이 기술분야에서 통상적인 지식을 가진 자에게 본 발명이 충분히 이해되도록 제공되는 것으로서 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 다음에 기술되는 실시예에 한정되는 것은 아니다. 이하의 설명에서 어떤 층이 다른 층의 위에 존재한다고 기술될 때, 이는 다른 층의 바로 위에 존재할 수도 있고, 그 사이에 제3의 층이 게재될 수도 있다. 또한, 도면에서 각 층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장되었다. 도면상에서 동일 부호는 동일한 요소를 지칭한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. It doesn't happen. In the following description, when a layer is described as being on top of another layer, it may be present directly on top of another layer, with a third layer interposed therebetween. In the drawings, the thickness and size of each layer are exaggerated for clarity and convenience of explanation. Like numbers refer to like elements in the figures.
도 1 내지 도 15는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위하여 도시한 단면도들이다.1 to 15 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
도 1을 참조하면, P형 실리콘 기판(102)을 NMOS 영역과 PMOS 영역으로 정의하기 위해 STI(Shallow Trench Isolation) 공정을 실시하여 소자 분리막(104)을 형성한 후, NMOS 영역에는 'p-' 불순물인 보론(boron)을 주입하여 P-웰(P-Well)을 형성하고, PMOS 영역에는 'n-' 불순물인 인(phosphorous)을 주입하여 N-웰(N-Well)을 형성한다.1, after forming the device isolation film 104 is subjected to STI (Shallow Trench Isolation) process in order to define a P-type silicon substrate 102 in the NMOS region and the PMOS region, NMOS region 'p -' implanting an impurity of boron (boron) to form a P- well (P-well) and, PMOS region has 'n -' by implanting phosphorus (phosphorous) impurity to form the N- well (N-well).
도 2를 참조하면, 전체 구조 상부에 게이트 산화막(106)을 형성하고, 그 상부에 게이트 전극용 폴리실리콘층(108)을 형성한 후, 게이트 전극 패턴용 마스크를 이용한 식각공정을 실시하여 폴리실리콘층(108) 및 게이트 산화막(106)을 순차적으로 패터닝하여 NMOS 영역에는 NMOS 게이트 전극(110)을 형성하고, PMOS 영역에는 PMOS 게이트 전극(112)을 형성한다.Referring to FIG. 2, the gate oxide film 106 is formed on the entire structure, the polysilicon layer 108 for the gate electrode is formed thereon, and then an etching process using a mask for the gate electrode pattern is performed to polysilicon. The layer 108 and the gate oxide film 106 are sequentially patterned to form the NMOS gate electrode 110 in the NMOS region, and the PMOS gate electrode 112 in the PMOS region.
도 3 및 도 4를 참조하면, NMOS 영역을 개방하는 포토레지스트 패턴(PR1)을 형성한 후, 'n-' 이온 주입 공정을 실시하여 NMOS 영역의 P-웰에 얕은 접합영역(Shallow junction)인 저농도 접합영역(114)을 형성한다. 이어서, PMOS 영역을 개방하는 포토레지스트 패턴(PR2)을 형성한 후,'p-' 이온 주입 공정을 실시하여 PMOS 영역의 N-웰에 얕은 접합영역인 저농도 접합영역(116)을 형성한다.3 and 4, after forming a photoresist pattern (PR1) for releasing the NMOS region, - an ion implantation process conducted by the shallow junction regions (Shallow junction) on the P- well of the NMOS area 'n' The low concentration junction region 114 is formed. Then, after forming a photoresist pattern for releasing the PMOS region (PR2), 'p -' subjected to the ion implantation process to form a shallow junction regions in the N- well region of the PMOS lightly doped junction region 116.
도 5를 참조하면, 스페이서 형성용 절연막의 증착 및 식각공정을 실시하여 NMOS 게이트 전극(110) 및 PMOS 게이트 전극(112)의 측벽에 스페이서(118)를 형성한다.Referring to FIG. 5, a spacer 118 is formed on sidewalls of the NMOS gate electrode 110 and the PMOS gate electrode 112 by performing a deposition and etching process of an insulating film for forming a spacer.
도 6을 참조하면, NMOS 영역을 개방하는 포토레지스트 패턴(PR3)을 형성한 후, 'n+' 이온 주입 공정을 실시하여 NMOS 영역의 P-웰에 깊은 접합영역(Deepjunction)인 고농도 접합영역(120)을 형성한다.Referring to FIG. 6, after forming the photoresist pattern PR3 that opens the NMOS region, a 'n + ' ion implantation process is performed to form a high concentration junction region, which is a deep junction region (Deepjunction) in the P-well of the NMOS region. 120).
도 7을 참조하면, PMOS 영역을 개방하는 포토레지스트 패턴(PR4)을 형성한 후, 'p+' 이온 주입 공정을 실시하여 PMOS 영역의 N-웰에 깊은 접합영역인 고농도 접합영역(122)을 형성한다.Referring to FIG. 7, after forming the photoresist pattern PR4 that opens the PMOS region, a 'p + ' ion implantation process is performed to form the high concentration junction region 122, which is a deep junction region in the N-well of the PMOS region. Form.
이로써, NMOS 영역의 P-웰에는 저농도 접합영역(114) 및 고농도 접합영역(120)으로 이루어진 NMOS 소오스/드레인 영역이 형성되고, PMOS 영역의 N-웰에는 저농도 접합영역(116) 및 고농도 접합영역(122)으로 이루어진 PMOS 소오스/드레인 영역이 형성된다.As a result, an NMOS source / drain region including a low concentration junction region 114 and a high concentration junction region 120 is formed in the P-well of the NMOS region, and a low concentration junction region 116 and a high concentration junction region are formed in the N-well of the PMOS region. A PMOS source / drain region consisting of 122 is formed.
도 8 및 도 9를 참조하면, 전체 결과물 상부에 코발트막(124)를 증착한 후, 코발트막(124) 상부에 갭핑막(126)을 형성한다. 이때, 갭핑막(126)은 후속의 코발트 실리사이드막 형성 공정전에 코발트막(124)이 오염되는 것을 방지하기 위하여 티타늄(Ti)막, 티타늄 질화막(TiN) 또는 이들의 조합막으로 형성한다.8 and 9, after the cobalt film 124 is deposited on the entire product, the gapping film 126 is formed on the cobalt film 124. In this case, the gapping film 126 is formed of a titanium (Ti) film, a titanium nitride film (TiN), or a combination thereof in order to prevent the cobalt film 124 from being contaminated before the subsequent cobalt silicide film forming process.
이어서, RTP(Rapid Thermal Process) 방식으로 제1 열처리 공정을 실시하여 NMOS 영역과 PMOS 영역의 고농도 접합영역(120 및 122)과 게이트 전극(110 및 112) 상에 코발트 실리사이드막(CoSi; 128)을 형성한다. 상기 제1 열처리 공정은 400 내지 650℃ 정도의 온도에서 실시하는 것이 바람직하다.Subsequently, a first heat treatment process is performed using a rapid thermal process (RTP) method to form a cobalt silicide layer (CoSi) 128 on the high-concentration junction regions 120 and 122 of the NMOS region and the PMOS region and the gate electrodes 110 and 112. Form. It is preferable to perform the said 1st heat processing process at the temperature of about 400-650 degreeC.
이어서, 소정의 세정공정을 실시하여 잔류하는 미반응 캡핑막(126) 및 코발트막(124)을 선택적으로 제거한다. 미반응된 캡핑막(126) 및 코발트막(124)은 SC-1 용액(Standard Cleaning-1 용액; NH4OH, H2O2및 H2O가 혼합된 용액)과 SC-2용액(Standard Cleaning-2 용액; HCl, H2O2및 H2O가 혼합된 용액)을 사용하여 제거할 수 있다.Subsequently, a predetermined washing process is performed to selectively remove the remaining unreacted capping film 126 and the cobalt film 124. The unreacted capping film 126 and the cobalt film 124 are composed of an SC-1 solution (Standard Cleaning-1 solution; a mixture of NH 4 OH, H 2 O 2 and H 2 O) and an SC-2 solution (Standard Cleaning-2 solution; a mixture of HCl, H 2 O 2 and H 2 O) can be removed.
도 10을 참조하면, RTP 방식으로 제2 열처리 공정을 실시하여 코발트 실리사이드막(CoSi; 128)을 상변이 시켜 코발트 살리사이드막(CoSi2; 128a)을 형성한다. 상기 제2 열처리 공정은 700 내지 850℃ 정도의 온도에서 실시하는 것이 바람직하다.Referring to FIG. 10, a cobalt silicide layer (CoSi 2 ; 128a) is formed by phase shifting a cobalt silicide layer (CoSi) 128 by performing a second heat treatment process using an RTP method. It is preferable to perform the said 2nd heat processing process at the temperature of about 700-850 degreeC.
도 11 및 도 12를 참조하면, 전체 결과물 상부에 티타늄막(130)을 증착한다. 이어서, RTP(Rapid Thermal Process) 방식으로 제3 열처리 공정을 실시하여 코발트 실리사이드막(128a) 상에 티타늄 실리사이드막(C49-TiSi2; 132)을 형성한다. 상기 제3 열처리 공정은 600 내지 750℃ 정도의 온도에서 실시하는 것이 바람직하다.11 and 12, the titanium film 130 is deposited on the entire resultant. Subsequently, a third heat treatment process is performed by a rapid thermal process (RTP) method to form a titanium silicide film (C49-TiSi 2 ; 132) on the cobalt silicide film 128a. It is preferable to perform the said 3rd heat processing process at the temperature of about 600-750 degreeC.
다음에, 소정의 세정공정을 실시하여 잔류하는 미반응 티타늄막(130)을 선택적으로 제거한다. 미반응된 티타늄막(130)은 SC-1 용액을 사용하여 제거할 수 있다.Next, a predetermined washing process is performed to selectively remove the remaining unreacted titanium film 130. The unreacted titanium film 130 may be removed using an SC-1 solution.
도 13을 참조하면, RTP 방식으로 제4 열처리 공정을 실시하여 티타늄 실리사이드막(C49-TiSi2; 132)을 상변이 시켜 티타늄 살리사이드막(C54-TiSi2; 132a)을 형성한다. 상기 제4 열처리 공정은 700 내지 850℃ 정도의 온도에서 실시하는 것이 바람직하다. 티타늄 실리사이드막(132a)이 C54 상(Phase)인 경우에는 면저항(Rs)에서 코발트 실리사이드막(128a)과 큰 차이가 없어 소자 특성에 미치는 영향은 거의 없다.Referring to FIG. 13, the titanium silicide layer C49-TiSi 2 132 is phase-shifted to form a titanium salicide layer C54-TiSi 2 132a by performing a fourth heat treatment process using an RTP method. The fourth heat treatment step is preferably carried out at a temperature of about 700 to 850 ℃. In the case where the titanium silicide layer 132a is in the C54 phase, there is no significant difference in the sheet resistance Rs from the cobalt silicide layer 128a, and thus there is little effect on the device characteristics.
도 14를 참조하면, 티타늄 실리사이드막(132a)이 형성된 실리콘 기판(102) 상에 후속 BLC(Bit Line Contact) 공정을 위하여 LPCVD(Low Plesure Chemcial Vapor Deposition) 공정을 실시하여 질화막(134)과 층간절연막(136)을 형성한다. 상기 층간절연막(136) 형성 공정, 즉 층간절연막(136)의 증착 및 어닐링 공정에서 티타늄 실리사이드막(132a) 상에 티타늄 산화막(138)이 10 내지 20Å 정도로 아주 얇게 형성되게 된다. 티타늄 산화막(138)은 코발트 실리사이드막(128a)과 실리콘 기판(100) 계면으로부터 확산되어 오는 실리콘을 차단하여 실리콘과 산소가 반응하는 것을 억제하기 때문에 코발트 실리사이드막(128a)의 이상 산화는 일어나지 않게 된다.Referring to FIG. 14, the nitride film 134 and the interlayer dielectric layer are formed by performing a low CVD chemical vapor deposition (LPCVD) process on a silicon substrate 102 on which the titanium silicide layer 132a is formed for a subsequent bit line contact (BLC) process. 136 is formed. In the process of forming the interlayer dielectric layer 136, that is, the deposition and annealing of the interlayer dielectric layer 136, the titanium oxide layer 138 is formed to be very thin on the titanium silicide layer 132a. Since the titanium oxide film 138 blocks silicon diffused from the interface between the cobalt silicide film 128a and the silicon substrate 100 to suppress the reaction between silicon and oxygen, abnormal oxidation of the cobalt silicide film 128a does not occur. .
도 15를 참조하면, 콘택홀을 정의하는 포토레지스트 패턴(미도시)을 형성한 후, 상기 포토레지스트 패턴을 식각 마스크로 사용하여 층간절연막(136) 및 질화막(134)을 식각하여 콘택홀을 형성한다. 이때, 티타늄 산화막(138)은 10 내지 20Å 정도로 아주 얇게 형성되어 있기 때문에 상기 콘택홀 형성시 콘택 오픈 페일은 발생하지 않는다. 이어서, 상기 콘택홀 내에 도전 물질을 매립하고 평탄화하여 콘택 플러그(140)를 형성한다.Referring to FIG. 15, after forming a photoresist pattern (not shown) defining a contact hole, the interlayer insulating layer 136 and the nitride layer 134 are etched using the photoresist pattern as an etching mask to form a contact hole. do. At this time, since the titanium oxide film 138 is formed to be very thin, about 10 to about 20 kPa, a contact open fail does not occur when the contact hole is formed. Subsequently, a contact plug 140 is formed by filling and planarizing a conductive material in the contact hole.
본 발명에 의한 반도체 소자의 제조방법에 의하면, 코발트 실리사이드막 형성 후, 코발트 실리사이드막 상에 티타늄막을 증착하고 열처리하여 티타늄 실리사이드막을 형성하게 되면 후속 열공정에서 티타늄 실리사이드막 표면 상에 티타늄 산화막이 아주 얇게 형성되며, 상기 티타늄 산화막은 산소와 실리콘의 반응을 억제하여 코발트 실리사이드막이 이상 산화되는 현상을 방지할 수 있다.According to the method of manufacturing a semiconductor device according to the present invention, after the formation of the cobalt silicide film, the titanium film is deposited on the cobalt silicide film and subjected to heat treatment to form the titanium silicide film. The titanium oxide film may be prevented from oxidizing the cobalt silicide layer by inhibiting the reaction between oxygen and silicon.
이상, 본 발명의 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되는 것은 아니며, 본 발명의 기술적 사상의 범위내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능하다.As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to the said embodiment, A various deformation | transformation by a person of ordinary skill in the art within the scope of the technical idea of this invention is carried out. This is possible.
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| JPH08204187A (en) * | 1995-01-30 | 1996-08-09 | Nec Corp | Manufacture of semiconductor device |
| US5937325A (en) * | 1997-11-07 | 1999-08-10 | Advanced Micro Devices, Inc. | Formation of low resistivity titanium silicide gates in semiconductor integrated circuits |
| KR20000021070A (en) * | 1998-09-25 | 2000-04-15 | 김영환 | Method for forming mos transistors |
| KR20030049309A (en) * | 2001-12-14 | 2003-06-25 | 아남반도체 주식회사 | Method for forming a silicide of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7994039B2 (en) | 2008-05-12 | 2011-08-09 | Kabushiki Kaisha Toshiba | Method of fabricating semiconductor device |
| KR101091468B1 (en) * | 2008-05-12 | 2011-12-07 | 가부시끼가이샤 도시바 | Method of fabricating semiconductor device |
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| KR20040003904A (en) | 2004-01-13 |
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