KR100702790B1 - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
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- KR100702790B1 KR100702790B1 KR1020050132298A KR20050132298A KR100702790B1 KR 100702790 B1 KR100702790 B1 KR 100702790B1 KR 1020050132298 A KR1020050132298 A KR 1020050132298A KR 20050132298 A KR20050132298 A KR 20050132298A KR 100702790 B1 KR100702790 B1 KR 100702790B1
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000001020 plasma etching Methods 0.000 claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- 230000009977 dual effect Effects 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 230000000087 stabilizing effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000012528 membrane Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 229920003986 novolac Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000001668 ameliorated effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- Chemical Kinetics & Catalysis (AREA)
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Abstract
본 발명에 따른 반도체 소자 제조방법은, 비아홀(via hole)을 먼저 형성한 후 트렌치(trench)를 형성하는 듀얼 다마신(dual damascene) 공정을 이용한 반도체 소자 제조방법에 있어서, 층간 절연막에 상기 비아홀을 형성하는 단계; 상기 비아홀 위에 상기 트렌치 형성을 위한 포토레지스트 패턴을 형성하는 단계; Xe 가스를 포함하는 플라즈마를 이용하여 RIE(Reactive Ion Etching) 공정을 수행하고 상기 트렌치를 형성하는 단계; 를 포함한다.In the method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device using a dual damascene process of forming a via hole first and then forming a trench, the via hole is formed in an interlayer insulating film. Forming; Forming a photoresist pattern for forming the trench on the via hole; Performing a reactive ion etching (RIE) process using a plasma containing Xe gas and forming the trenches; It includes.
또한 본 발명에 의하면, 상기 RIE 공정은 CF4 가스, Xe 가스, CHF3를 포함하여 수행되며, 상기 CF4 가스는 80sccm±20%, 상기 Xe 가스는 120sccm±20%, 상기 CHF3 가스는 15sccm±20%로 공급된다.In addition, according to the present invention, the RIE process is performed including CF 4 gas, Xe gas, CHF 3 , the CF 4 gas is 80sccm ± 20%, the Xe gas is 120sccm ± 20%, the CHF 3 gas is 15sccm Supplied at ± 20%.
또한 본 발명에 의하면, 상기 RIE 공정을 진행함에 있어, 소스 전력(source power)은 1200W±15%, 바이어스 전력(bias power)은 800W±15%를 인가하며, 압력은 180mT±15%를 인가한다.According to the present invention, in the RIE process, source power is applied at 1200W ± 15%, bias power is applied at 800W ± 15%, and pressure is applied at 180mT ± 15%. .
이와 같은 본 발명에 의하면, 비아홀을 먼저 형성한 후 트렌치를 형성하는 듀얼 다마신 공정에 있어서, 트렌치 프로파일(trench profile)을 개선하고 면 저항(sheet resistance)을 안정화시킬 수 있는 장점이 있다.According to the present invention, in the dual damascene process of forming the via hole first and then forming the trench, there is an advantage of improving the trench profile and stabilizing the sheet resistance.
Description
도 1은 종래 반도체 소자 제조방법에 의하여 제조된 반도체 소자의 문제점을 나타낸 사진.1 is a photograph showing a problem of a semiconductor device manufactured by a conventional semiconductor device manufacturing method.
도 2는 본 발명에 따른 반도체 소자 제조방법을 나타낸 순서도.2 is a flow chart showing a method of manufacturing a semiconductor device according to the present invention.
도 3은 본 발명에 따른 반도체 소자 제조방법을 설명하기 위한 도면.3 is a view for explaining a semiconductor device manufacturing method according to the present invention.
도 4는 본 발명에 따른 반도체 소자 제조방법에 의하여 제조된 반도체 소자의 단면을 개념적으로 나타낸 도면.4 is a view conceptually showing a cross section of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101...SiN 막 103... 제 1 모노실란(Monosilane:SiH4) 막101 ...
105... FSG 막 107... 제 2 모노실란(Monosilane:SiH4) 막105 ...
109... 노보락 수지막 111... BARC 막109 ... Novorak
113... 포토레지스트 패턴113 ... Photoresist Pattern
본 발명은 반도체 소자 제조방법에 관한 것이다.The present invention relates to a semiconductor device manufacturing method.
반도체 소자가 고집적화되어 감에 따라 금속 배선의 폭이 좁아짐과 동시에 다층 구조로 금속 배선이 형성되고, 다층의 금속 배선층을 전기적으로 연결시키기 위해 비아홀(via hole)이 형성된다. As semiconductor devices become highly integrated, metal wires become narrower, metal wires are formed in a multilayer structure, and via holes are formed to electrically connect the multilayer metal wire layers.
그러나, 금속 배선의 폭이 좁아짐에 따라 저항이 증가하기 때문에 저항을 감소시키기 위해 전기 전도도가 상대적으로 우수한 구리가 반도체 소자의 금속 배선에 사용되고 있다. However, since the resistance increases as the width of the metal wiring becomes narrower, copper having excellent electrical conductivity is used for the metal wiring of the semiconductor element in order to reduce the resistance.
구리는 기존의 알루미늄 배선에 비해 낮은 저항을 나타내고, 일렉트로마이그레이션(electromigration) 내성이 우수하나, 기존의 플라즈마 식각으로는 배선을 형성할 수 없기 때문에 다마신(Damascene) 공정으로 층간 절연막에 비아홀 또는 트렌치(trench)를 형성한 후, 전기도금법 등에 의하여 그 내부를 구리로 매립하고 있다. Copper exhibits lower resistance than conventional aluminum wiring and has excellent electromigration resistance. However, since the plasma cannot be formed using conventional plasma etching, copper has a via hole or a trench in the interlayer insulating film by a damascene process. After the trench is formed, the inside of the trench is embedded with copper by an electroplating method or the like.
층간 절연막에 비아홀 및 트렌치를 형성하는 듀얼 다마신 공정 기법은 크게 두 가지 방법으로 나뉘는데, 첫째는 금속 배선용 트렌치를 먼저 형성한 후 금속 배선 간의 전기적 접속을 위한 비아홀을 형성하는 방법이고, 둘째는 비아홀을 먼저 형성한 후 트렌치를 형성하는 방법이다.The dual damascene process for forming via holes and trenches in an interlayer insulating film is largely divided into two methods. First, a trench for metal wiring is formed first, and then a via hole for electrical connection between the metal wirings is formed. It is a method of forming a trench after forming it first.
일반적으로, 비아홀을 먼저 형성한 후에 트렌치를 형성하는 듀얼 다마신 공정에 있어서, RIE 방식을 이용하여 식각을 수행하고 트렌치를 형성한다.In general, in a dual damascene process in which a via hole is first formed and then a trench is formed, etching is performed using an RIE method to form a trench.
이때, RIE 공정을 진행함에 있어 CF4 가스, Ar 가스를 이용하여 160mT에서 공정을 진행한다. 그런데, 이와 같은 RIE 공정이 진행되는 경우에 트렌치 영역에 따라 식각 정도가 다르게 발생되고 있다. 즉 도 1에 나타낸 바와 같이, 두 개의 비아홀이 형성된 경우, 트렌치의 중심 부분은 식각이 상대적으로 적게 발생되고, 트렌치의 끝 영역(비아홀에 인접한 영역)은 식각이 상대적으로 많이 발생된 것을 볼 수 있다. 이에 따라 트렌치가 무덤 형상으로 형성되는 것을 볼 수 있다. 도 1은 종래 반도체 소자 제조방법에 의하여 제조된 반도체 소자의 문제점을 나타낸 사진이다. 이와 같이 트렌치가 무덤 형상으로 형성되는 경우에는 트렌치의 영역에 따라 면 저항(sheet resistance)이 달라지게 되어 안정화되지 못하는 문제점이 있다.At this time, in the RIE process, the process is performed at 160mT using CF 4 gas and Ar gas. However, when the RIE process is performed, the etching degree is different depending on the trench region. That is, as shown in FIG. 1, when two via holes are formed, the center portion of the trench is relatively less etched, and the end region of the trench (the region adjacent to the via hole) is relatively more etched. . Accordingly, it can be seen that the trench is formed in a tomb shape. 1 is a photograph showing a problem of a semiconductor device manufactured by a conventional semiconductor device manufacturing method. As such, when the trench is formed in a tomb shape, sheet resistance may vary depending on the region of the trench, and thus, the trench may not be stabilized.
이러한 원인은 압력이 제일 큰 요인인 것으로 분석되고 있다. 고 압력(예를 들어 대기에 가까운 압력)을 사용하는 경우에 이러한 현상은 개선되는 것으로 보고되고 있다. 하지만 플라즈마 RIE 챔버의 특성상 250mT 이상으로 압력을 제어하는 것은 어려우며, CD(Critical Dimension) 등의 문제로 인하여 압력을 무한정 높일 수도 없는 실정이다.This cause is analyzed to be the biggest factor. It is reported that this phenomenon is ameliorated when using high pressures (eg close to atmospheric pressure). However, it is difficult to control the pressure above 250mT due to the characteristics of the plasma RIE chamber, and due to problems such as CD (Critical Dimension), it is impossible to increase the pressure indefinitely.
본 발명은 비아홀(via hole)을 먼저 형성한 후 트렌치(trench)를 형성하는 듀얼 다마신(dual damascene) 공정에 있어서, 트렌치 프로파일(trench profile)을 개선하고 면 저항(sheet resistance)을 안정화시킬 수 있는 반도체 소자 제조방법을 제공함에 그 목적이 있다.The present invention can improve the trench profile and stabilize the sheet resistance in a dual damascene process in which via holes are first formed and then trenches are formed. It is an object of the present invention to provide a method for manufacturing a semiconductor device.
상기 목적을 달성하기 위하여 본 발명에 따른 반도체 소자 제조방법은, 비아홀(via hole)을 먼저 형성한 후 트렌치(trench)를 형성하는 듀얼 다마신(dual damascene) 공정을 이용한 반도체 소자 제조방법에 있어서, 층간 절연막에 상기 비아홀을 형성하는 단계; 상기 비아홀 위에 상기 트렌치 형성을 위한 포토레지스트 패턴을 형성하는 단계; Xe 가스를 포함하는 플라즈마를 이용하여 RIE(Reactive Ion Etching) 공정을 수행하고 상기 트렌치를 형성하는 단계; 를 포함한다.In the semiconductor device manufacturing method according to the present invention in order to achieve the above object, in the semiconductor device manufacturing method using a dual damascene process of forming a trench (via hole) first to form a trench (trench), Forming the via hole in an interlayer insulating film; Forming a photoresist pattern for forming the trench on the via hole; Performing a reactive ion etching (RIE) process using a plasma containing Xe gas and forming the trenches; It includes.
또한 본 발명에 의하면, 상기 RIE 공정은 CF4 가스, Xe 가스, CHF3를 포함하여 수행되며, 상기 CF4 가스는 80sccm±20%, 상기 Xe 가스는 120sccm±20%, 상기 CHF3 가스는 15sccm±20%로 공급된다.In addition, according to the present invention, the RIE process is performed including CF 4 gas, Xe gas, CHF 3 , the CF 4 gas is 80sccm ± 20%, the Xe gas is 120sccm ± 20%, the CHF 3 gas is 15sccm Supplied at ± 20%.
또한 본 발명에 의하면, 상기 RIE 공정을 진행함에 있어, 소스 전력(source power)은 1200W±15%, 바이어스 전력(bias power)은 800W±15%를 인가하며, 압력은 180mT±15%를 인가한다.According to the present invention, in the RIE process, source power is applied at 1200W ± 15%, bias power is applied at 800W ± 15%, and pressure is applied at 180mT ± 15%. .
이와 같은 본 발명에 의하면, 비아홀(via hole)을 먼저 형성한 후 트렌치(trench)를 형성하는 듀얼 다마신(dual damascene) 공정에 있어서, 트렌치 프로파일(trench profile)을 개선하고 면 저항(sheet resistance)을 안정화시킬 수 있는 장점이 있다.According to the present invention, in the dual damascene process of forming a via hole first and then forming a trench, the trench profile is improved and sheet resistance is improved. There is an advantage that can be stabilized.
이하, 첨부된 도면을 참조하여 본 발명에 따른 실시 예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명에서는 두 개의 비아홀(via hole)을 먼저 형성한 후 트렌치(trench)를 형성하는 듀얼 다마신(dual damascene) 공정을 이용한 반도체 소자 제조방법에 있어서, 두 개의 비아홀 사이의 트렌치 영역을 평탄한 형상으로 균일하게 식각할 수 있는 방안을 제시하고자 한다. In the present invention, in the method of manufacturing a semiconductor device using a dual damascene process in which two via holes are first formed and then trenches are formed, the trench regions between the two via holes are formed in a flat shape. The purpose of this paper is to suggest a method for uniform etching.
도 2는 본 발명에 따른 반도체 소자 제조방법을 나타낸 순서도이다.2 is a flowchart illustrating a method of manufacturing a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자 제조방법에 의하면, 도 2에 나타낸 바와 같이, 층간 절연막에 비아홀을 형성하고(단계 210), 상기 비아홀 위에 트렌치 형성을 위한 포토레지스트 패턴을 형성한다(단계 220). According to the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 2, via holes are formed in the interlayer insulating film (step 210), and photoresist patterns for trench formation are formed on the via holes (step 220).
이러한 공정의 하나의 예를 도 3을 참조하여 간략하게 설명하기로 한다. 도 3은 본 발명에 따른 반도체 소자 제조방법을 설명하기 위한 도면이다.One example of such a process will be briefly described with reference to FIG. 3. 3 is a view for explaining a method of manufacturing a semiconductor device according to the present invention.
먼저 SiN 막(101), 제 1 모노실란(Monosilane:SiH4) 막(103), FSG 막(105), 제 2 모노실란(Monosilane:SiH4) 막(107)을 적층 형성한다. 그리고, 상기 FSG 막(105)과 상기 제 2 모노실란(Monosilane:SiH4) 막(107)을 관통하는 비아홀을 형성한다. 이어서 상기 비아홀을 노보락(novolac) 수지막(109)으로 채우는 공정이 수행된다. First, a SiN
상기 노보락 수지막(109)은 추후 진행될 트렌치 형성 공정에서 상기 SiN 막(101)이 손상되는 것을 방지하기 위하여 형성된 것이다. 상기 SiN 막(101)이 손상되는 경우에는 그 하부에 있는 금속층(예컨대 구리)이 노출될 수 있게 되며, 확산에 의한 각종 결함이 발생될 수 있기 때문이다.The novolak
상기 결과물 위에 BARC 막(111)을 형성하고, RIE(Reactive Ion Etching) 공정을 위한 포토레지스트 패턴(113)을 형성한다. A BARC
이어서 RIE(Reactive Ion Etching) 공정을 수행하고 트렌치를 형성한다(단계 230).A reactive ion etching (RIE) process is then performed and trenches are formed (step 230).
여기서 상기 RIE(Reactive Ion Etching) 공정은 Xe 가스를 포함하는 플라즈 마를 이용하여 수행하고 도 4에 나타낸 바와 같은 트렌치를 형성할 수 있게 된다. 도 4는 본 발명에 따른 반도체 소자 제조방법에 의하여 제조된 반도체 소자의 단면을 개념적으로 나타낸 도면이다.The reactive ion etching (RIE) process may be performed using a plasma including Xe gas and form a trench as shown in FIG. 4. 4 is a view conceptually showing a cross section of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자 제조방법에 의하면, 도 4에 나타낸 바와 같이, 트랜치(409)가 평탄한 형상으로 제조될 수 있으며, 균일한 면 저항(sheet resistance) 특성을 제공할 수 있게 된다. 도 4에 나타낸 반도체 소자는 하부 배선(401)과 상부 배선(403) 사이에 두 개의 비아홀(405)이 형성된 경우를 나타낸 것이다. 도면부호 407은 층간 절연층을 나타낸다.According to the semiconductor device manufacturing method according to the present invention, as shown in Figure 4, the
본 발명에 의하면 종래의 Ar 가스 대신에 Xe 가스를 사용하여 RIE를 수행함으로써, 상기 트렌치(409) 영역의 프로파일을 평탄하게 개선할 수 있게 된다. 이는 Xe 가스가 Ar 가스보다 입자가 무거워서 평판 식각과 같은 경우 Ar 가스보다 Xe 가스가 훨씬 균일한 식각을 수행할 수 있기 때문이다.According to the present invention, by performing the RIE using Xe gas instead of the conventional Ar gas, the profile of the
본 발명에서는 RIE 공정을 수행함에 있어, CF4 가스, Xe 가스, CHF3를 포함하는 플라즈마를 이용하여 식각 공정을 수행하였다. 또한, RF 전력을 인가함에 있어, 포토레지스트 선택비를 위하여 소스 전력(source power)은 1200W±15%, 바이어스 전력(bias power)은 800W±15%를 인가하였으며, 압력은 180mT±15%를 인가하였다. In the present invention, in performing the RIE process, the etching process was performed using a plasma containing CF 4 gas, Xe gas, CHF 3 . In addition, in applying RF power, a source power of 1200W ± 15%, a bias power of 800W ± 15%, and a pressure of 180mT ± 15% were applied for the photoresist selection ratio. It was.
또한, RIE 공정을 수행함에 있어, CF4 가스는 80sccm으로 공급하였고, Xe 가스는 120sccm으로 공급하였다. 또한 포토레지스트의 특성을 좋게 하기 위하여 CHF3 를 15sccm 첨가하였다.In addition, in performing the RIE process, CF 4 gas was supplied at 80 sccm, and Xe gas was supplied at 120 sccm. In addition, 15 sccm of CHF 3 was added to improve the properties of the photoresist.
본 발명에서는 Ar 가스 대신에 Xe 가스를 사용하여 식각을 수행하였는데, 홀이 아닌 평판의 경우에는 훨씬 균일한 식각량이 발생되며, 이는 마이크로 트렌치 프로파일(micro trench profile)을 개선하는 중요한 요소가 된다. 이로 인하여 트렌치 형성 공정에 있어 과식각(over etch)량을 줄일 수 있게 된다.In the present invention, etching was performed using Xe gas instead of Ar gas, and in the case of a plate rather than a hole, a much more uniform etching amount is generated, which is an important factor for improving a micro trench profile. This may reduce the amount of overetch in the trench formation process.
또한 기존 트렌치 형성 공정 중에서, 가장 많은 부분을 차지하는 탑 로스(top loss)에 의한 브리지(bridge) 개선도 이룰 수 있게 되며, 안정적인 면 저항(sheet resistance)을 유지하여 소자의 특성도 향상시킬 수 있게 된다.In addition, it is possible to achieve bridge improvement due to the top loss, which occupies the largest portion of the existing trench forming process, and to improve the characteristics of the device by maintaining stable sheet resistance. .
이상의 설명에서와 같이 본 발명에 따른 반도체 소자 제조방법에 의하면, 비아홀(via hole)을 먼저 형성한 후 트렌치(trench)를 형성하는 듀얼 다마신(dual damascene) 공정에 있어서, 트렌치 프로파일(trench profile)을 개선하고 면 저항(sheet resistance)을 안정화시킬 수 있는 장점이 있다.As described above, according to the method of manufacturing a semiconductor device according to the present invention, in a dual damascene process in which a via hole is first formed and then a trench is formed, a trench profile is formed. There is an advantage that can improve and stabilize the sheet resistance (sheet resistance).
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