KR100685600B1 - Method for forming semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In particular, in forming a star asymmetry recess that can solve a short channel effect, characteristics of the device due to a gate lining phenomenon In order to overcome the degradation problem, by forming a recessed region that is not protruding in the center of the active region but increasing the line width of the active region of the region where the recess region is formed, a gate overlapping the recess region is formed in the top-flush. The present invention relates to a method of forming a semiconductor device capable of improving the short channel effect while being affected by the least amount.

Description

Method of forming a semiconductor device {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

1 and 2 are conceptual diagrams illustrating a short channel effect generated by a strong side electric field by an insulating film having a high dielectric constant.

3 to 5 are plan and cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the prior art.

6A through 6C are plan views illustrating a method of forming a STAR gate according to the present invention.

7A to 7F are cross-sectional views illustrating a method of forming a STAR gate according to the present invention.

8 is a cross-sectional view of a STAR gate according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In particular, in forming a STAR gate that can solve a short channel effect, it is possible to overcome the problem of deterioration of device characteristics due to the gate lining phenomenon. The present invention relates to a method of forming a semiconductor device in which a recess region is formed only in a central portion of an active region to form a STAR gate.

One of the most important parameters in the fabrication of transistors is the threshold voltage (Vt). The threshold voltage is a variable that depends on the gate oxide thickness, the channel doping concentration, the oxide charge, and the material used for the gate stack. As the size of the device decreases as the threshold voltage, various phenomena appearing that do not coincide with theoretical values. The problem currently encountered is the short channel effect that occurs as the gate channel length decreases.

As semiconductor devices have been highly integrated, nm-class devices require devices that operate at lower speeds and lower operating voltages of 1 to 2V, and therefore require lower voltages.

However, due to the short channel effect, the threshold voltage is lowered, making the device uncontrollable.

In particular, while using a material having a high-k dielectric constant to prevent breakdown of the gate, the short channel effect is becoming more problematic.

1 and 2 are conceptual diagrams illustrating a short channel effect generated by a strong side electric field by an insulating film having a high dielectric constant.

FIG. 1 illustrates a drain induced built-in leakage (DIBL) phenomenon due to a short channel effect, and FIG. 2 illustrates a strong electric field generated by a high dielectric constant. (Reference: Design Considerations of High-K Gate Dielectrics and Metal Gate Electrodes for Sub-0.1 um MOSFETs
Cheng, B .; Cao, M .; Voode, PV; Greene, W .; Stork, H .; Yu, Z .; Woo, JCS
Solid-State Device Research Conference, 1998. Proceeding of the 28th European Volume, Issue, 8-10 September 1998 Page (s): 308-311)

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In order to reduce the short channel effect, various researches are underway, but the solution to satisfy this problem is still incomplete due to the high integration of semiconductor devices.

The current direction is to find a solution by adjusting the doping concentration, but this is not the solution for the ultimate short channel effect. Currently known research methods include super steep retrograde channels (SSRs), near ion implant channels (Vertically Abrupt Channel Doping), and ion implant channels (laterally abrupt channel doping). A method of forming a recessed-channel through a channel, a method of forming a channel having a halo structure through a large angle tilt implant, and the like has been studied.

However, the reduction of the short channel effect through the gate oxide thickness and the channel concentration has a fundamental limitation.

Recently, in order to overcome fundamental limitations, the channel length can be increased with the STAR gate.

3 to 5 are plan views and cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the prior art.

FIG. 3 is a plan view illustrating an exposure mask having a chrome pattern formed on a quartz substrate, and illustrates a STAR gate mask 20 having a chrome pattern 15 as a light shielding pattern formed at a portion constituting a protrusion in a process of forming a STAR gate. will be.

In this case, the protrusion is formed over two gate bottoms passing through the active region.

4 is a plan view illustrating a protrusion and a gate formed on a semiconductor substrate by using the exposure mask of FIG. 3, and FIG. 5 is a cross-sectional view taken along a ⓑ-ⓑ direction of FIG. 4.

4 and 5, a trench type isolation layer 35 defining an active region 30 is formed on a semiconductor substrate. In this case, the trench type isolation layer 35 may form a pad insulating film (not shown) on the semiconductor substrate 10 and etch the pad insulating film and the semiconductor substrate having a predetermined thickness by a photolithography process using a device isolation mask. It is formed by forming a field oxide film filling the gap and removing the pad insulating film.

Next, the protrusion 25 passing through the active region 30 and the device isolation region is formed by a photolithography process using the STAR gate mask of FIG. 3. In this case, the photolithography process is performed using a negative photosensitive film.

Then, the gate oxide film 40, the gate silicon 45, the high melting point metal layer 50, and the hard mask layer 55 are laminated on the entire surface. In this case, the gate silicon 45 is formed in an amorphous form and then heat treated, and the high melting point metal layer 50 is formed of a tungsten silicide layer, and the hard mask layer 55 is formed of a silicon nitride film. It is.

Next, the gate 65 is formed by patterning by a photolithography process using a gate mask (not shown).

In this case, the gate 65 is formed to span the protrusion 25, and each protrusion 25 is provided in each of the device isolation region and the active region 30 in which the device isolation film is formed in the long axis direction of the active region 30. ) Is formed in such a way that the bottom of the two gates 65 spans.

Finally, an insulating film spacer 60 is formed on the sidewall of the gate 65. In this case, the insulating film spacer 60 is formed by depositing a nitride film on the entire surface and anisotropic etching it.

As described above, the method of forming a semiconductor device according to the related art has a problem due to the short channel effect, and the short channel effect can be overcome by forming a STAR gate to increase the channel length, but the active region of the portion to be etched. In the upper gate, the round top-flush is destroyed and the gate tilts. Accordingly, there is a problem in that a characteristic of a semiconductor device is deteriorated due to a lining phenomenon in which gates at edge portions of an active region are leaned against each other.

In order to solve the above-mentioned problems of the prior art, the shape of the STAR gate is modified to form a recessed region that is not protruding in the center of the active region, but the line width of the active region of the region where the recessed region is formed. The purpose of the present invention is to provide a method of forming a semiconductor device in which a gate overlapping the recess region can be improved while the short channel effect is minimized while the gate overlapped with the recess region is minimized.

The method for forming a semiconductor device according to the present invention for achieving the above object,
A semiconductor substrate comprising a recess region for forming a star asymmetry recess (STAR) gate in a central portion of an active region arranged in an island shape.
Forming an active region in which a line width of a central portion of the active region, which is predetermined as the recess region, is defined to be larger than a line width of both edge portions of the active region;
Etching a semiconductor substrate for forming the STAR gate to form a recess region; And
A gate overlapping the active region and the recess region is formed, and a line width of the gate overlapping with both edge portions of the active region is formed to be smaller than a line width of another portion, such that a concave portion is included in the line width of the gate. It is characterized by that.

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Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

6A through 6C are plan views illustrating a method of forming a STAR gate according to the present invention.

Referring to FIG. 6A, an active region 130 having a line width at the center of the active region 130 defined as the recess region 125 on the semiconductor substrate 100 is greater than the line widths of other portions of the active region 130, that is, both edge portions. ). In this case, the center portion of the active region 130 refers to a bit line contact scheduled region, and when viewed in plan view, the center portion of the active region is convex, so that the shape of the active region is a galaxy shape.

Referring to FIG. 6B, a recessed region of the active region 130 is etched to form a recessed region 125 for forming a STAR gate. In this case, the recess region 125 for forming the STAR gate preferably includes a bit line contact predetermined region, which is the center of the active region 130, and a semiconductor substrate adjacent thereto.

Referring to FIG. 6C, the gate 165 overlapping with the recess region 125 for forming the STAR gate is formed, but the line width of the gate 165 overlapping with both edge portions of the edge portion of the active region 130 is different. It is formed smaller than the line width of the part. In this case, the range of the recess region 125, which is the active region 130 overlapping with the gate 165, may be an extended region from the bit line contact region to the center of the gate 165.

7A to 7F are cross-sectional views illustrating a method of forming a STAR gate according to the present invention.

Referring to FIG. 7A, a trench type isolation layer 135 defining an active region 130 is formed on the semiconductor substrate 100. In this case, the trench type isolation layer 135 may form a pad insulating film (not shown) on the semiconductor substrate 100 and etch the pad insulating film and the semiconductor substrate having a predetermined thickness by a photolithography process using a device isolation mask. It is formed by forming a field oxide film filling the gap and removing the pad insulating film. Here, the active region 130 is formed so that the line width of the active region 130 of the region to be recessed for the subsequent formation of the STAR gate is thicker than the line width of the edge portion of the active region 130. This is a method for increasing the contact area between the gate 165 and the active region 130 to improve the electrical characteristics of the gate 165 as well as to secure a wide bit line contact region.

Next, a buffer oxide layer 110 is formed on the surface of the active region 130, and well ion implantation and channel ion implantation processes are performed.                     

Referring to FIG. 7B, after the anti-reflection film 115 is formed on the entire surface of the semiconductor substrate 100, the photoresist pattern 120 may be formed to etch only the center portion of the active region 130 for the STAR gate structure according to the present invention. do.

Referring to FIG. 7C, in the photolithography process using the photoresist pattern 120, the center portion of the active region 130 and the peripheral device isolation region are etched to form a recessed region, and the anti-reflection film 115 is removed.

Referring to FIG. 7D, the buffer oxide layer 110 is removed to form the gate 165 stack structure.

Referring to FIG. 7E, the gate oxide layer 140, the gate silicon 145, the high melting point metal layer 150, and the hard mask layer 155 are stacked on the entire surface. In this case, the gate silicon 145 is formed in an amorphous form and then heat treated, and the high melting point metal layer 150 is formed of a tungsten silicide layer, and the hard mask layer 155 is formed of a silicon nitride film. will be.

Referring to FIG. 7F, the gate 165 is formed by patterning a photolithography process using a gate mask (not shown). In this case, the gate overlapping with the active region 130 is formed, and the line width of the gate 165 overlapping with both edge portions of the active region 135 is smaller than the line width of other portions. That is, a portion of the gate 165 adjacent to both edge portions of the active region 130 is formed to be concave. If the line width of the gate 165 is deformed in this way, it is formed at both ends of the active region 130. It is possible to secure the area of the storage node contact to be as wide as possible, and to prevent the gate 165 from being inclined due to the change of the top plug.

8 is a cross-sectional view of the STAR gate according to the present invention, and shows a cross section taken along the line ⓒ- © of FIG. 6C.

Referring to FIG. 8, the bit line contact predetermined region is recessed, and a region 170 in which boron ions are diffused by a subsequent C-halo ion implantation process is included.

As described above, the method for forming a semiconductor device according to the present invention forms an active region having a central convex shape for the main purpose of modifying the shape of the STAR gate, and a recess region for forming the STAR gate at the central portion of the active region. And forming a concave portion in the line width of the gate, thereby forming a STAR gate which is not affected by the top-flush and at the same time forms a STAR gate capable of overcoming the short channel effect. Therefore, the present invention increases the process margin for forming a highly integrated semiconductor device, and provides an effect of improving the electrical characteristics and the refresh characteristics of the semiconductor device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (1)

A semiconductor substrate comprising a recess region for forming a star asymmetry recess (STAR) gate in a central portion of an active region arranged in an island shape. Forming an active region in which a line width of a central portion of the active region, which is predetermined as the recess region, is defined to be larger than a line width of both edge portions of the active region; Etching a semiconductor substrate for forming the STAR gate to form a recess region; And A gate overlapping the active region and the recess region is formed, and a line width of the gate overlapping with both edge portions of the active region is formed to be smaller than a line width of another portion, such that a concave portion is included in the line width of the gate. Method for forming a semiconductor device, characterized in that.

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