[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

KR100664339B1 - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

Info

Publication number
KR100664339B1
KR100664339B1 KR1020000086038A KR20000086038A KR100664339B1 KR 100664339 B1 KR100664339 B1 KR 100664339B1 KR 1020000086038 A KR1020000086038 A KR 1020000086038A KR 20000086038 A KR20000086038 A KR 20000086038A KR 100664339 B1 KR100664339 B1 KR 100664339B1
Authority
KR
South Korea
Prior art keywords
metal
hard mask
forming
film
metal film
Prior art date
Application number
KR1020000086038A
Other languages
Korean (ko)
Other versions
KR20020056637A (en
Inventor
이성권
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020000086038A priority Critical patent/KR100664339B1/en
Publication of KR20020056637A publication Critical patent/KR20020056637A/en
Application granted granted Critical
Publication of KR100664339B1 publication Critical patent/KR100664339B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 금속 배선간의 중간에 에어 갭을 효과적으로 형성하도록 한 반도체 소자의 금속배선 형성방법에 관한 것으로서, 반도체 기판상에 금속막, 베리어 금속막, 하드 마스크층을 차례로 형성하는 단계와, 상기 하드 마스크층을 경사 식각하여 메사 구조를 갖는 하드 마스크 패턴을 형성하는 단계와, 상기 하드 마스크 패턴을 마스크로 이용하여 상기 베리어 금속막 및 금속막을 선택적으로 제거하여 일정한 간격을 갖는 금속 배선을 형성하는 단계와, 상기 금속 배선을 포함한 반도체 기판의 전면에 PECVD법으로 층간 절연막을 형성함과 동시에 상기 금속 배선 사이에 에어 갭을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The present invention relates to a method for forming a metal wiring of a semiconductor device to effectively form an air gap between metal wirings, the method comprising: sequentially forming a metal film, a barrier metal film, and a hard mask layer on a semiconductor substrate; Forming a hard mask pattern having a mesa structure by obliquely etching the layer, selectively removing the barrier metal film and the metal film by using the hard mask pattern as a mask to form metal wires having a predetermined interval; And forming an air gap between the metal wires and forming an interlayer insulating film on the entire surface of the semiconductor substrate including the metal wires by PECVD.

에어 갭, 캐패시턴스, 층간 절연막, 금속 배선Air Gap, Capacitance, Interlayer Insulation, Metal Wiring

Description

반도체 소자의 금속배선 형성방법{method for forming metal line of semiconductor device}Method for forming metal line of semiconductor device

도 1a 내지 도 1c는 종래의 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method of forming metal wirings in a conventional semiconductor device.

도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도2A through 2D are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 금속막21 semiconductor substrate 22 metal film

23 : 베리어 금속막 24 : 하드 마스크층23: barrier metal film 24: hard mask layer

25 : 감광막 26 : 층간 절연막25 photosensitive film 26 interlayer insulating film

27 : 에어 갭27: air gap

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 다층 금속배신서 배선간 캐패시턴스(capacitance)를 줄이는데 적당한 반도체 소자의 금속배선 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device suitable for reducing capacitance between wirings of a multi-layer metal distribution box.                         

반도체 소자의 집적도가 증가함에 따라, 다층 금속 배선을 가지는 소자의 구조가 필요하게 되고, 또한 동일 층상에 있어서 금속 배선 사이의 간격이 점차 좁아지게 되었다. As the integration degree of a semiconductor element increases, the structure of the element which has a multilayer metal wiring becomes necessary, and also the space | interval between metal wiring on the same layer became narrow gradually.

이에 따라, 동일층상에서 서로 인접한 금속 배선 사이 또는 상하로 인접한 각 금속배선 사이에 존재하는 기생 저항(Parasitic resistance) 및 기생 캐패시턴스(Parasitic capacitance)가 가장 중요한 문제로 대두된다. Accordingly, parasitic resistance and parasitic capacitance existing between metal wires adjacent to each other on the same layer or between metal wires adjacent to each other up and down become the most important problems.

초고집적 반도체 소자에 있어서, 다층 금속 배선 구조에 존재하는 기생 저항 및 기생 캐패시턴스 성분들은 RC 에 의해 유도되는 지연(Delay)에 의하여 소자의 전기적 특성(Performance)을 열화시키고, 더 나아가 반도체 소자의 전력 소모량을 증가시키고 신호 누설량 또한 증가시킨다. In the highly integrated semiconductor device, the parasitic resistance and parasitic capacitance components present in the multilayer metal wiring structure degrade the electrical performance of the device due to the delay induced by RC, and further, the power consumption of the semiconductor device. Increases the signal leakage.

따라서, 초고집적 반도체 소자에 있어서 RC 값이 작은 다층 금속 배선 기술을 개발하는 것이 매우 중요한 문제이다. Therefore, it is very important to develop a multilayer metal wiring technology having a small RC value in an ultra-high density semiconductor device.

상기 RC 값이 작은 고성능의 다층 금속 배선 구조를 형성하기 위해서는 비저항이 낮은 금속을 사용하여 배선층을 형성하거나, 유전율이 낮은 절연막을 사용할 필요가 있다. In order to form a high performance multilayer metal wiring structure having a small RC value, it is necessary to form a wiring layer using a metal having a low specific resistance or to use an insulating film having a low dielectric constant.

최근 들어서, 에어 갭(Air gap)으로 층간 절연막을 대체하려는 시도가 많이 되고 있다. 그 이유는 공기의 유전율이 1로써 그 값이 매우 작기 때문이다. Recently, many attempts have been made to replace an interlayer insulating film with an air gap. The reason is that the air permittivity is 1, which is very small.

따라서, 에어 갭을 사용하면 초 고집적 반도체 소자에 있어서 다층 콘택 구조에서 발생하는 기생 캐패시턴스를 확실히 줄일 수 있게 된다.Therefore, the use of the air gap can reliably reduce the parasitic capacitance generated in the multilayer contact structure in the ultra-high density semiconductor device.

한편, 종래 기술은 SOVT 1998년 학회(P46)의 논문에서 발표한 내용으로 층간 절연막을 증착할 때 단차 피복성(step coverage)이 불량한 PECVD(Plasma Enhanced Chemical Vapor Deposition)법으로 제 1 층간 절연막을 증착하고, 단차 피복성이 우수한 HDP(High Density Plasma) CVD(Chemical Vapor Deposition)법으로 제 2 층간 절연막을 형성하는 등의 2중 증착으로 에어 갭(air gap)을 형성하여 금속 배선간 캐패시턴스를 낮추고 있다.On the other hand, the prior art is the information published in the paper of the SOVT 1998 Society (P46), the first interlayer insulating film is deposited by the Plasma Enhanced Chemical Vapor Deposition (PECVD) method, which has poor step coverage when the interlayer insulating film is deposited. In addition, an air gap is formed by double deposition such as forming a second interlayer insulating film by HDP (High Density Plasma) chemical vapor deposition (CVD) method having excellent step coverage, thereby reducing capacitance between metal wirings. .

이하, 첨부된 도면을 참고하여 반도체 소자의 금속배선 형성방법을 설명하면 다음과 같다.Hereinafter, a metal wiring forming method of a semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1c는 종래의 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming metal wirings in a conventional semiconductor device.

도 1a에 도시한 바와 같이, 절연막(도시되지 않음)이 형성된 반도체 기판(11)상에 금속막을 증착하고, 포토 및 식각공정을 통해 상기 금속막을 선택적으로 제거하여 일정한 간격을 갖는 금속 배선(12)을 형성한다.As shown in FIG. 1A, a metal film is deposited on a semiconductor substrate 11 on which an insulating film (not shown) is formed, and the metal film 12 is selectively removed by a photo and etching process to remove the metal film. To form.

도 1b에 도시한 바와 같이, 상기 금속 배선(12)을 포함한 반도체 기판(11)의 전면에 피복성(step coverage)이 불량한 PECVD법으로 제 1 층간 절연막(13)을 형성한다.As shown in FIG. 1B, the first interlayer insulating film 13 is formed on the entire surface of the semiconductor substrate 11 including the metal wiring 12 by PECVD with poor step coverage.

여기서 피복성이 불량한 PECVD법으로 제 1 층간 절연막(13)을 형성함으로서 금속 배선(12) 사이에는 에어 갭(Air cap)(14)이 형성된다.Here, the air gap 14 is formed between the metal wirings 12 by forming the first interlayer insulating film 13 by PECVD with poor coating properties.

도 1c에 도시한 바와 같이, 상기 제 1 층간 절연막(13)상에 피복성이 우수한 HDP CVD법으로 제 2 층간 절연막(15)을 형성한다.As shown in Fig. 1C, a second interlayer insulating film 15 is formed on the first interlayer insulating film 13 by the HDP CVD method with excellent coating properties.

이어, 상기 제 2 창간 절연막(15)의 전면에 CMP(Chemical Mechanical Polishing) 공정을 실시하여 표면을 평탄화한다. Subsequently, the surface of the second interlayer insulating layer 15 is subjected to a chemical mechanical polishing (CMP) process to planarize the surface.

그러나 상기와 같은 종래의 반도체 소자의 금속배선 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the above-described conventional method for forming metal wirings of semiconductor devices has the following problems.

첫째, 유전율이 낮은 절연막에 대한 공정 전반에 걸친 연구가 미진한 상태로 낮은 유전율 갖는 절연막의 도입에 따른 제반 연구가 필요하다.First, research on the introduction of an insulating film having a low dielectric constant is required, while the overall process of the insulating film having a low dielectric constant is insufficient.

둘째, 에어 갭을 형성하는 경우 이중의 증착 공정에 의해 그 공정이 복잡하다.Second, when forming an air gap, the process is complicated by a double deposition process.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 금속 배선간의 중간에 에어 갭을 효과적으로 형성하도록 한 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device to effectively form an air gap between metal wirings.

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 금속배선 형성방법은 반도체 기판상에 금속막, 베리어 금속막, 하드 마스크층을 차례로 형성하는 단계와, 상기 하드 마스크층을 경사 식각하여 메사 구조를 갖는 하드 마스크 패턴을 형성하는 단계와, 상기 하드 마스크 패턴을 마스크로 이용하여 상기 베리어 금속막 및 금속막을 선택적으로 제거하여 일정한 간격을 갖는 금속 배선을 형성하는 단계와, 상기 금속 배선을 포함한 반도체 기판의 전면에 PECVD법으로 층간 절연막을 형성함과 동시에 상기 금속 배선 사이에 에어 갭을 형성하는 단계를 포함하여 형성함을 특징으로 한다. Metal wiring formation method of a semiconductor device according to the present invention for achieving the above object is a step of sequentially forming a metal film, a barrier metal film, a hard mask layer on the semiconductor substrate, and by obliquely etching the hard mask layer mesa Forming a hard mask pattern having a structure, selectively removing the barrier metal film and the metal film by using the hard mask pattern as a mask to form a metal wiring having a predetermined gap, and a semiconductor including the metal wiring And forming an air gap between the metal wires and forming an interlayer insulating film on the entire surface of the substrate by PECVD.                     

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 금속배선 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a metal wiring forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.

도 2a에 도시한 바와 같이, 절연막(도시되지 않음)이 형성된 반도체 기판(21)상에 금속막(22)을 증착하고, 상기 금속막(22)상에 베리어 금속막(23)을 형성한다.As shown in FIG. 2A, a metal film 22 is deposited on a semiconductor substrate 21 on which an insulating film (not shown) is formed, and a barrier metal film 23 is formed on the metal film 22.

여기서 상기 금속막(22)은 Al, W, Ti, TiN, W, WN, TiW, TaN 등의 재료를 CVD 또는 PVD법을 통해 증착한다.The metal film 22 may be formed by depositing materials such as Al, W, Ti, TiN, W, WN, TiW, and TaN by CVD or PVD.

이어, 상기 베리어 금속막(23)상에 하드 마스크층(24)을 형성하고, 상기 하드 마스크층(24)상에 감광막(25)을 도포한 후, 노광 및 현상 공정으로 감광막(25)을 패터닝하여 금속배선 영역을 정의한다.Subsequently, a hard mask layer 24 is formed on the barrier metal film 23, the photosensitive film 25 is applied on the hard mask layer 24, and then the photosensitive film 25 is patterned by an exposure and development process. To define the metallization area.

여기서 상기 하드 마스크층(24)은 TEOS, HDP 산화막, PE-SiON, PE 나이트라이드, Al2O3 중에서 적어도 어느 하나를 약 2000Å이하의 두께로 형성한다.The hard mask layer 24 may form at least one of TEOS, HDP oxide, PE-SiON, PE nitride, and Al 2 O 3 to a thickness of about 2000 kPa or less.

한편, 상기 금속막(22)과 하드 마스크층(24)간의 접착력 개선을 위해 베리어 금속막(23)으로 TiN, Ti 등의 재료를 단독 또는 혼용하여 50 ~ 500Å 두께로 형성한다.Meanwhile, in order to improve adhesion between the metal film 22 and the hard mask layer 24, the barrier metal film 23 is formed to have a thickness of 50 to 500 kPa by using a single or mixed material such as TiN or Ti.

도 2b에 도시한 바와 같이, 상기 패터닝된 감광막(25)을 마스크로 이용하여 경사를 갖는 플라즈마 식각을 통해 상기 하드 마스크층(24)을 선택적으로 제거하여 섬 형태의 메사(mesa) 구조를 갖는 하드 마스크 패턴(24a)을 형성한다.As shown in FIG. 2B, the hard mask layer 24 may be selectively removed by an inclined plasma etching using the patterned photoresist 25 as a mask to form a hard mesa structure. The mask pattern 24a is formed.

여기서 상기 하드 마스크층(24)을 플라즈마 식각시 상기 하드 마스크층(24)의 두께 조절을 통해 메사 구조의 식각 프로파일을 원하는 형태로 제어할 수 있으며, 상기 하드 마스크층(24)은 산화막 계통의 재료를 사용함으로서 제거하기 위한 추가 공정이 필요 없게 한다.Here, the etching of the mesa structure can be controlled to a desired shape by controlling the thickness of the hard mask layer 24 during plasma etching of the hard mask layer 24, and the hard mask layer 24 is an oxide-based material. By using an additional process for removal is eliminated.

한편, 상기 하드 마스크층(24)의 마스크로 사용되는 감광막(25)은 하드 마스크층(24)의 식각시 표면으로부터 소정 두께가 식각된다.Meanwhile, the photoresist 25 used as a mask of the hard mask layer 24 is etched from a surface when the hard mask layer 24 is etched.

도 2c에 도시한 바와 같이, 상기 감광막(25)을 제거하고, 상기 하드 마스크층(24)을 마스크로 이용하여 플라즈마 식각을 통해 상기 베리어 금속막(23) 및 금속막(22)을 선택적으로 제거하여 금속 배선(22a)을 형성한다.As shown in FIG. 2C, the barrier metal layer 23 and the metal layer 22 are selectively removed by plasma etching using the hard mask layer 24 as a mask. The metal wiring 22a is formed.

여기서 상기 금속 배선(22a)의 선간 거리/선폭 비를 1/1.5 ~ 1/0.5로 하고 금속 배선(22a)의 두께는 선폭 치수의 2.5 ~ 5배 두껍게 형성한다.Here, the line distance / line width ratio of the metal wire 22a is 1 / 1.5 to 1 / 0.5, and the thickness of the metal wire 22a is 2.5 to 5 times thicker than the line width dimension.

도 2d에 도시한 바와 같이, 상기 금속 배선(22a)을 포함한 반도체 기판(21)의 전면에 PECVD법으로 층간 절연막(26)을 형성하여 상기 금속 배선(22a) 사이에 에어 갭(27)을 형성한다.As shown in FIG. 2D, an interlayer insulating film 26 is formed on the entire surface of the semiconductor substrate 21 including the metal lines 22a by PECVD to form an air gap 27 between the metal lines 22a. do.

여기서 상기 층간 절연막(26)은 USG, PECVD SiO2, HDP SiO2막 등을 2000 ~ 3000Å 두께로 형성한다.In this case, the interlayer insulating layer 26 forms a USG, PECVD SiO 2 , HDP SiO 2 film, or the like in a thickness of 2000 to 3000 Å.

한편, 상기 층간 절연막(26)을 형성하여 금속 배선(22a) 사이에 에어 갭(27)을 형성한 후 평탄화를 위해 CMP 또는 플라즈마 에치백을 실시한다.Meanwhile, the interlayer insulating layer 26 is formed to form an air gap 27 between the metal wires 22a, and then CMP or plasma etchback is performed to planarize.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 금속배선 형성방법은 다음과 같은 효과가 있다.As described above, the metal wiring forming method of the semiconductor device according to the present invention has the following effects.

즉, 금속 배선간에 에어 갭(air gap)을 효과적으로 형성함으로 금속 배선간의 캐패시턴스를 줄이어 반도체 소자의 전기 특성을 향상시킬 수 있다.In other words, by effectively forming an air gap between the metal wires, the capacitance between the metal wires can be reduced, thereby improving the electrical characteristics of the semiconductor device.

Claims (5)

반도체 기판상에 금속막, 베리어 금속막, 하드 마스크층을 차례로 형성하는 단계;Sequentially forming a metal film, a barrier metal film, and a hard mask layer on the semiconductor substrate; 상기 하드 마스크층을 경사 식각하여 메사 구조를 갖는 하드 마스크 패턴을 형성하는 단계;Obliquely etching the hard mask layer to form a hard mask pattern having a mesa structure; 상기 하드 마스크 패턴을 마스크로 이용하여 상기 베리어 금속막 및 금속막을 선택적으로 제거하여 일정한 간격을 갖는 금속 배선을 형성하는 단계;Selectively removing the barrier metal film and the metal film by using the hard mask pattern as a mask to form metal wires having a predetermined interval; 상기 금속 배선을 포함한 반도체 기판의 전면에 PECVD법으로 층간 절연막을 형성함과 동시에 상기 금속 배선 사이에 에어 갭을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 금속배선 형성방법.Forming an interlayer insulating film on the front surface of the semiconductor substrate including the metal wirings by PECVD and simultaneously forming an air gap between the metal wirings. 제 1 항에 있어서, 상기 금속 배선의 선간 거리/선폭 비를 1/1.5 ~ 1/0.5로 하고 금속 배선의 두께는 선폭 치수의 2.5 ~ 5배 두껍게 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.2. The metallization of the semiconductor device as claimed in claim 1, wherein the line-to-line / linewidth ratio of the metallization line is 1 / 1.5 to 1 / 0.5, and the thickness of the metallization line is 2.5 to 5 times the line width dimension. Way. 제 1 항에 있어서, 상기 하드 마스크층은 TEOS, HDP 산화막, PE-SiON, PE 나이트라이드, Al2O3 중에서 적어도 어느 하나를 사용하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the hard mask layer comprises at least one of TEOS, HDP oxide, PE-SiON, PE nitride, and Al 2 O 3 . 제 1 항에 있어서, 상기 베리어 금속막은 TiN, Ti 등의 재료를 단독 또는 혼용하여 50 ~ 500Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.2. The method of claim 1, wherein the barrier metal film is formed to have a thickness of 50 to 500 GPa by using a single material or a mixture of TiN and Ti. 제 1 항에 있어서, 상기 층간 절연막은 USG, PECVD SiO2, HDP SiO2막 등을 2000 ~ 3000Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법. The method of claim 1, wherein the interlayer insulating layer is formed of a USG, PECVD SiO 2 , or HDP SiO 2 film having a thickness of 2000 to 3000 Å.
KR1020000086038A 2000-12-29 2000-12-29 Method for forming metal line of semiconductor device KR100664339B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000086038A KR100664339B1 (en) 2000-12-29 2000-12-29 Method for forming metal line of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000086038A KR100664339B1 (en) 2000-12-29 2000-12-29 Method for forming metal line of semiconductor device

Publications (2)

Publication Number Publication Date
KR20020056637A KR20020056637A (en) 2002-07-10
KR100664339B1 true KR100664339B1 (en) 2007-01-02

Family

ID=27689136

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000086038A KR100664339B1 (en) 2000-12-29 2000-12-29 Method for forming metal line of semiconductor device

Country Status (1)

Country Link
KR (1) KR100664339B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023043505A1 (en) * 2021-09-20 2023-03-23 Sandisk Technologies Llc Semiconductor device containing bit lines separated by air gaps and methods for forming the same
US11984395B2 (en) 2021-09-20 2024-05-14 Sandisk Technologies Llc Semiconductor device containing bit lines separated by air gaps and methods for forming the same
US12096636B2 (en) 2021-09-20 2024-09-17 Sandisk Technologies Llc Semiconductor device containing bit lines separated by air gaps and methods for forming the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100485157B1 (en) * 2002-12-05 2005-04-22 동부아남반도체 주식회사 Multilayer structure of metal line in semiconductor device and formation method thereof
CN103187392B (en) * 2011-12-31 2015-07-08 中芯国际集成电路制造(上海)有限公司 Metal line structure and forming method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023043505A1 (en) * 2021-09-20 2023-03-23 Sandisk Technologies Llc Semiconductor device containing bit lines separated by air gaps and methods for forming the same
US11984395B2 (en) 2021-09-20 2024-05-14 Sandisk Technologies Llc Semiconductor device containing bit lines separated by air gaps and methods for forming the same
US12096636B2 (en) 2021-09-20 2024-09-17 Sandisk Technologies Llc Semiconductor device containing bit lines separated by air gaps and methods for forming the same

Also Published As

Publication number Publication date
KR20020056637A (en) 2002-07-10

Similar Documents

Publication Publication Date Title
US7772112B2 (en) Method of manufacturing a semiconductor device
US6160316A (en) Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths
KR100664339B1 (en) Method for forming metal line of semiconductor device
KR100495857B1 (en) Method of forming multi-layered metal wiring of semiconductor device
US6358845B1 (en) Method for forming inter metal dielectric
KR100772073B1 (en) Method for fabricating metal-insulator-metal capacitor
KR20040049969A (en) Method for forming a metal line in semiconductor device
US6709975B2 (en) Method of forming inter-metal dielectric
KR100578223B1 (en) Method of fabricating of dual damascene of semiconductor device
KR19980025403A (en) Planarization Method of Semiconductor Device
KR20040059466A (en) Method for forming gap fill of metal line for semiconductor
KR100661220B1 (en) Method for forming metal interconnect with dual dielectric layer
KR100459063B1 (en) Method for manufacturing intermetal dielectric layer of semiconductor device
KR20040077307A (en) Method for forming of damascene metal wire
KR100367499B1 (en) Method for manufacturing semiconductor device
KR19990055200A (en) Method of forming inlaid metal wiring
KR100249130B1 (en) Method for forming metal line of semiconductor device
KR100770533B1 (en) Semiconductor device and method for manufacturing the semiconductor device
KR100582372B1 (en) A method for forming damascene type metal wire
KR100244713B1 (en) Method of fabricating semiconductor device
KR100269662B1 (en) Method for manufacturing conductor plug of semiconductor device
KR100359774B1 (en) method for manufacturing of semiconductor device
KR100641488B1 (en) Method for manufacturing contact of the semiconductor device
KR100641484B1 (en) Method for forming a metal line of semiconductor device
KR20040077042A (en) Method for forming of damascene metal wire

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101125

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee