KR100648221B1 - Array substrate manufacturing method of thin film transistor liquid crystal display - Google Patents

Abstract

The present invention discloses a method for manufacturing a thin film transistor liquid crystal display array substrate for reducing the number of masks. The disclosed method includes forming a gate electrode on a transparent insulating substrate; Sequentially depositing a gate insulating film, an a-Si film, an n ⁺ a-Si film, a second metal film, and a protective film on the entire surface of the substrate including the gate electrode; Forming a photoresist pattern on the passivation layer, the photoresist pattern being divided into a first region of a channel portion, a second region of a contact portion, and a third region of a data line portion; Forming a data line in a third region by an etching process using the photoresist pattern; Forming a source / drain electrode in a first region and an active layer in a third region by an etching process using the photoresist pattern; Forming a contact hole in a second region and a channel layer in the first region by an etching process using the photoresist pattern; Removing the remaining photoresist pattern; Depositing and patterning a transparent metal film on the substrate resultant to form a pixel electrode in contact with the source / drain electrodes.

Description

Method for fabricating array substrate of TFT-LCD

1A to 1I are cross-sectional views illustrating a method of manufacturing an array substrate according to the related art.

2A to 2J are cross-sectional views illustrating a method of manufacturing an array substrate according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

21 glass substrate 22 gate electrode

23: gate insulating film 24: a-Si layer

25: n ⁺ a-Si layer 26: metal film for source / drain electrodes

27a, 27b: photosensitive film 28: protective film

29: ITO film 29a: pixel electrode

The present invention relates to a method of manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for reducing the number of masks.

Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, a TFT LCD equipped with a thin film transistor (TFT) as a switching element for independently controlling the driving of each pixel is comparable to a CRT because of its advantages of high-speed response characteristics and its suitability for high pixel numbers. It is greatly contributing to the realization of high quality screen, large size, and color.

Such a TFT LCD generally includes an array substrate on which TFTs and pixel electrodes are formed, a color filter substrate on which color filters and counter electrodes are formed, and a liquid crystal layer interposed between the substrates.

On the other hand, in manufacturing the TFT LCD of the above structure, it is very important to reduce the number of manufacturing process of the array substrate, that is, the number of etching masks. This is to lower the manufacturing cost, and at this point a four-mask process is proposed.

1A to 1J are cross-sectional views illustrating a method of manufacturing an array substrate using a 4-mask process according to the prior art.

Referring to FIG. 1A, a gate metal film is deposited on a transparent insulating substrate, for example, a glass substrate 11, and then the gate metal film is patterned by a first mask process to form a gate electrode 12. Then, the gate insulating layer 13 is coated on the entire surface of the glass substrate 11 so that the gate electrode 12 is covered. An undoped amorphous silicon layer 14 (hereinafter referred to as an a-Si layer) and a doped amorphous silicon layer (hereinafter referred to as an n ⁺ a-Si layer) for forming an ohmic layer are formed on the gate insulating layer 13. ), And the metal film 16 for forming the source / drain electrodes is formed in this order.

Referring to FIG. 1B, a photoresist film is coated on the metal layer 16 and a second mask process is performed to divide the photoresist pattern 17a into a first region of the channel portion, a second region of the contact portion, and a third region of the data line portion. To form. In this case, the photoresist pattern may have a 1/3 thickness photoresist on the passivation layer in the first region, the photoresist layer remains on the passivation layer in the second region, and the photoresist layer does not remain in the third region. Pattern.

Referring to FIG. 1C, only the source / drain metal film 16 of the third region for forming the data line is etched.

Referring to FIG. 1D, a first ashing process is performed on the entire surface of the substrate to expose the metal film 16 of the first region.

Referring to FIG. 1E, the n ⁺ a-Si layer 15 forming the channel layer in the first region is etched and the predetermined thickness of the a-Si layer 14 is etched. At the same time, the n ⁺ a-Si layer 15 and the a-Si layer 14 are all etched in the third region. In this case, since the material of each layer to be etched is different, and the selectivity varies depending on the thickness or etching gas to be etched, it should be appropriately adjusted and applied to the etching process.

Referring to FIG. 1F, the photoresist film 17a is removed and a protective film 18 is deposited on the entire surface of the resultant product. Then, the photoresist film 17b is coated to form a contact hole in the second region, and a third mask process is performed.

Referring to FIG. 1G, an etching process is performed on the resultant to form a contact hole exposing a source electrode in a second region.

Referring to FIG. 1H, an ITO film 19 is deposited on the passivation layer 18, and a fourth mask process is performed to form a photoresist pattern 17c covering the second region and the third region.

Referring to FIG. 1I, the ITO film 19 is etched using the photoresist pattern 17c as an etch barrier to form a pixel electrode 19a in contact with the source electrode of the TFT.

However, since the method for manufacturing an array substrate according to the prior art as described above uses four etching masks, the process is relatively complicated, and in particular, there is a limit in reducing the manufacturing cost.

Accordingly, an object of the present invention is to provide a method for manufacturing an array substrate, which is devised to solve the above problems and can further reduce the number of etching processes.

Method of manufacturing an array substrate of the present invention for achieving the above object comprises the steps of: depositing a first metal film on a transparent insulating substrate; Patterning the first metal layer using a first mask process to form a gate electrode; Sequentially depositing a gate insulating film, an a-Si film, an n ⁺ a-Si film, a second metal film, and a protective film on the entire surface of the substrate including the gate electrode; After applying the photoresist on the passivation layer, the photoresist is exposed and developed according to a second mask process, and is divided into a first region of the channel portion, a second region of the contact portion, and a third region of the data line portion. Forming a photoresist pattern on the passivation layer, wherein a first thickness remains on the passivation layer, and a second thickness thicker than the first thickness remains on the passivation layer; Etching the passivation layer of the exposed third region using the photoresist pattern; Exposing the protective film of the first region by first applying the photoresist pattern; Etching the passivation layer of the exposed first region using the photoresist pattern to expose a second metal layer below the same, and etching the second metal layer of the third region to form a data line; Forming a source / drain electrode by etching the second metal film of the first region using the photoresist pattern, and etching the n ⁺ a-Si film and the a-Si film of the third region to form an active layer; Exposing the protective film of a second region by second etching the photoresist pattern; By using the photoresist pattern, a portion of the passivation layer in the second region is etched to form a contact hole exposing the source / drain electrodes, and a portion of the n ⁺ a-Si and a-Si layers in the first region are etched. Forming a; Removing the remaining photoresist pattern; Depositing a transparent metal film on the substrate resultant; And patterning the transparent metal film using a third mask process to form a pixel electrode in contact with the source / drain electrodes.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2J are cross-sectional views illustrating a method of manufacturing an array substrate according to an exemplary embodiment of the present invention using a 3-mask process, which will be described below.

Referring to FIG. 2A, a gate first metal film is deposited on a transparent insulating substrate, for example, a glass substrate 21, and then the gate metal is patterned by an etching process using a first etching mask. To form (22). Then, the gate insulating film 23, the undoped amorphous silicon layer 24 (hereinafter referred to as an a-Si film) and the ohmic layer are formed on the entire surface of the glass substrate 21 including the gate electrode 22. A doped amorphous silicon layer (hereinafter referred to as n ⁺ a-Si film), a second metal film 26 for forming a source / drain electrode, and a protective film 28 are deposited in this order.

Referring to FIG. 2B, a photoresist film is coated on the passivation layer 28 and a second mask process is performed to divide the photoresist pattern 27a into a first region of the channel portion, a second region of the contact portion, and a third region of the data line portion. Form. At this time, the photoresist pattern has 1/3 thickness photoresist on the passivation layer in the first region, 2/3 thickness photoresist on the passivation layer in the second region, and photoresist layer in the third region. It is patterned so that it does not remain.

Referring to FIG. 2C, the protective layer 28 of the exposed third region is etched using the photoresist pattern as an etching mask.

Referring to FIG. 2D, the photoresist pattern is first ashed to expose the passivation layer 28 of the first region.

Referring to FIG. 2E, the protective layer 28 of the first region is etched using the photoresist pattern as an etching mask to expose the second metal layer 26 below the second metal layer 26 of the third region. Is etched to form a data line.

Referring to FIG. 2F, the second metal layer 26 of the first region is etched using the photoresist pattern as an etch mask to form a source / drain electrode and an n ⁺ a-Si layer 25 of the third region. ) And the a-Si film layer 24 are etched to form an active layer.

Referring to FIG. 2G, the photoresist pattern is subjected to secondary ashing to reduce the thickness of the photoresist film on the entire surface of the substrate and to expose the protective film 28 in the second region.

Referring to FIG. 2H, the protective layer of the second region is etched using the photoresist pattern as an etch mask to form a contact hole for exposing the source / drain electrodes and the n ⁺ a-Si film 25 of the first region. ) And a portion of the a-Si film 24 are etched to form a channel layer. Thereafter, the remaining photoresist layer pattern 27a is removed.

Referring to FIG. 2I, a transparent metal film, for example, an ITO film 29 is deposited on the substrate, and a third mask process is performed to form a photoresist pattern 27b covering the second and third regions. .

Referring to FIG. 2J, the ITO layer 29 is etched using the photoresist pattern 27b as an etch barrier to form a pixel electrode 29a in contact with a source / drain electrode.

Here, in the method of forming the photoresist pattern of the second mask process, the mask process for forming the contact hole may be omitted by patterning not only the channel portion and the data line portion but also the photoresist of the contact portion.

As described above, the present invention can manufacture an array substrate using three etching masks, thereby simplifying the manufacturing process as well as reducing the manufacturing cost than conventional methods using a four-mask process.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (2)

Depositing a first metal film on the transparent insulating substrate; Patterning the first metal layer using a first mask process to form a gate electrode; Sequentially depositing a gate insulating film, an a-Si film, an n ⁺ a-Si film, a second metal film, and a protective film on the entire surface of the substrate including the gate electrode; After applying the photoresist on the passivation layer, the photoresist is exposed and developed according to a second mask process, and is divided into a first region of the channel portion, a second region of the contact portion, and a third region of the data line portion. Forming a photoresist pattern on the passivation layer, wherein a first thickness remains on the passivation layer, and a second thickness thicker than the first thickness remains on the passivation layer; Etching the passivation layer of the exposed third region using the photoresist pattern; Exposing the protective film of the first region by first applying the photoresist pattern; Etching the passivation layer of the exposed first region using the photoresist pattern to expose a second metal layer below the same, and etching the second metal layer of the third region to form a data line; Forming a source / drain electrode by etching the second metal film of the first region using the photoresist pattern, and etching the n ⁺ a-Si film and the a-Si film of the third region to form an active layer; Exposing the protective film of a second region by second etching the photoresist pattern; By using the photoresist pattern, a portion of the passivation layer in the second region is etched to form a contact hole exposing the source / drain electrodes, and a portion of the n ⁺ a-Si and a-Si layers in the first region are etched. Forming a; Removing the remaining photoresist pattern; Depositing a transparent metal film on the substrate resultant; And And patterning the transparent metal film using a third mask process to form a pixel electrode in contact with a source / drain electrode. The photoresist pattern of claim 1, wherein a photoresist having a thickness of 1/3 is left on the passivation layer in the first region, and a photoresist having a thickness of 2/3 is left on the passivation layer in the second region. 3. The method of manufacturing an array substrate of a thin film transistor liquid crystal display device, wherein the photosensitive film is formed so as not to remain in the three regions.

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